1 | /* |
2 | * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver |
3 | * |
4 | * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de> |
5 | * |
6 | * This file is subject to the terms and conditions of the GNU General |
7 | * Public License. See the file COPYING in the main directory of this |
8 | * archive for more details. |
9 | */ |
10 | |
11 | |
12 | #ifndef __SAVAGEFB_H__ |
13 | #define __SAVAGEFB_H__ |
14 | |
15 | #include <linux/i2c.h> |
16 | #include <linux/i2c-algo-bit.h> |
17 | #include <linux/mutex.h> |
18 | #include <video/vga.h> |
19 | #include "../edid.h" |
20 | |
21 | #ifdef SAVAGEFB_DEBUG |
22 | # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x)); |
23 | #else |
24 | # define DBG(x) no_printk(x) |
25 | # define SavagePrintRegs(...) |
26 | #endif |
27 | |
28 | |
29 | #define PCI_CHIP_SAVAGE4 0x8a22 |
30 | #define PCI_CHIP_SAVAGE3D 0x8a20 |
31 | #define PCI_CHIP_SAVAGE3D_MV 0x8a21 |
32 | #define PCI_CHIP_SAVAGE2000 0x9102 |
33 | #define PCI_CHIP_SAVAGE_MX_MV 0x8c10 |
34 | #define PCI_CHIP_SAVAGE_MX 0x8c11 |
35 | #define PCI_CHIP_SAVAGE_IX_MV 0x8c12 |
36 | #define PCI_CHIP_SAVAGE_IX 0x8c13 |
37 | #define PCI_CHIP_PROSAVAGE_PM 0x8a25 |
38 | #define PCI_CHIP_PROSAVAGE_KM 0x8a26 |
39 | #define PCI_CHIP_S3TWISTER_P 0x8d01 |
40 | #define PCI_CHIP_S3TWISTER_K 0x8d02 |
41 | #define PCI_CHIP_PROSAVAGE_DDR 0x8d03 |
42 | #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 |
43 | #define PCI_CHIP_SUPSAV_MX128 0x8c22 |
44 | #define PCI_CHIP_SUPSAV_MX64 0x8c24 |
45 | #define PCI_CHIP_SUPSAV_MX64C 0x8c26 |
46 | #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a |
47 | #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b |
48 | #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c |
49 | #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d |
50 | #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e |
51 | #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f |
52 | |
53 | |
54 | #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) |
55 | |
56 | #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) |
57 | |
58 | #define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR)) |
59 | |
60 | #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) |
61 | |
62 | #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR)) |
63 | |
64 | /* Chip tags. These are used to group the adapters into |
65 | * related families. |
66 | */ |
67 | |
68 | typedef enum { |
69 | S3_UNKNOWN = 0, |
70 | S3_SAVAGE3D, |
71 | S3_SAVAGE_MX, |
72 | S3_SAVAGE4, |
73 | S3_PROSAVAGE, |
74 | S3_TWISTER, |
75 | S3_PROSAVAGEDDR, |
76 | S3_SUPERSAVAGE, |
77 | S3_SAVAGE2000, |
78 | S3_LAST |
79 | } savage_chipset; |
80 | |
81 | #define BIOS_BSIZE 1024 |
82 | #define BIOS_BASE 0xc0000 |
83 | |
84 | #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ |
85 | #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 |
86 | #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ |
87 | #define SAVAGE_NEWMMIO_VGABASE 0x8000 |
88 | |
89 | #define BASE_FREQ 14318 |
90 | #define HALF_BASE_FREQ 7159 |
91 | |
92 | #define FIFO_CONTROL_REG 0x8200 |
93 | #define MIU_CONTROL_REG 0x8204 |
94 | #define STREAMS_TIMEOUT_REG 0x8208 |
95 | #define MISC_TIMEOUT_REG 0x820c |
96 | |
97 | #define MONO_PAT_0 0xa4e8 |
98 | #define MONO_PAT_1 0xa4ec |
99 | |
100 | #define MAXFIFO 0x7f00 |
101 | |
102 | #define BCI_CMD_NOP 0x40000000 |
103 | #define BCI_CMD_SETREG 0x96000000 |
104 | #define BCI_CMD_RECT 0x48000000 |
105 | #define BCI_CMD_RECT_XP 0x01000000 |
106 | #define BCI_CMD_RECT_YP 0x02000000 |
107 | #define BCI_CMD_SEND_COLOR 0x00008000 |
108 | #define BCI_CMD_DEST_GBD 0x00000000 |
109 | #define BCI_CMD_SRC_GBD 0x00000020 |
110 | #define BCI_CMD_SRC_SOLID 0x00000000 |
111 | #define BCI_CMD_SRC_MONO 0x00000060 |
112 | #define BCI_CMD_CLIP_NEW 0x00006000 |
113 | #define BCI_CMD_CLIP_LR 0x00004000 |
114 | |
115 | #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) |
116 | #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) |
117 | #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) |
118 | #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF)) |
119 | #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF)) |
120 | |
121 | #define BCI_GBD1 0xE0 |
122 | #define BCI_GBD2 0xE1 |
123 | |
124 | #define BCI_BUFFER_OFFSET 0x10000 |
125 | #define BCI_SIZE 0x4000 |
126 | |
127 | #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++) |
128 | |
129 | #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) |
130 | #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) |
131 | #define BCI_CMD_SEND_COLOR 0x00008000 |
132 | |
133 | #define DISP_CRT 1 |
134 | #define DISP_LCD 2 |
135 | #define DISP_DFP 3 |
136 | |
137 | struct xtimings { |
138 | unsigned int Clock; |
139 | unsigned int HDisplay; |
140 | unsigned int HSyncStart; |
141 | unsigned int HSyncEnd; |
142 | unsigned int HTotal; |
143 | unsigned int HAdjusted; |
144 | unsigned int VDisplay; |
145 | unsigned int VSyncStart; |
146 | unsigned int VSyncEnd; |
147 | unsigned int VTotal; |
148 | unsigned int sync; |
149 | int dblscan; |
150 | int interlaced; |
151 | }; |
152 | |
153 | struct savage_reg { |
154 | unsigned char MiscOutReg; /* Misc */ |
155 | unsigned char CRTC[25]; /* Crtc Controller */ |
156 | unsigned char Sequencer[5]; /* Video Sequencer */ |
157 | unsigned char Graphics[9]; /* Video Graphics */ |
158 | unsigned char Attribute[21]; /* Video Attribute */ |
159 | |
160 | unsigned int mode, refresh; |
161 | unsigned char SR08, SR0E, SR0F; |
162 | unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30; |
163 | unsigned char SR54[8]; |
164 | unsigned char Clock; |
165 | unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; |
166 | unsigned char CR40, CR41, CR42, CR43, CR45; |
167 | unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; |
168 | unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; |
169 | unsigned char CR86, CR88; |
170 | unsigned char CR90, CR91, CRB0; |
171 | unsigned int STREAMS[22]; /* yuck, streams regs */ |
172 | unsigned int MMPR0, MMPR1, MMPR2, MMPR3; |
173 | }; |
174 | /* --------------------------------------------------------------------- */ |
175 | |
176 | #define NR_PALETTE 256 |
177 | |
178 | |
179 | struct savagefb_par; |
180 | |
181 | struct savagefb_i2c_chan { |
182 | struct savagefb_par *par; |
183 | struct i2c_adapter adapter; |
184 | struct i2c_algo_bit_data algo; |
185 | volatile u8 __iomem *ioaddr; |
186 | u32 reg; |
187 | }; |
188 | |
189 | struct savagefb_par { |
190 | struct pci_dev *pcidev; |
191 | savage_chipset chip; |
192 | struct savagefb_i2c_chan chan; |
193 | struct savage_reg state; |
194 | struct savage_reg save; |
195 | struct savage_reg initial; |
196 | struct vgastate vgastate; |
197 | struct mutex open_lock; |
198 | u32 pseudo_palette[16]; |
199 | u32 open_count; |
200 | int paletteEnabled; |
201 | int pm_state; |
202 | int display_type; |
203 | int dvi; |
204 | int crtonly; |
205 | int dacSpeedBpp; |
206 | int maxClock; |
207 | int minClock; |
208 | int numClocks; |
209 | int clock[4]; |
210 | int MCLK, REFCLK, LCDclk; |
211 | struct { |
212 | void __iomem *vbase; |
213 | u32 pbase; |
214 | u32 len; |
215 | int wc_cookie; |
216 | } video; |
217 | |
218 | struct { |
219 | void __iomem *vbase; |
220 | u32 pbase; |
221 | u32 len; |
222 | } mmio; |
223 | |
224 | volatile u32 __iomem *bci_base; |
225 | unsigned int bci_ptr; |
226 | u32 cob_offset; |
227 | u32 cob_size; |
228 | int cob_index; |
229 | |
230 | void (*SavageWaitIdle) (struct savagefb_par *par); |
231 | void (*SavageWaitFifo) (struct savagefb_par *par, int space); |
232 | |
233 | int HorizScaleFactor; |
234 | |
235 | /* Panels size */ |
236 | int SavagePanelWidth; |
237 | int SavagePanelHeight; |
238 | |
239 | struct { |
240 | u16 red, green, blue, transp; |
241 | } palette[NR_PALETTE]; |
242 | |
243 | int depth; |
244 | int vwidth; |
245 | }; |
246 | |
247 | #define BCI_BD_BW_DISABLE 0x10000000 |
248 | #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) |
249 | #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) |
250 | |
251 | |
252 | /* IO functions */ |
253 | static inline u8 savage_in8(u32 addr, struct savagefb_par *par) |
254 | { |
255 | return readb(addr: par->mmio.vbase + addr); |
256 | } |
257 | |
258 | static inline u16 savage_in16(u32 addr, struct savagefb_par *par) |
259 | { |
260 | return readw(addr: par->mmio.vbase + addr); |
261 | } |
262 | |
263 | static inline u32 savage_in32(u32 addr, struct savagefb_par *par) |
264 | { |
265 | return readl(addr: par->mmio.vbase + addr); |
266 | } |
267 | |
268 | static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par) |
269 | { |
270 | writeb(val, addr: par->mmio.vbase + addr); |
271 | } |
272 | |
273 | static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par) |
274 | { |
275 | writew(val, addr: par->mmio.vbase + addr); |
276 | } |
277 | |
278 | static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par) |
279 | { |
280 | writel(val, addr: par->mmio.vbase + addr); |
281 | } |
282 | |
283 | static inline u8 vga_in8(int addr, struct savagefb_par *par) |
284 | { |
285 | return savage_in8(addr: 0x8000 + addr, par); |
286 | } |
287 | |
288 | static inline u16 vga_in16(int addr, struct savagefb_par *par) |
289 | { |
290 | return savage_in16(addr: 0x8000 + addr, par); |
291 | } |
292 | |
293 | static inline u8 vga_in32(int addr, struct savagefb_par *par) |
294 | { |
295 | return savage_in32(addr: 0x8000 + addr, par); |
296 | } |
297 | |
298 | static inline void vga_out8(int addr, u8 val, struct savagefb_par *par) |
299 | { |
300 | savage_out8(addr: 0x8000 + addr, val, par); |
301 | } |
302 | |
303 | static inline void vga_out16(int addr, u16 val, struct savagefb_par *par) |
304 | { |
305 | savage_out16(addr: 0x8000 + addr, val, par); |
306 | } |
307 | |
308 | static inline void vga_out32(int addr, u32 val, struct savagefb_par *par) |
309 | { |
310 | savage_out32(addr: 0x8000 + addr, val, par); |
311 | } |
312 | |
313 | static inline u8 VGArCR (u8 index, struct savagefb_par *par) |
314 | { |
315 | vga_out8(addr: 0x3d4, val: index, par); |
316 | return vga_in8(addr: 0x3d5, par); |
317 | } |
318 | |
319 | static inline u8 VGArGR (u8 index, struct savagefb_par *par) |
320 | { |
321 | vga_out8(addr: 0x3ce, val: index, par); |
322 | return vga_in8(addr: 0x3cf, par); |
323 | } |
324 | |
325 | static inline u8 VGArSEQ (u8 index, struct savagefb_par *par) |
326 | { |
327 | vga_out8(addr: 0x3c4, val: index, par); |
328 | return vga_in8(addr: 0x3c5, par); |
329 | } |
330 | |
331 | static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par) |
332 | { |
333 | vga_out8(addr: 0x3d4, val: index, par); |
334 | vga_out8(addr: 0x3d5, val, par); |
335 | } |
336 | |
337 | static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par) |
338 | { |
339 | vga_out8(addr: 0x3ce, val: index, par); |
340 | vga_out8(addr: 0x3cf, val, par); |
341 | } |
342 | |
343 | static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par) |
344 | { |
345 | vga_out8(addr: 0x3c4, val: index, par); |
346 | vga_out8 (addr: 0x3c5, val, par); |
347 | } |
348 | |
349 | static inline void VGAenablePalette(struct savagefb_par *par) |
350 | { |
351 | vga_in8(addr: 0x3da, par); |
352 | vga_out8(addr: 0x3c0, val: 0x00, par); |
353 | par->paletteEnabled = 1; |
354 | } |
355 | |
356 | static inline void VGAdisablePalette(struct savagefb_par *par) |
357 | { |
358 | vga_in8(addr: 0x3da, par); |
359 | vga_out8(addr: 0x3c0, val: 0x20, par); |
360 | par->paletteEnabled = 0; |
361 | } |
362 | |
363 | static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par) |
364 | { |
365 | if (par->paletteEnabled) |
366 | index &= ~0x20; |
367 | else |
368 | index |= 0x20; |
369 | |
370 | vga_in8(addr: 0x3da, par); |
371 | vga_out8(addr: 0x3c0, val: index, par); |
372 | vga_out8 (addr: 0x3c0, val: value, par); |
373 | } |
374 | |
375 | static inline void VGAwMISC(u8 value, struct savagefb_par *par) |
376 | { |
377 | vga_out8(addr: 0x3c2, val: value, par); |
378 | } |
379 | |
380 | #ifndef CONFIG_FB_SAVAGE_ACCEL |
381 | #define savagefb_set_clip(x) |
382 | #endif |
383 | |
384 | static inline void VerticalRetraceWait(struct savagefb_par *par) |
385 | { |
386 | vga_out8(addr: 0x3d4, val: 0x17, par); |
387 | if (vga_in8(addr: 0x3d5, par) & 0x80) { |
388 | while ((vga_in8(addr: 0x3da, par) & 0x08) == 0x08); |
389 | while ((vga_in8(addr: 0x3da, par) & 0x08) == 0x00); |
390 | } |
391 | } |
392 | |
393 | extern int savagefb_probe_i2c_connector(struct fb_info *info, |
394 | u8 **out_edid); |
395 | extern void savagefb_create_i2c_busses(struct fb_info *info); |
396 | extern void savagefb_delete_i2c_busses(struct fb_info *info); |
397 | extern int savagefb_sync(struct fb_info *info); |
398 | extern void savagefb_copyarea(struct fb_info *info, |
399 | const struct fb_copyarea *region); |
400 | extern void savagefb_fillrect(struct fb_info *info, |
401 | const struct fb_fillrect *rect); |
402 | extern void savagefb_imageblit(struct fb_info *info, |
403 | const struct fb_image *image); |
404 | |
405 | |
406 | #endif /* __SAVAGEFB_H__ */ |
407 | |