1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * HPE WatchDog Driver |
4 | * based on |
5 | * |
6 | * SoftDog 0.05: A Software Watchdog Device |
7 | * |
8 | * (c) Copyright 2018 Hewlett Packard Enterprise Development LP |
9 | * Thomas Mingarelli <thomas.mingarelli@hpe.com> |
10 | */ |
11 | |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
13 | |
14 | #include <linux/device.h> |
15 | #include <linux/io.h> |
16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> |
18 | #include <linux/moduleparam.h> |
19 | #include <linux/pci.h> |
20 | #include <linux/pci_ids.h> |
21 | #include <linux/types.h> |
22 | #include <linux/watchdog.h> |
23 | #ifdef CONFIG_HPWDT_NMI_DECODING |
24 | #include <asm/nmi.h> |
25 | #endif |
26 | #include <linux/crash_dump.h> |
27 | |
28 | #define HPWDT_VERSION "2.0.4" |
29 | #define SECS_TO_TICKS(secs) ((secs) * 1000 / 128) |
30 | #define TICKS_TO_SECS(ticks) ((ticks) * 128 / 1000) |
31 | #define HPWDT_MAX_TICKS 65535 |
32 | #define HPWDT_MAX_TIMER TICKS_TO_SECS(HPWDT_MAX_TICKS) |
33 | #define DEFAULT_MARGIN 30 |
34 | #define PRETIMEOUT_SEC 9 |
35 | |
36 | static bool ilo5; |
37 | static unsigned int soft_margin = DEFAULT_MARGIN; /* in seconds */ |
38 | static bool nowayout = WATCHDOG_NOWAYOUT; |
39 | static bool pretimeout = IS_ENABLED(CONFIG_HPWDT_NMI_DECODING); |
40 | static int kdumptimeout = -1; |
41 | |
42 | static void __iomem *pci_mem_addr; /* the PCI-memory address */ |
43 | static unsigned long __iomem *hpwdt_nmistat; |
44 | static unsigned long __iomem *hpwdt_timer_reg; |
45 | static unsigned long __iomem *hpwdt_timer_con; |
46 | |
47 | static const struct pci_device_id hpwdt_devices[] = { |
48 | { PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xB203) }, /* iLO2 */ |
49 | { PCI_DEVICE(PCI_VENDOR_ID_HP, 0x3306) }, /* iLO3 */ |
50 | { PCI_DEVICE(PCI_VENDOR_ID_HP_3PAR, 0x0389) }, /* PCtrl */ |
51 | {0}, /* terminate list */ |
52 | }; |
53 | MODULE_DEVICE_TABLE(pci, hpwdt_devices); |
54 | |
55 | static const struct pci_device_id hpwdt_blacklist[] = { |
56 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP, 0x3306, PCI_VENDOR_ID_HP, 0x1979) }, /* auxilary iLO */ |
57 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP, 0x3306, PCI_VENDOR_ID_HP_3PAR, 0x0289) }, /* CL */ |
58 | {0}, /* terminate list */ |
59 | }; |
60 | |
61 | static struct watchdog_device hpwdt_dev; |
62 | /* |
63 | * Watchdog operations |
64 | */ |
65 | static int hpwdt_hw_is_running(void) |
66 | { |
67 | return ioread8(hpwdt_timer_con) & 0x01; |
68 | } |
69 | |
70 | static int hpwdt_start(struct watchdog_device *wdd) |
71 | { |
72 | int control = 0x81 | (pretimeout ? 0x4 : 0); |
73 | int reload = SECS_TO_TICKS(min(wdd->timeout, wdd->max_hw_heartbeat_ms/1000)); |
74 | |
75 | dev_dbg(wdd->parent, "start watchdog 0x%08x:0x%08x:0x%02x\n" , wdd->timeout, reload, control); |
76 | iowrite16(reload, hpwdt_timer_reg); |
77 | iowrite8(control, hpwdt_timer_con); |
78 | |
79 | return 0; |
80 | } |
81 | |
82 | static void hpwdt_stop(void) |
83 | { |
84 | unsigned long data; |
85 | |
86 | pr_debug("stop watchdog\n" ); |
87 | |
88 | data = ioread8(hpwdt_timer_con); |
89 | data &= 0xFE; |
90 | iowrite8(data, hpwdt_timer_con); |
91 | } |
92 | |
93 | static int hpwdt_stop_core(struct watchdog_device *wdd) |
94 | { |
95 | hpwdt_stop(); |
96 | |
97 | return 0; |
98 | } |
99 | |
100 | static void hpwdt_ping_ticks(int val) |
101 | { |
102 | val = min(val, HPWDT_MAX_TICKS); |
103 | iowrite16(val, hpwdt_timer_reg); |
104 | } |
105 | |
106 | static int hpwdt_ping(struct watchdog_device *wdd) |
107 | { |
108 | int reload = SECS_TO_TICKS(min(wdd->timeout, wdd->max_hw_heartbeat_ms/1000)); |
109 | |
110 | dev_dbg(wdd->parent, "ping watchdog 0x%08x:0x%08x\n" , wdd->timeout, reload); |
111 | hpwdt_ping_ticks(val: reload); |
112 | |
113 | return 0; |
114 | } |
115 | |
116 | static unsigned int hpwdt_gettimeleft(struct watchdog_device *wdd) |
117 | { |
118 | return TICKS_TO_SECS(ioread16(hpwdt_timer_reg)); |
119 | } |
120 | |
121 | static int hpwdt_settimeout(struct watchdog_device *wdd, unsigned int val) |
122 | { |
123 | dev_dbg(wdd->parent, "set_timeout = %d\n" , val); |
124 | |
125 | wdd->timeout = val; |
126 | if (val <= wdd->pretimeout) { |
127 | dev_dbg(wdd->parent, "pretimeout < timeout. Setting to zero\n" ); |
128 | wdd->pretimeout = 0; |
129 | pretimeout = false; |
130 | if (watchdog_active(wdd)) |
131 | hpwdt_start(wdd); |
132 | } |
133 | hpwdt_ping(wdd); |
134 | |
135 | return 0; |
136 | } |
137 | |
138 | #ifdef CONFIG_HPWDT_NMI_DECODING |
139 | static int hpwdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req) |
140 | { |
141 | unsigned int val = 0; |
142 | |
143 | dev_dbg(wdd->parent, "set_pretimeout = %d\n" , req); |
144 | if (req) { |
145 | val = PRETIMEOUT_SEC; |
146 | if (val >= wdd->timeout) |
147 | return -EINVAL; |
148 | } |
149 | |
150 | if (val != req) |
151 | dev_dbg(wdd->parent, "Rounding pretimeout to: %d\n" , val); |
152 | |
153 | wdd->pretimeout = val; |
154 | pretimeout = !!val; |
155 | |
156 | if (watchdog_active(wdd)) |
157 | hpwdt_start(wdd); |
158 | |
159 | return 0; |
160 | } |
161 | |
162 | static int hpwdt_my_nmi(void) |
163 | { |
164 | return ioread8(hpwdt_nmistat) & 0x6; |
165 | } |
166 | |
167 | /* |
168 | * NMI Handler |
169 | */ |
170 | static int hpwdt_pretimeout(unsigned int ulReason, struct pt_regs *regs) |
171 | { |
172 | unsigned int mynmi = hpwdt_my_nmi(); |
173 | static char panic_msg[] = |
174 | "00: An NMI occurred. Depending on your system the reason " |
175 | "for the NMI is logged in any one of the following resources:\n" |
176 | "1. Integrated Management Log (IML)\n" |
177 | "2. OA Syslog\n" |
178 | "3. OA Forward Progress Log\n" |
179 | "4. iLO Event Log" ; |
180 | |
181 | if (ilo5 && ulReason == NMI_UNKNOWN && !mynmi) |
182 | return NMI_DONE; |
183 | |
184 | if (ilo5 && !pretimeout && !mynmi) |
185 | return NMI_DONE; |
186 | |
187 | if (kdumptimeout < 0) |
188 | hpwdt_stop(); |
189 | else if (kdumptimeout == 0) |
190 | ; |
191 | else { |
192 | unsigned int val = max((unsigned int)kdumptimeout, hpwdt_dev.timeout); |
193 | hpwdt_ping_ticks(SECS_TO_TICKS(val)); |
194 | } |
195 | |
196 | hex_byte_pack(buf: panic_msg, byte: mynmi); |
197 | nmi_panic(regs, msg: panic_msg); |
198 | |
199 | return NMI_HANDLED; |
200 | } |
201 | #endif /* CONFIG_HPWDT_NMI_DECODING */ |
202 | |
203 | |
204 | static const struct watchdog_info ident = { |
205 | .options = WDIOF_PRETIMEOUT | |
206 | WDIOF_SETTIMEOUT | |
207 | WDIOF_KEEPALIVEPING | |
208 | WDIOF_MAGICCLOSE, |
209 | .identity = "HPE iLO2+ HW Watchdog Timer" , |
210 | }; |
211 | |
212 | /* |
213 | * Kernel interfaces |
214 | */ |
215 | |
216 | static const struct watchdog_ops hpwdt_ops = { |
217 | .owner = THIS_MODULE, |
218 | .start = hpwdt_start, |
219 | .stop = hpwdt_stop_core, |
220 | .ping = hpwdt_ping, |
221 | .set_timeout = hpwdt_settimeout, |
222 | .get_timeleft = hpwdt_gettimeleft, |
223 | #ifdef CONFIG_HPWDT_NMI_DECODING |
224 | .set_pretimeout = hpwdt_set_pretimeout, |
225 | #endif |
226 | }; |
227 | |
228 | static struct watchdog_device hpwdt_dev = { |
229 | .info = &ident, |
230 | .ops = &hpwdt_ops, |
231 | .min_timeout = 1, |
232 | .timeout = DEFAULT_MARGIN, |
233 | .pretimeout = PRETIMEOUT_SEC, |
234 | .max_hw_heartbeat_ms = HPWDT_MAX_TIMER * 1000, |
235 | }; |
236 | |
237 | |
238 | /* |
239 | * Init & Exit |
240 | */ |
241 | |
242 | static int hpwdt_init_nmi_decoding(struct pci_dev *dev) |
243 | { |
244 | #ifdef CONFIG_HPWDT_NMI_DECODING |
245 | int retval; |
246 | /* |
247 | * Only one function can register for NMI_UNKNOWN |
248 | */ |
249 | retval = register_nmi_handler(NMI_UNKNOWN, hpwdt_pretimeout, 0, "hpwdt" ); |
250 | if (retval) |
251 | goto error; |
252 | retval = register_nmi_handler(NMI_SERR, hpwdt_pretimeout, 0, "hpwdt" ); |
253 | if (retval) |
254 | goto error1; |
255 | retval = register_nmi_handler(NMI_IO_CHECK, hpwdt_pretimeout, 0, "hpwdt" ); |
256 | if (retval) |
257 | goto error2; |
258 | |
259 | dev_info(&dev->dev, |
260 | "HPE Watchdog Timer Driver: NMI decoding initialized\n" ); |
261 | |
262 | return 0; |
263 | |
264 | error2: |
265 | unregister_nmi_handler(NMI_SERR, "hpwdt" ); |
266 | error1: |
267 | unregister_nmi_handler(NMI_UNKNOWN, "hpwdt" ); |
268 | error: |
269 | dev_warn(&dev->dev, |
270 | "Unable to register a die notifier (err=%d).\n" , |
271 | retval); |
272 | return retval; |
273 | #endif /* CONFIG_HPWDT_NMI_DECODING */ |
274 | return 0; |
275 | } |
276 | |
277 | static void hpwdt_exit_nmi_decoding(void) |
278 | { |
279 | #ifdef CONFIG_HPWDT_NMI_DECODING |
280 | unregister_nmi_handler(NMI_UNKNOWN, "hpwdt" ); |
281 | unregister_nmi_handler(NMI_SERR, "hpwdt" ); |
282 | unregister_nmi_handler(NMI_IO_CHECK, "hpwdt" ); |
283 | #endif |
284 | } |
285 | |
286 | static int hpwdt_init_one(struct pci_dev *dev, |
287 | const struct pci_device_id *ent) |
288 | { |
289 | int retval; |
290 | |
291 | /* |
292 | * First let's find out if we are on an iLO2+ server. We will |
293 | * not run on a legacy ASM box. |
294 | * So we only support the G5 ProLiant servers and higher. |
295 | */ |
296 | if (dev->subsystem_vendor != PCI_VENDOR_ID_HP && |
297 | dev->subsystem_vendor != PCI_VENDOR_ID_HP_3PAR) { |
298 | dev_warn(&dev->dev, |
299 | "This server does not have an iLO2+ ASIC.\n" ); |
300 | return -ENODEV; |
301 | } |
302 | |
303 | if (pci_match_id(ids: hpwdt_blacklist, dev)) { |
304 | dev_dbg(&dev->dev, "Not supported on this device\n" ); |
305 | return -ENODEV; |
306 | } |
307 | |
308 | if (pci_enable_device(dev)) { |
309 | dev_warn(&dev->dev, |
310 | "Not possible to enable PCI Device: 0x%x:0x%x.\n" , |
311 | ent->vendor, ent->device); |
312 | return -ENODEV; |
313 | } |
314 | |
315 | pci_mem_addr = pci_iomap(dev, bar: 1, max: 0x80); |
316 | if (!pci_mem_addr) { |
317 | dev_warn(&dev->dev, |
318 | "Unable to detect the iLO2+ server memory.\n" ); |
319 | retval = -ENOMEM; |
320 | goto error_pci_iomap; |
321 | } |
322 | hpwdt_nmistat = pci_mem_addr + 0x6e; |
323 | hpwdt_timer_reg = pci_mem_addr + 0x70; |
324 | hpwdt_timer_con = pci_mem_addr + 0x72; |
325 | |
326 | /* Have the core update running timer until user space is ready */ |
327 | if (hpwdt_hw_is_running()) { |
328 | dev_info(&dev->dev, "timer is running\n" ); |
329 | set_bit(WDOG_HW_RUNNING, addr: &hpwdt_dev.status); |
330 | } |
331 | |
332 | /* Initialize NMI Decoding functionality */ |
333 | retval = hpwdt_init_nmi_decoding(dev); |
334 | if (retval != 0) |
335 | goto error_init_nmi_decoding; |
336 | |
337 | watchdog_stop_on_unregister(wdd: &hpwdt_dev); |
338 | watchdog_set_nowayout(wdd: &hpwdt_dev, nowayout); |
339 | watchdog_init_timeout(wdd: &hpwdt_dev, timeout_parm: soft_margin, NULL); |
340 | |
341 | if (is_kdump_kernel()) { |
342 | pretimeout = false; |
343 | kdumptimeout = 0; |
344 | } |
345 | |
346 | if (pretimeout && hpwdt_dev.timeout <= PRETIMEOUT_SEC) { |
347 | dev_warn(&dev->dev, "timeout <= pretimeout. Setting pretimeout to zero\n" ); |
348 | pretimeout = false; |
349 | } |
350 | hpwdt_dev.pretimeout = pretimeout ? PRETIMEOUT_SEC : 0; |
351 | kdumptimeout = min(kdumptimeout, HPWDT_MAX_TIMER); |
352 | |
353 | hpwdt_dev.parent = &dev->dev; |
354 | retval = watchdog_register_device(&hpwdt_dev); |
355 | if (retval < 0) |
356 | goto error_wd_register; |
357 | |
358 | dev_info(&dev->dev, "HPE Watchdog Timer Driver: Version: %s\n" , |
359 | HPWDT_VERSION); |
360 | dev_info(&dev->dev, "timeout: %d seconds (nowayout=%d)\n" , |
361 | hpwdt_dev.timeout, nowayout); |
362 | dev_info(&dev->dev, "pretimeout: %s.\n" , |
363 | pretimeout ? "on" : "off" ); |
364 | dev_info(&dev->dev, "kdumptimeout: %d.\n" , kdumptimeout); |
365 | |
366 | if (dev->subsystem_vendor == PCI_VENDOR_ID_HP_3PAR) |
367 | ilo5 = true; |
368 | |
369 | return 0; |
370 | |
371 | error_wd_register: |
372 | hpwdt_exit_nmi_decoding(); |
373 | error_init_nmi_decoding: |
374 | pci_iounmap(dev, pci_mem_addr); |
375 | error_pci_iomap: |
376 | pci_disable_device(dev); |
377 | return retval; |
378 | } |
379 | |
380 | static void hpwdt_exit(struct pci_dev *dev) |
381 | { |
382 | watchdog_unregister_device(&hpwdt_dev); |
383 | hpwdt_exit_nmi_decoding(); |
384 | pci_iounmap(dev, pci_mem_addr); |
385 | pci_disable_device(dev); |
386 | } |
387 | |
388 | static struct pci_driver hpwdt_driver = { |
389 | .name = "hpwdt" , |
390 | .id_table = hpwdt_devices, |
391 | .probe = hpwdt_init_one, |
392 | .remove = hpwdt_exit, |
393 | }; |
394 | |
395 | MODULE_AUTHOR("Tom Mingarelli" ); |
396 | MODULE_DESCRIPTION("hpe watchdog driver" ); |
397 | MODULE_LICENSE("GPL" ); |
398 | MODULE_VERSION(HPWDT_VERSION); |
399 | |
400 | module_param(soft_margin, int, 0); |
401 | MODULE_PARM_DESC(soft_margin, "Watchdog timeout in seconds" ); |
402 | |
403 | module_param_named(timeout, soft_margin, int, 0); |
404 | MODULE_PARM_DESC(timeout, "Alias of soft_margin" ); |
405 | |
406 | module_param(nowayout, bool, 0); |
407 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
408 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")" ); |
409 | |
410 | module_param(kdumptimeout, int, 0444); |
411 | MODULE_PARM_DESC(kdumptimeout, "Timeout applied for crash kernel transition in seconds" ); |
412 | |
413 | #ifdef CONFIG_HPWDT_NMI_DECODING |
414 | module_param(pretimeout, bool, 0); |
415 | MODULE_PARM_DESC(pretimeout, "Watchdog pretimeout enabled" ); |
416 | #endif |
417 | |
418 | module_pci_driver(hpwdt_driver); |
419 | |