| 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Ralink MT7621/MT7628 built-in hardware watchdog timer |
| 4 | * |
| 5 | * Copyright (C) 2014 John Crispin <john@phrozen.org> |
| 6 | * |
| 7 | * This driver was based on: drivers/watchdog/rt2880_wdt.c |
| 8 | */ |
| 9 | |
| 10 | #include <linux/clk.h> |
| 11 | #include <linux/reset.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/watchdog.h> |
| 15 | #include <linux/moduleparam.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/mod_devicetable.h> |
| 18 | #include <linux/mfd/syscon.h> |
| 19 | #include <linux/regmap.h> |
| 20 | |
| 21 | #define SYSC_RSTSTAT 0x38 |
| 22 | #define WDT_RST_CAUSE BIT(1) |
| 23 | |
| 24 | #define RALINK_WDT_TIMEOUT 30 |
| 25 | |
| 26 | #define TIMER_REG_TMRSTAT 0x00 |
| 27 | #define TIMER_REG_TMR1LOAD 0x24 |
| 28 | #define TIMER_REG_TMR1CTL 0x20 |
| 29 | |
| 30 | #define TMR1CTL_ENABLE BIT(7) |
| 31 | #define TMR1CTL_RESTART BIT(9) |
| 32 | #define TMR1CTL_PRESCALE_SHIFT 16 |
| 33 | |
| 34 | struct mt7621_wdt_data { |
| 35 | void __iomem *base; |
| 36 | struct reset_control *rst; |
| 37 | struct regmap *sysc; |
| 38 | struct watchdog_device wdt; |
| 39 | }; |
| 40 | |
| 41 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 42 | module_param(nowayout, bool, 0); |
| 43 | MODULE_PARM_DESC(nowayout, |
| 44 | "Watchdog cannot be stopped once started (default=" |
| 45 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")" ); |
| 46 | |
| 47 | static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val) |
| 48 | { |
| 49 | iowrite32(val, base + reg); |
| 50 | } |
| 51 | |
| 52 | static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg) |
| 53 | { |
| 54 | return ioread32(base + reg); |
| 55 | } |
| 56 | |
| 57 | static int mt7621_wdt_ping(struct watchdog_device *w) |
| 58 | { |
| 59 | struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(wdd: w); |
| 60 | |
| 61 | rt_wdt_w32(base: drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) |
| 67 | { |
| 68 | struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(wdd: w); |
| 69 | |
| 70 | w->timeout = t; |
| 71 | rt_wdt_w32(base: drvdata->base, TIMER_REG_TMR1LOAD, val: t * 1000); |
| 72 | mt7621_wdt_ping(w); |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static int mt7621_wdt_start(struct watchdog_device *w) |
| 78 | { |
| 79 | struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(wdd: w); |
| 80 | u32 t; |
| 81 | |
| 82 | /* set the prescaler to 1ms == 1000us */ |
| 83 | rt_wdt_w32(base: drvdata->base, TIMER_REG_TMR1CTL, val: 1000 << TMR1CTL_PRESCALE_SHIFT); |
| 84 | |
| 85 | mt7621_wdt_set_timeout(w, t: w->timeout); |
| 86 | |
| 87 | t = rt_wdt_r32(base: drvdata->base, TIMER_REG_TMR1CTL); |
| 88 | t |= TMR1CTL_ENABLE; |
| 89 | rt_wdt_w32(base: drvdata->base, TIMER_REG_TMR1CTL, val: t); |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | static int mt7621_wdt_stop(struct watchdog_device *w) |
| 95 | { |
| 96 | struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(wdd: w); |
| 97 | u32 t; |
| 98 | |
| 99 | mt7621_wdt_ping(w); |
| 100 | |
| 101 | t = rt_wdt_r32(base: drvdata->base, TIMER_REG_TMR1CTL); |
| 102 | t &= ~TMR1CTL_ENABLE; |
| 103 | rt_wdt_w32(base: drvdata->base, TIMER_REG_TMR1CTL, val: t); |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d) |
| 109 | { |
| 110 | u32 val; |
| 111 | |
| 112 | regmap_read(map: d->sysc, SYSC_RSTSTAT, val: &val); |
| 113 | if (val & WDT_RST_CAUSE) |
| 114 | return WDIOF_CARDRESET; |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | static int mt7621_wdt_is_running(struct watchdog_device *w) |
| 120 | { |
| 121 | struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(wdd: w); |
| 122 | |
| 123 | return !!(rt_wdt_r32(base: drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); |
| 124 | } |
| 125 | |
| 126 | static const struct watchdog_info mt7621_wdt_info = { |
| 127 | .identity = "Mediatek Watchdog" , |
| 128 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, |
| 129 | }; |
| 130 | |
| 131 | static const struct watchdog_ops mt7621_wdt_ops = { |
| 132 | .owner = THIS_MODULE, |
| 133 | .start = mt7621_wdt_start, |
| 134 | .stop = mt7621_wdt_stop, |
| 135 | .ping = mt7621_wdt_ping, |
| 136 | .set_timeout = mt7621_wdt_set_timeout, |
| 137 | }; |
| 138 | |
| 139 | static int mt7621_wdt_probe(struct platform_device *pdev) |
| 140 | { |
| 141 | struct device_node *np = pdev->dev.of_node; |
| 142 | struct device *dev = &pdev->dev; |
| 143 | struct watchdog_device *mt7621_wdt; |
| 144 | struct mt7621_wdt_data *drvdata; |
| 145 | int err; |
| 146 | |
| 147 | drvdata = devm_kzalloc(dev, size: sizeof(*drvdata), GFP_KERNEL); |
| 148 | if (!drvdata) |
| 149 | return -ENOMEM; |
| 150 | |
| 151 | drvdata->sysc = syscon_regmap_lookup_by_phandle(np, property: "mediatek,sysctl" ); |
| 152 | if (IS_ERR(ptr: drvdata->sysc)) { |
| 153 | drvdata->sysc = syscon_regmap_lookup_by_compatible(s: "mediatek,mt7621-sysc" ); |
| 154 | if (IS_ERR(ptr: drvdata->sysc)) |
| 155 | return PTR_ERR(ptr: drvdata->sysc); |
| 156 | } |
| 157 | |
| 158 | drvdata->base = devm_platform_ioremap_resource(pdev, index: 0); |
| 159 | if (IS_ERR(ptr: drvdata->base)) |
| 160 | return PTR_ERR(ptr: drvdata->base); |
| 161 | |
| 162 | drvdata->rst = devm_reset_control_get_exclusive(dev, NULL); |
| 163 | if (!IS_ERR(ptr: drvdata->rst)) |
| 164 | reset_control_deassert(rstc: drvdata->rst); |
| 165 | |
| 166 | mt7621_wdt = &drvdata->wdt; |
| 167 | mt7621_wdt->info = &mt7621_wdt_info; |
| 168 | mt7621_wdt->ops = &mt7621_wdt_ops; |
| 169 | mt7621_wdt->min_timeout = 1; |
| 170 | mt7621_wdt->max_timeout = 0xfffful / 1000; |
| 171 | mt7621_wdt->parent = dev; |
| 172 | |
| 173 | mt7621_wdt->bootstatus = mt7621_wdt_bootcause(d: drvdata); |
| 174 | |
| 175 | watchdog_init_timeout(wdd: mt7621_wdt, timeout_parm: mt7621_wdt->max_timeout, dev); |
| 176 | watchdog_set_nowayout(wdd: mt7621_wdt, nowayout); |
| 177 | watchdog_set_drvdata(wdd: mt7621_wdt, data: drvdata); |
| 178 | |
| 179 | if (mt7621_wdt_is_running(w: mt7621_wdt)) { |
| 180 | /* |
| 181 | * Make sure to apply timeout from watchdog core, taking |
| 182 | * the prescaler of this driver here into account (the |
| 183 | * boot loader might be using a different prescaler). |
| 184 | * |
| 185 | * To avoid spurious resets because of different scaling, |
| 186 | * we first disable the watchdog, set the new prescaler |
| 187 | * and timeout, and then re-enable the watchdog. |
| 188 | */ |
| 189 | mt7621_wdt_stop(w: mt7621_wdt); |
| 190 | mt7621_wdt_start(w: mt7621_wdt); |
| 191 | set_bit(WDOG_HW_RUNNING, addr: &mt7621_wdt->status); |
| 192 | } |
| 193 | |
| 194 | err = devm_watchdog_register_device(dev, &drvdata->wdt); |
| 195 | if (err) |
| 196 | return err; |
| 197 | |
| 198 | platform_set_drvdata(pdev, data: drvdata); |
| 199 | |
| 200 | return 0; |
| 201 | } |
| 202 | |
| 203 | static void mt7621_wdt_shutdown(struct platform_device *pdev) |
| 204 | { |
| 205 | struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev); |
| 206 | |
| 207 | mt7621_wdt_stop(w: &drvdata->wdt); |
| 208 | } |
| 209 | |
| 210 | static const struct of_device_id mt7621_wdt_match[] = { |
| 211 | { .compatible = "mediatek,mt7621-wdt" }, |
| 212 | {}, |
| 213 | }; |
| 214 | MODULE_DEVICE_TABLE(of, mt7621_wdt_match); |
| 215 | |
| 216 | static struct platform_driver mt7621_wdt_driver = { |
| 217 | .probe = mt7621_wdt_probe, |
| 218 | .shutdown = mt7621_wdt_shutdown, |
| 219 | .driver = { |
| 220 | .name = KBUILD_MODNAME, |
| 221 | .of_match_table = mt7621_wdt_match, |
| 222 | }, |
| 223 | }; |
| 224 | |
| 225 | module_platform_driver(mt7621_wdt_driver); |
| 226 | |
| 227 | MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver" ); |
| 228 | MODULE_AUTHOR("John Crispin <john@phrozen.org" ); |
| 229 | MODULE_LICENSE("GPL v2" ); |
| 230 | |