1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Watchdog driver for the UniPhier watchdog timer |
4 | * |
5 | * (c) Copyright 2014 Panasonic Corporation |
6 | * (c) Copyright 2016 Socionext Inc. |
7 | * All rights reserved. |
8 | */ |
9 | |
10 | #include <linux/bitops.h> |
11 | #include <linux/mfd/syscon.h> |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/regmap.h> |
16 | #include <linux/watchdog.h> |
17 | |
18 | /* WDT timer setting register */ |
19 | #define WDTTIMSET 0x3004 |
20 | #define WDTTIMSET_PERIOD_MASK (0xf << 0) |
21 | #define WDTTIMSET_PERIOD_1_SEC (0x3 << 0) |
22 | |
23 | /* WDT reset selection register */ |
24 | #define WDTRSTSEL 0x3008 |
25 | #define WDTRSTSEL_RSTSEL_MASK (0x3 << 0) |
26 | #define WDTRSTSEL_RSTSEL_BOTH (0x0 << 0) |
27 | #define WDTRSTSEL_RSTSEL_IRQ_ONLY (0x2 << 0) |
28 | |
29 | /* WDT control register */ |
30 | #define WDTCTRL 0x300c |
31 | #define WDTCTRL_STATUS BIT(8) |
32 | #define WDTCTRL_CLEAR BIT(1) |
33 | #define WDTCTRL_ENABLE BIT(0) |
34 | |
35 | #define SEC_TO_WDTTIMSET_PRD(sec) \ |
36 | (ilog2(sec) + WDTTIMSET_PERIOD_1_SEC) |
37 | |
38 | #define WDTST_TIMEOUT 1000 /* usec */ |
39 | |
40 | #define WDT_DEFAULT_TIMEOUT 64 /* Default is 64 seconds */ |
41 | #define WDT_PERIOD_MIN 1 |
42 | #define WDT_PERIOD_MAX 128 |
43 | |
44 | static unsigned int timeout = 0; |
45 | static bool nowayout = WATCHDOG_NOWAYOUT; |
46 | |
47 | struct uniphier_wdt_dev { |
48 | struct watchdog_device wdt_dev; |
49 | struct regmap *regmap; |
50 | }; |
51 | |
52 | /* |
53 | * UniPhier Watchdog operations |
54 | */ |
55 | static int uniphier_watchdog_ping(struct watchdog_device *w) |
56 | { |
57 | struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(wdd: w); |
58 | unsigned int val; |
59 | int ret; |
60 | |
61 | /* Clear counter */ |
62 | ret = regmap_write_bits(map: wdev->regmap, WDTCTRL, |
63 | WDTCTRL_CLEAR, WDTCTRL_CLEAR); |
64 | if (!ret) |
65 | /* |
66 | * As SoC specification, after clear counter, |
67 | * it needs to wait until counter status is 1. |
68 | */ |
69 | ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val, |
70 | (val & WDTCTRL_STATUS), |
71 | 0, WDTST_TIMEOUT); |
72 | |
73 | return ret; |
74 | } |
75 | |
76 | static int __uniphier_watchdog_start(struct regmap *regmap, unsigned int sec) |
77 | { |
78 | unsigned int val; |
79 | int ret; |
80 | |
81 | ret = regmap_read_poll_timeout(regmap, WDTCTRL, val, |
82 | !(val & WDTCTRL_STATUS), |
83 | 0, WDTST_TIMEOUT); |
84 | if (ret) |
85 | return ret; |
86 | |
87 | /* Setup period */ |
88 | ret = regmap_write(map: regmap, WDTTIMSET, |
89 | SEC_TO_WDTTIMSET_PRD(sec)); |
90 | if (ret) |
91 | return ret; |
92 | |
93 | /* Enable and clear watchdog */ |
94 | ret = regmap_write(map: regmap, WDTCTRL, WDTCTRL_ENABLE | WDTCTRL_CLEAR); |
95 | if (!ret) |
96 | /* |
97 | * As SoC specification, after clear counter, |
98 | * it needs to wait until counter status is 1. |
99 | */ |
100 | ret = regmap_read_poll_timeout(regmap, WDTCTRL, val, |
101 | (val & WDTCTRL_STATUS), |
102 | 0, WDTST_TIMEOUT); |
103 | |
104 | return ret; |
105 | } |
106 | |
107 | static int __uniphier_watchdog_stop(struct regmap *regmap) |
108 | { |
109 | /* Disable and stop watchdog */ |
110 | return regmap_write_bits(map: regmap, WDTCTRL, WDTCTRL_ENABLE, val: 0); |
111 | } |
112 | |
113 | static int __uniphier_watchdog_restart(struct regmap *regmap, unsigned int sec) |
114 | { |
115 | int ret; |
116 | |
117 | ret = __uniphier_watchdog_stop(regmap); |
118 | if (ret) |
119 | return ret; |
120 | |
121 | return __uniphier_watchdog_start(regmap, sec); |
122 | } |
123 | |
124 | static int uniphier_watchdog_start(struct watchdog_device *w) |
125 | { |
126 | struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(wdd: w); |
127 | unsigned int tmp_timeout; |
128 | |
129 | tmp_timeout = roundup_pow_of_two(w->timeout); |
130 | |
131 | return __uniphier_watchdog_start(regmap: wdev->regmap, sec: tmp_timeout); |
132 | } |
133 | |
134 | static int uniphier_watchdog_stop(struct watchdog_device *w) |
135 | { |
136 | struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(wdd: w); |
137 | |
138 | return __uniphier_watchdog_stop(regmap: wdev->regmap); |
139 | } |
140 | |
141 | static int uniphier_watchdog_set_timeout(struct watchdog_device *w, |
142 | unsigned int t) |
143 | { |
144 | struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(wdd: w); |
145 | unsigned int tmp_timeout; |
146 | int ret; |
147 | |
148 | tmp_timeout = roundup_pow_of_two(t); |
149 | if (tmp_timeout == w->timeout) |
150 | return 0; |
151 | |
152 | if (watchdog_active(wdd: w)) { |
153 | ret = __uniphier_watchdog_restart(regmap: wdev->regmap, sec: tmp_timeout); |
154 | if (ret) |
155 | return ret; |
156 | } |
157 | |
158 | w->timeout = tmp_timeout; |
159 | |
160 | return 0; |
161 | } |
162 | |
163 | /* |
164 | * Kernel Interfaces |
165 | */ |
166 | static const struct watchdog_info uniphier_wdt_info = { |
167 | .identity = "uniphier-wdt" , |
168 | .options = WDIOF_SETTIMEOUT | |
169 | WDIOF_KEEPALIVEPING | |
170 | WDIOF_MAGICCLOSE | |
171 | WDIOF_OVERHEAT, |
172 | }; |
173 | |
174 | static const struct watchdog_ops uniphier_wdt_ops = { |
175 | .owner = THIS_MODULE, |
176 | .start = uniphier_watchdog_start, |
177 | .stop = uniphier_watchdog_stop, |
178 | .ping = uniphier_watchdog_ping, |
179 | .set_timeout = uniphier_watchdog_set_timeout, |
180 | }; |
181 | |
182 | static int uniphier_wdt_probe(struct platform_device *pdev) |
183 | { |
184 | struct device *dev = &pdev->dev; |
185 | struct uniphier_wdt_dev *wdev; |
186 | struct regmap *regmap; |
187 | struct device_node *parent; |
188 | int ret; |
189 | |
190 | wdev = devm_kzalloc(dev, size: sizeof(*wdev), GFP_KERNEL); |
191 | if (!wdev) |
192 | return -ENOMEM; |
193 | |
194 | parent = of_get_parent(node: dev->of_node); /* parent should be syscon node */ |
195 | regmap = syscon_node_to_regmap(np: parent); |
196 | of_node_put(node: parent); |
197 | if (IS_ERR(ptr: regmap)) |
198 | return PTR_ERR(ptr: regmap); |
199 | |
200 | wdev->regmap = regmap; |
201 | wdev->wdt_dev.info = &uniphier_wdt_info; |
202 | wdev->wdt_dev.ops = &uniphier_wdt_ops; |
203 | wdev->wdt_dev.max_timeout = WDT_PERIOD_MAX; |
204 | wdev->wdt_dev.min_timeout = WDT_PERIOD_MIN; |
205 | wdev->wdt_dev.timeout = WDT_DEFAULT_TIMEOUT; |
206 | wdev->wdt_dev.parent = dev; |
207 | |
208 | watchdog_init_timeout(wdd: &wdev->wdt_dev, timeout_parm: timeout, dev); |
209 | watchdog_set_nowayout(wdd: &wdev->wdt_dev, nowayout); |
210 | watchdog_stop_on_reboot(wdd: &wdev->wdt_dev); |
211 | |
212 | watchdog_set_drvdata(wdd: &wdev->wdt_dev, data: wdev); |
213 | |
214 | uniphier_watchdog_stop(w: &wdev->wdt_dev); |
215 | ret = regmap_write(map: wdev->regmap, WDTRSTSEL, WDTRSTSEL_RSTSEL_BOTH); |
216 | if (ret) |
217 | return ret; |
218 | |
219 | ret = devm_watchdog_register_device(dev, &wdev->wdt_dev); |
220 | if (ret) |
221 | return ret; |
222 | |
223 | dev_info(dev, "watchdog driver (timeout=%d sec, nowayout=%d)\n" , |
224 | wdev->wdt_dev.timeout, nowayout); |
225 | |
226 | return 0; |
227 | } |
228 | |
229 | static const struct of_device_id uniphier_wdt_dt_ids[] = { |
230 | { .compatible = "socionext,uniphier-wdt" }, |
231 | { /* sentinel */ } |
232 | }; |
233 | MODULE_DEVICE_TABLE(of, uniphier_wdt_dt_ids); |
234 | |
235 | static struct platform_driver uniphier_wdt_driver = { |
236 | .probe = uniphier_wdt_probe, |
237 | .driver = { |
238 | .name = "uniphier-wdt" , |
239 | .of_match_table = uniphier_wdt_dt_ids, |
240 | }, |
241 | }; |
242 | |
243 | module_platform_driver(uniphier_wdt_driver); |
244 | |
245 | module_param(timeout, uint, 0000); |
246 | MODULE_PARM_DESC(timeout, |
247 | "Watchdog timeout seconds in power of 2. (0 < timeout < 128, default=" |
248 | __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")" ); |
249 | |
250 | module_param(nowayout, bool, 0000); |
251 | MODULE_PARM_DESC(nowayout, |
252 | "Watchdog cannot be stopped once started (default=" |
253 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")" ); |
254 | |
255 | MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>" ); |
256 | MODULE_DESCRIPTION("UniPhier Watchdog Device Driver" ); |
257 | MODULE_LICENSE("GPL v2" ); |
258 | |