1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
4 */
5
6#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
7#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
8
9#define JH7100_CLK_CPUNDBUS_ROOT 0
10#define JH7100_CLK_DLA_ROOT 1
11#define JH7100_CLK_DSP_ROOT 2
12#define JH7100_CLK_GMACUSB_ROOT 3
13#define JH7100_CLK_PERH0_ROOT 4
14#define JH7100_CLK_PERH1_ROOT 5
15#define JH7100_CLK_VIN_ROOT 6
16#define JH7100_CLK_VOUT_ROOT 7
17#define JH7100_CLK_AUDIO_ROOT 8
18#define JH7100_CLK_CDECHIFI4_ROOT 9
19#define JH7100_CLK_CDEC_ROOT 10
20#define JH7100_CLK_VOUTBUS_ROOT 11
21#define JH7100_CLK_CPUNBUS_ROOT_DIV 12
22#define JH7100_CLK_DSP_ROOT_DIV 13
23#define JH7100_CLK_PERH0_SRC 14
24#define JH7100_CLK_PERH1_SRC 15
25#define JH7100_CLK_PLL0_TESTOUT 16
26#define JH7100_CLK_PLL1_TESTOUT 17
27#define JH7100_CLK_PLL2_TESTOUT 18
28#define JH7100_CLK_PLL2_REF 19
29#define JH7100_CLK_CPU_CORE 20
30#define JH7100_CLK_CPU_AXI 21
31#define JH7100_CLK_AHB_BUS 22
32#define JH7100_CLK_APB1_BUS 23
33#define JH7100_CLK_APB2_BUS 24
34#define JH7100_CLK_DOM3AHB_BUS 25
35#define JH7100_CLK_DOM7AHB_BUS 26
36#define JH7100_CLK_U74_CORE0 27
37#define JH7100_CLK_U74_CORE1 28
38#define JH7100_CLK_U74_AXI 29
39#define JH7100_CLK_U74RTC_TOGGLE 30
40#define JH7100_CLK_SGDMA2P_AXI 31
41#define JH7100_CLK_DMA2PNOC_AXI 32
42#define JH7100_CLK_SGDMA2P_AHB 33
43#define JH7100_CLK_DLA_BUS 34
44#define JH7100_CLK_DLA_AXI 35
45#define JH7100_CLK_DLANOC_AXI 36
46#define JH7100_CLK_DLA_APB 37
47#define JH7100_CLK_VP6_CORE 38
48#define JH7100_CLK_VP6BUS_SRC 39
49#define JH7100_CLK_VP6_AXI 40
50#define JH7100_CLK_VCDECBUS_SRC 41
51#define JH7100_CLK_VDEC_BUS 42
52#define JH7100_CLK_VDEC_AXI 43
53#define JH7100_CLK_VDECBRG_MAIN 44
54#define JH7100_CLK_VDEC_BCLK 45
55#define JH7100_CLK_VDEC_CCLK 46
56#define JH7100_CLK_VDEC_APB 47
57#define JH7100_CLK_JPEG_AXI 48
58#define JH7100_CLK_JPEG_CCLK 49
59#define JH7100_CLK_JPEG_APB 50
60#define JH7100_CLK_GC300_2X 51
61#define JH7100_CLK_GC300_AHB 52
62#define JH7100_CLK_JPCGC300_AXIBUS 53
63#define JH7100_CLK_GC300_AXI 54
64#define JH7100_CLK_JPCGC300_MAIN 55
65#define JH7100_CLK_VENC_BUS 56
66#define JH7100_CLK_VENC_AXI 57
67#define JH7100_CLK_VENCBRG_MAIN 58
68#define JH7100_CLK_VENC_BCLK 59
69#define JH7100_CLK_VENC_CCLK 60
70#define JH7100_CLK_VENC_APB 61
71#define JH7100_CLK_DDRPLL_DIV2 62
72#define JH7100_CLK_DDRPLL_DIV4 63
73#define JH7100_CLK_DDRPLL_DIV8 64
74#define JH7100_CLK_DDROSC_DIV2 65
75#define JH7100_CLK_DDRC0 66
76#define JH7100_CLK_DDRC1 67
77#define JH7100_CLK_DDRPHY_APB 68
78#define JH7100_CLK_NOC_ROB 69
79#define JH7100_CLK_NOC_COG 70
80#define JH7100_CLK_NNE_AHB 71
81#define JH7100_CLK_NNEBUS_SRC1 72
82#define JH7100_CLK_NNE_BUS 73
83#define JH7100_CLK_NNE_AXI 74
84#define JH7100_CLK_NNENOC_AXI 75
85#define JH7100_CLK_DLASLV_AXI 76
86#define JH7100_CLK_DSPX2C_AXI 77
87#define JH7100_CLK_HIFI4_SRC 78
88#define JH7100_CLK_HIFI4_COREFREE 79
89#define JH7100_CLK_HIFI4_CORE 80
90#define JH7100_CLK_HIFI4_BUS 81
91#define JH7100_CLK_HIFI4_AXI 82
92#define JH7100_CLK_HIFI4NOC_AXI 83
93#define JH7100_CLK_SGDMA1P_BUS 84
94#define JH7100_CLK_SGDMA1P_AXI 85
95#define JH7100_CLK_DMA1P_AXI 86
96#define JH7100_CLK_X2C_AXI 87
97#define JH7100_CLK_USB_BUS 88
98#define JH7100_CLK_USB_AXI 89
99#define JH7100_CLK_USBNOC_AXI 90
100#define JH7100_CLK_USBPHY_ROOTDIV 91
101#define JH7100_CLK_USBPHY_125M 92
102#define JH7100_CLK_USBPHY_PLLDIV25M 93
103#define JH7100_CLK_USBPHY_25M 94
104#define JH7100_CLK_AUDIO_DIV 95
105#define JH7100_CLK_AUDIO_SRC 96
106#define JH7100_CLK_AUDIO_12288 97
107#define JH7100_CLK_VIN_SRC 98
108#define JH7100_CLK_ISP0_BUS 99
109#define JH7100_CLK_ISP0_AXI 100
110#define JH7100_CLK_ISP0NOC_AXI 101
111#define JH7100_CLK_ISPSLV_AXI 102
112#define JH7100_CLK_ISP1_BUS 103
113#define JH7100_CLK_ISP1_AXI 104
114#define JH7100_CLK_ISP1NOC_AXI 105
115#define JH7100_CLK_VIN_BUS 106
116#define JH7100_CLK_VIN_AXI 107
117#define JH7100_CLK_VINNOC_AXI 108
118#define JH7100_CLK_VOUT_SRC 109
119#define JH7100_CLK_DISPBUS_SRC 110
120#define JH7100_CLK_DISP_BUS 111
121#define JH7100_CLK_DISP_AXI 112
122#define JH7100_CLK_DISPNOC_AXI 113
123#define JH7100_CLK_SDIO0_AHB 114
124#define JH7100_CLK_SDIO0_CCLKINT 115
125#define JH7100_CLK_SDIO0_CCLKINT_INV 116
126#define JH7100_CLK_SDIO1_AHB 117
127#define JH7100_CLK_SDIO1_CCLKINT 118
128#define JH7100_CLK_SDIO1_CCLKINT_INV 119
129#define JH7100_CLK_GMAC_AHB 120
130#define JH7100_CLK_GMAC_ROOT_DIV 121
131#define JH7100_CLK_GMAC_PTP_REF 122
132#define JH7100_CLK_GMAC_GTX 123
133#define JH7100_CLK_GMAC_RMII_TX 124
134#define JH7100_CLK_GMAC_RMII_RX 125
135#define JH7100_CLK_GMAC_TX 126
136#define JH7100_CLK_GMAC_TX_INV 127
137#define JH7100_CLK_GMAC_RX_PRE 128
138#define JH7100_CLK_GMAC_RX_INV 129
139#define JH7100_CLK_GMAC_RMII 130
140#define JH7100_CLK_GMAC_TOPHYREF 131
141#define JH7100_CLK_SPI2AHB_AHB 132
142#define JH7100_CLK_SPI2AHB_CORE 133
143#define JH7100_CLK_EZMASTER_AHB 134
144#define JH7100_CLK_E24_AHB 135
145#define JH7100_CLK_E24RTC_TOGGLE 136
146#define JH7100_CLK_QSPI_AHB 137
147#define JH7100_CLK_QSPI_APB 138
148#define JH7100_CLK_QSPI_REF 139
149#define JH7100_CLK_SEC_AHB 140
150#define JH7100_CLK_AES 141
151#define JH7100_CLK_SHA 142
152#define JH7100_CLK_PKA 143
153#define JH7100_CLK_TRNG_APB 144
154#define JH7100_CLK_OTP_APB 145
155#define JH7100_CLK_UART0_APB 146
156#define JH7100_CLK_UART0_CORE 147
157#define JH7100_CLK_UART1_APB 148
158#define JH7100_CLK_UART1_CORE 149
159#define JH7100_CLK_SPI0_APB 150
160#define JH7100_CLK_SPI0_CORE 151
161#define JH7100_CLK_SPI1_APB 152
162#define JH7100_CLK_SPI1_CORE 153
163#define JH7100_CLK_I2C0_APB 154
164#define JH7100_CLK_I2C0_CORE 155
165#define JH7100_CLK_I2C1_APB 156
166#define JH7100_CLK_I2C1_CORE 157
167#define JH7100_CLK_GPIO_APB 158
168#define JH7100_CLK_UART2_APB 159
169#define JH7100_CLK_UART2_CORE 160
170#define JH7100_CLK_UART3_APB 161
171#define JH7100_CLK_UART3_CORE 162
172#define JH7100_CLK_SPI2_APB 163
173#define JH7100_CLK_SPI2_CORE 164
174#define JH7100_CLK_SPI3_APB 165
175#define JH7100_CLK_SPI3_CORE 166
176#define JH7100_CLK_I2C2_APB 167
177#define JH7100_CLK_I2C2_CORE 168
178#define JH7100_CLK_I2C3_APB 169
179#define JH7100_CLK_I2C3_CORE 170
180#define JH7100_CLK_WDTIMER_APB 171
181#define JH7100_CLK_WDT_CORE 172
182#define JH7100_CLK_TIMER0_CORE 173
183#define JH7100_CLK_TIMER1_CORE 174
184#define JH7100_CLK_TIMER2_CORE 175
185#define JH7100_CLK_TIMER3_CORE 176
186#define JH7100_CLK_TIMER4_CORE 177
187#define JH7100_CLK_TIMER5_CORE 178
188#define JH7100_CLK_TIMER6_CORE 179
189#define JH7100_CLK_VP6INTC_APB 180
190#define JH7100_CLK_PWM_APB 181
191#define JH7100_CLK_MSI_APB 182
192#define JH7100_CLK_TEMP_APB 183
193#define JH7100_CLK_TEMP_SENSE 184
194#define JH7100_CLK_SYSERR_APB 185
195
196#define JH7100_CLK_PLL0_OUT 186
197#define JH7100_CLK_PLL1_OUT 187
198#define JH7100_CLK_PLL2_OUT 188
199
200#define JH7100_CLK_END 189
201
202#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */
203

source code of linux/include/dt-bindings/clock/starfive-jh7100.h