1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * StarFive JH7100 Clock Generator Driver |
4 | * |
5 | * Copyright 2021 Ahmad Fatoum, Pengutronix |
6 | * Copyright (C) 2021 Glider bv |
7 | * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> |
8 | */ |
9 | |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/device.h> |
12 | #include <linux/init.h> |
13 | #include <linux/mod_devicetable.h> |
14 | #include <linux/platform_device.h> |
15 | |
16 | #include <dt-bindings/clock/starfive-jh7100.h> |
17 | |
18 | #include "clk-starfive-jh71x0.h" |
19 | |
20 | /* external clocks */ |
21 | #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0) |
22 | #define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1) |
23 | #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2) |
24 | #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) |
25 | |
26 | static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { |
27 | JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root" , 0, 4, |
28 | JH7100_CLK_OSC_SYS, |
29 | JH7100_CLK_PLL0_OUT, |
30 | JH7100_CLK_PLL1_OUT, |
31 | JH7100_CLK_PLL2_OUT), |
32 | JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root" , 0, 3, |
33 | JH7100_CLK_OSC_SYS, |
34 | JH7100_CLK_PLL1_OUT, |
35 | JH7100_CLK_PLL2_OUT), |
36 | JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root" , 0, 4, |
37 | JH7100_CLK_OSC_SYS, |
38 | JH7100_CLK_PLL0_OUT, |
39 | JH7100_CLK_PLL1_OUT, |
40 | JH7100_CLK_PLL2_OUT), |
41 | JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root" , 0, 3, |
42 | JH7100_CLK_OSC_SYS, |
43 | JH7100_CLK_PLL0_OUT, |
44 | JH7100_CLK_PLL2_OUT), |
45 | JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root" , 0, 2, |
46 | JH7100_CLK_OSC_SYS, |
47 | JH7100_CLK_PLL0_OUT), |
48 | JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root" , 0, 2, |
49 | JH7100_CLK_OSC_SYS, |
50 | JH7100_CLK_PLL2_OUT), |
51 | JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root" , 0, 3, |
52 | JH7100_CLK_OSC_SYS, |
53 | JH7100_CLK_PLL1_OUT, |
54 | JH7100_CLK_PLL2_OUT), |
55 | JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root" , 0, 3, |
56 | JH7100_CLK_OSC_AUD, |
57 | JH7100_CLK_PLL0_OUT, |
58 | JH7100_CLK_PLL2_OUT), |
59 | JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root" , 0, 8, JH7100_CLK_PLL0_OUT), |
60 | JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root" , 0, 3, |
61 | JH7100_CLK_OSC_SYS, |
62 | JH7100_CLK_PLL1_OUT, |
63 | JH7100_CLK_PLL2_OUT), |
64 | JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root" , 0, 3, |
65 | JH7100_CLK_OSC_SYS, |
66 | JH7100_CLK_PLL0_OUT, |
67 | JH7100_CLK_PLL1_OUT), |
68 | JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root" , 0, 3, |
69 | JH7100_CLK_OSC_AUD, |
70 | JH7100_CLK_PLL0_OUT, |
71 | JH7100_CLK_PLL2_OUT), |
72 | JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div" , 2, JH7100_CLK_CPUNDBUS_ROOT), |
73 | JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div" , 4, JH7100_CLK_DSP_ROOT), |
74 | JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src" , 4, JH7100_CLK_PERH0_ROOT), |
75 | JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src" , 4, JH7100_CLK_PERH1_ROOT), |
76 | JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout" , 0, 31, JH7100_CLK_PERH0_SRC), |
77 | JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout" , 0, 31, JH7100_CLK_DLA_ROOT), |
78 | JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout" , 0, 31, JH7100_CLK_PERH1_SRC), |
79 | JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk" , 0, 2, |
80 | JH7100_CLK_OSC_SYS, |
81 | JH7100_CLK_OSC_AUD), |
82 | JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core" , 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
83 | JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi" , 8, JH7100_CLK_CPU_CORE), |
84 | JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus" , 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
85 | JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus" , 8, JH7100_CLK_AHB_BUS), |
86 | JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus" , 8, JH7100_CLK_AHB_BUS), |
87 | JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus" , CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), |
88 | JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus" , CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), |
89 | JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0" , CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE), |
90 | JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1" , CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE), |
91 | JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi" , CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI), |
92 | JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle" , CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS), |
93 | JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi" , 0, JH7100_CLK_CPU_AXI), |
94 | JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi" , 0, JH7100_CLK_CPU_AXI), |
95 | JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb" , 0, JH7100_CLK_AHB_BUS), |
96 | JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus" , 4, JH7100_CLK_DLA_ROOT), |
97 | JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi" , 0, JH7100_CLK_DLA_BUS), |
98 | JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi" , 0, JH7100_CLK_DLA_BUS), |
99 | JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb" , 0, JH7100_CLK_APB1_BUS), |
100 | JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core" , 0, 4, JH7100_CLK_DSP_ROOT_DIV), |
101 | JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src" , 4, JH7100_CLK_DSP_ROOT), |
102 | JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi" , 0, 4, JH7100_CLK_VP6BUS_SRC), |
103 | JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src" , 4, JH7100_CLK_CDECHIFI4_ROOT), |
104 | JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus" , 8, JH7100_CLK_VCDECBUS_SRC), |
105 | JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi" , 0, JH7100_CLK_VDEC_BUS), |
106 | JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk" , 0, JH7100_CLK_VDEC_BUS), |
107 | JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk" , 0, 8, JH7100_CLK_VCDECBUS_SRC), |
108 | JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk" , 0, 8, JH7100_CLK_CDEC_ROOT), |
109 | JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb" , 0, JH7100_CLK_APB1_BUS), |
110 | JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi" , 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
111 | JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk" , 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
112 | JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb" , 0, JH7100_CLK_APB1_BUS), |
113 | JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x" , 0, 8, JH7100_CLK_CDECHIFI4_ROOT), |
114 | JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb" , 0, JH7100_CLK_AHB_BUS), |
115 | JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus" , 8, JH7100_CLK_VCDECBUS_SRC), |
116 | JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi" , 0, JH7100_CLK_JPCGC300_AXIBUS), |
117 | JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk" , 0, JH7100_CLK_JPCGC300_AXIBUS), |
118 | JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus" , 8, JH7100_CLK_VCDECBUS_SRC), |
119 | JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi" , 0, JH7100_CLK_VENC_BUS), |
120 | JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk" , 0, JH7100_CLK_VENC_BUS), |
121 | JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk" , 0, 8, JH7100_CLK_VCDECBUS_SRC), |
122 | JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk" , 0, 8, JH7100_CLK_CDEC_ROOT), |
123 | JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb" , 0, JH7100_CLK_APB1_BUS), |
124 | JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2" , CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT), |
125 | JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4" , CLK_IS_CRITICAL, 2, |
126 | JH7100_CLK_DDRPLL_DIV2), |
127 | JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8" , CLK_IS_CRITICAL, 2, |
128 | JH7100_CLK_DDRPLL_DIV4), |
129 | JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2" , CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS), |
130 | JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0" , CLK_IS_CRITICAL, 4, |
131 | JH7100_CLK_DDROSC_DIV2, |
132 | JH7100_CLK_DDRPLL_DIV2, |
133 | JH7100_CLK_DDRPLL_DIV4, |
134 | JH7100_CLK_DDRPLL_DIV8), |
135 | JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1" , CLK_IS_CRITICAL, 4, |
136 | JH7100_CLK_DDROSC_DIV2, |
137 | JH7100_CLK_DDRPLL_DIV2, |
138 | JH7100_CLK_DDRPLL_DIV4, |
139 | JH7100_CLK_DDRPLL_DIV8), |
140 | JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb" , 0, JH7100_CLK_APB1_BUS), |
141 | JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob" , 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
142 | JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog" , 8, JH7100_CLK_DLA_ROOT), |
143 | JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb" , 0, JH7100_CLK_AHB_BUS), |
144 | JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1" , 4, JH7100_CLK_DSP_ROOT), |
145 | JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus" , 0, 2, |
146 | JH7100_CLK_CPU_AXI, |
147 | JH7100_CLK_NNEBUS_SRC1), |
148 | JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi" , 0, JH7100_CLK_NNE_BUS), |
149 | JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi" , 0, JH7100_CLK_NNE_BUS), |
150 | JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi" , 0, JH7100_CLK_NNE_BUS), |
151 | JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi" , CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS), |
152 | JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src" , 4, JH7100_CLK_CDECHIFI4_ROOT), |
153 | JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree" , 8, JH7100_CLK_HIFI4_SRC), |
154 | JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core" , 0, JH7100_CLK_HIFI4_COREFREE), |
155 | JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus" , 8, JH7100_CLK_HIFI4_COREFREE), |
156 | JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi" , 0, JH7100_CLK_HIFI4_BUS), |
157 | JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi" , 0, JH7100_CLK_HIFI4_BUS), |
158 | JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus" , 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
159 | JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi" , 0, JH7100_CLK_SGDMA1P_BUS), |
160 | JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi" , 0, JH7100_CLK_SGDMA1P_BUS), |
161 | JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi" , CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
162 | JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus" , 8, JH7100_CLK_CPUNBUS_ROOT_DIV), |
163 | JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi" , 0, JH7100_CLK_USB_BUS), |
164 | JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi" , 0, JH7100_CLK_USB_BUS), |
165 | JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv" , 4, JH7100_CLK_GMACUSB_ROOT), |
166 | JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m" , 0, 8, JH7100_CLK_USBPHY_ROOTDIV), |
167 | JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m" , 0, 32, |
168 | JH7100_CLK_USBPHY_ROOTDIV), |
169 | JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m" , 0, 2, |
170 | JH7100_CLK_OSC_SYS, |
171 | JH7100_CLK_USBPHY_PLLDIV25M), |
172 | JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div" , JH7100_CLK_AUDIO_ROOT), |
173 | JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src" , 0, JH7100_CLK_AUDIO_DIV), |
174 | JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288" , 0, JH7100_CLK_OSC_AUD), |
175 | JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src" , 0, 4, JH7100_CLK_VIN_ROOT), |
176 | JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus" , 8, JH7100_CLK_VIN_SRC), |
177 | JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi" , 0, JH7100_CLK_ISP0_BUS), |
178 | JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi" , 0, JH7100_CLK_ISP0_BUS), |
179 | JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi" , 0, JH7100_CLK_ISP0_BUS), |
180 | JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus" , 8, JH7100_CLK_VIN_SRC), |
181 | JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi" , 0, JH7100_CLK_ISP1_BUS), |
182 | JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi" , 0, JH7100_CLK_ISP1_BUS), |
183 | JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus" , 8, JH7100_CLK_VIN_SRC), |
184 | JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi" , 0, JH7100_CLK_VIN_BUS), |
185 | JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi" , 0, JH7100_CLK_VIN_BUS), |
186 | JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src" , 0, 4, JH7100_CLK_VOUT_ROOT), |
187 | JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src" , 4, JH7100_CLK_VOUTBUS_ROOT), |
188 | JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus" , 4, JH7100_CLK_DISPBUS_SRC), |
189 | JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi" , 0, JH7100_CLK_DISP_BUS), |
190 | JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi" , 0, JH7100_CLK_DISP_BUS), |
191 | JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb" , 0, JH7100_CLK_AHB_BUS), |
192 | JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint" , 0, 24, JH7100_CLK_PERH0_SRC), |
193 | JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv" , JH7100_CLK_SDIO0_CCLKINT), |
194 | JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb" , 0, JH7100_CLK_AHB_BUS), |
195 | JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint" , 0, 24, JH7100_CLK_PERH1_SRC), |
196 | JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv" , JH7100_CLK_SDIO1_CCLKINT), |
197 | JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb" , 0, JH7100_CLK_AHB_BUS), |
198 | JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div" , 8, JH7100_CLK_GMACUSB_ROOT), |
199 | JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk" , 0, 31, JH7100_CLK_GMAC_ROOT_DIV), |
200 | JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk" , 0, 255, JH7100_CLK_GMAC_ROOT_DIV), |
201 | JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk" , 0, 8, JH7100_CLK_GMAC_RMII_REF), |
202 | JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk" , 0, 8, JH7100_CLK_GMAC_RMII_REF), |
203 | JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx" , CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 3, |
204 | JH7100_CLK_GMAC_GTX, |
205 | JH7100_CLK_GMAC_TX_INV, |
206 | JH7100_CLK_GMAC_RMII_TX), |
207 | JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv" , JH7100_CLK_GMAC_TX), |
208 | JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre" , 0, 2, |
209 | JH7100_CLK_GMAC_GR_MII_RX, |
210 | JH7100_CLK_GMAC_RMII_RX), |
211 | JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv" , JH7100_CLK_GMAC_RX_PRE), |
212 | JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii" , 0, JH7100_CLK_GMAC_RMII_REF), |
213 | JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref" , 0, 127, JH7100_CLK_GMAC_ROOT_DIV), |
214 | JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb" , 0, JH7100_CLK_AHB_BUS), |
215 | JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core" , 0, 31, JH7100_CLK_PERH0_SRC), |
216 | JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb" , 0, JH7100_CLK_AHB_BUS), |
217 | JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb" , 0, JH7100_CLK_AHB_BUS), |
218 | JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle" , 0, JH7100_CLK_OSC_SYS), |
219 | JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb" , 0, JH7100_CLK_AHB_BUS), |
220 | JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb" , 0, JH7100_CLK_APB1_BUS), |
221 | JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk" , 0, 31, JH7100_CLK_PERH0_SRC), |
222 | JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb" , 0, JH7100_CLK_AHB_BUS), |
223 | JH71X0_GATE(JH7100_CLK_AES, "aes_clk" , 0, JH7100_CLK_SEC_AHB), |
224 | JH71X0_GATE(JH7100_CLK_SHA, "sha_clk" , 0, JH7100_CLK_SEC_AHB), |
225 | JH71X0_GATE(JH7100_CLK_PKA, "pka_clk" , 0, JH7100_CLK_SEC_AHB), |
226 | JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb" , 0, JH7100_CLK_APB1_BUS), |
227 | JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb" , 0, JH7100_CLK_APB1_BUS), |
228 | JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb" , 0, JH7100_CLK_APB1_BUS), |
229 | JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core" , 0, 63, JH7100_CLK_PERH1_SRC), |
230 | JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb" , 0, JH7100_CLK_APB1_BUS), |
231 | JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core" , 0, 63, JH7100_CLK_PERH1_SRC), |
232 | JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb" , 0, JH7100_CLK_APB1_BUS), |
233 | JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core" , 0, 63, JH7100_CLK_PERH1_SRC), |
234 | JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb" , 0, JH7100_CLK_APB1_BUS), |
235 | JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core" , 0, 63, JH7100_CLK_PERH1_SRC), |
236 | JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb" , 0, JH7100_CLK_APB1_BUS), |
237 | JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core" , 0, 63, JH7100_CLK_PERH1_SRC), |
238 | JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb" , 0, JH7100_CLK_APB1_BUS), |
239 | JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core" , 0, 63, JH7100_CLK_PERH1_SRC), |
240 | JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb" , 0, JH7100_CLK_APB1_BUS), |
241 | JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb" , 0, JH7100_CLK_APB2_BUS), |
242 | JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core" , 0, 63, JH7100_CLK_PERH0_SRC), |
243 | JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb" , 0, JH7100_CLK_APB2_BUS), |
244 | JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core" , 0, 63, JH7100_CLK_PERH0_SRC), |
245 | JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb" , 0, JH7100_CLK_APB2_BUS), |
246 | JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core" , 0, 63, JH7100_CLK_PERH0_SRC), |
247 | JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb" , 0, JH7100_CLK_APB2_BUS), |
248 | JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core" , 0, 63, JH7100_CLK_PERH0_SRC), |
249 | JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb" , 0, JH7100_CLK_APB2_BUS), |
250 | JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core" , 0, 63, JH7100_CLK_PERH0_SRC), |
251 | JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb" , 0, JH7100_CLK_APB2_BUS), |
252 | JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core" , 0, 63, JH7100_CLK_PERH0_SRC), |
253 | JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb" , 0, JH7100_CLK_APB2_BUS), |
254 | JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
255 | JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
256 | JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
257 | JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
258 | JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
259 | JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
260 | JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
261 | JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk" , 0, 63, JH7100_CLK_PERH0_SRC), |
262 | JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb" , 0, JH7100_CLK_APB2_BUS), |
263 | JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb" , 0, JH7100_CLK_APB2_BUS), |
264 | JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb" , 0, JH7100_CLK_APB2_BUS), |
265 | JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb" , 0, JH7100_CLK_APB2_BUS), |
266 | JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense" , 0, 31, JH7100_CLK_OSC_SYS), |
267 | JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb" , 0, JH7100_CLK_APB2_BUS), |
268 | }; |
269 | |
270 | static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) |
271 | { |
272 | struct jh71x0_clk_priv *priv = data; |
273 | unsigned int idx = clkspec->args[0]; |
274 | |
275 | if (idx < JH7100_CLK_PLL0_OUT) |
276 | return &priv->reg[idx].hw; |
277 | |
278 | if (idx < JH7100_CLK_END) |
279 | return priv->pll[idx - JH7100_CLK_PLL0_OUT]; |
280 | |
281 | return ERR_PTR(error: -EINVAL); |
282 | } |
283 | |
284 | static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) |
285 | { |
286 | struct jh71x0_clk_priv *priv; |
287 | unsigned int idx; |
288 | int ret; |
289 | |
290 | priv = devm_kzalloc(dev: &pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL); |
291 | if (!priv) |
292 | return -ENOMEM; |
293 | |
294 | spin_lock_init(&priv->rmw_lock); |
295 | priv->dev = &pdev->dev; |
296 | priv->base = devm_platform_ioremap_resource(pdev, index: 0); |
297 | if (IS_ERR(ptr: priv->base)) |
298 | return PTR_ERR(ptr: priv->base); |
299 | |
300 | priv->pll[0] = devm_clk_hw_register_fixed_factor(dev: priv->dev, name: "pll0_out" , |
301 | parent_name: "osc_sys" , flags: 0, mult: 40, div: 1); |
302 | if (IS_ERR(ptr: priv->pll[0])) |
303 | return PTR_ERR(ptr: priv->pll[0]); |
304 | |
305 | priv->pll[1] = devm_clk_hw_register_fixed_factor(dev: priv->dev, name: "pll1_out" , |
306 | parent_name: "osc_sys" , flags: 0, mult: 64, div: 1); |
307 | if (IS_ERR(ptr: priv->pll[1])) |
308 | return PTR_ERR(ptr: priv->pll[1]); |
309 | |
310 | priv->pll[2] = devm_clk_hw_register_fixed_factor(dev: priv->dev, name: "pll2_out" , |
311 | parent_name: "pll2_refclk" , flags: 0, mult: 55, div: 1); |
312 | if (IS_ERR(ptr: priv->pll[2])) |
313 | return PTR_ERR(ptr: priv->pll[2]); |
314 | |
315 | for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) { |
316 | u32 max = jh7100_clk_data[idx].max; |
317 | struct clk_parent_data parents[4] = {}; |
318 | struct clk_init_data init = { |
319 | .name = jh7100_clk_data[idx].name, |
320 | .ops = starfive_jh71x0_clk_ops(max), |
321 | .parent_data = parents, |
322 | .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, |
323 | .flags = jh7100_clk_data[idx].flags, |
324 | }; |
325 | struct jh71x0_clk *clk = &priv->reg[idx]; |
326 | unsigned int i; |
327 | |
328 | for (i = 0; i < init.num_parents; i++) { |
329 | unsigned int pidx = jh7100_clk_data[idx].parents[i]; |
330 | |
331 | if (pidx < JH7100_CLK_PLL0_OUT) |
332 | parents[i].hw = &priv->reg[pidx].hw; |
333 | else if (pidx < JH7100_CLK_END) |
334 | parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT]; |
335 | else if (pidx == JH7100_CLK_OSC_SYS) |
336 | parents[i].fw_name = "osc_sys" ; |
337 | else if (pidx == JH7100_CLK_OSC_AUD) |
338 | parents[i].fw_name = "osc_aud" ; |
339 | else if (pidx == JH7100_CLK_GMAC_RMII_REF) |
340 | parents[i].fw_name = "gmac_rmii_ref" ; |
341 | else if (pidx == JH7100_CLK_GMAC_GR_MII_RX) |
342 | parents[i].fw_name = "gmac_gr_mii_rxclk" ; |
343 | } |
344 | |
345 | clk->hw.init = &init; |
346 | clk->idx = idx; |
347 | clk->max_div = max & JH71X0_CLK_DIV_MASK; |
348 | |
349 | ret = devm_clk_hw_register(dev: priv->dev, hw: &clk->hw); |
350 | if (ret) |
351 | return ret; |
352 | } |
353 | |
354 | return devm_of_clk_add_hw_provider(dev: priv->dev, get: jh7100_clk_get, data: priv); |
355 | } |
356 | |
357 | static const struct of_device_id clk_starfive_jh7100_match[] = { |
358 | { .compatible = "starfive,jh7100-clkgen" }, |
359 | { /* sentinel */ } |
360 | }; |
361 | |
362 | static struct platform_driver clk_starfive_jh7100_driver = { |
363 | .driver = { |
364 | .name = "clk-starfive-jh7100" , |
365 | .of_match_table = clk_starfive_jh7100_match, |
366 | .suppress_bind_attrs = true, |
367 | }, |
368 | }; |
369 | builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe); |
370 | |