| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2014 MediaTek Inc. |
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| 4 | * Author: Flora Fu, MediaTek |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __MFD_MT6397_REGISTERS_H__ |
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| 8 | #define __MFD_MT6397_REGISTERS_H__ |
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| 9 | |
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| 10 | /* PMIC Registers */ |
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| 11 | #define MT6397_CID 0x0100 |
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| 12 | #define MT6397_TOP_CKPDN 0x0102 |
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| 13 | #define MT6397_TOP_CKPDN_SET 0x0104 |
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| 14 | #define MT6397_TOP_CKPDN_CLR 0x0106 |
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| 15 | #define MT6397_TOP_CKPDN2 0x0108 |
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| 16 | #define MT6397_TOP_CKPDN2_SET 0x010A |
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| 17 | #define MT6397_TOP_CKPDN2_CLR 0x010C |
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| 18 | #define MT6397_TOP_GPIO_CKPDN 0x010E |
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| 19 | #define MT6397_TOP_RST_CON 0x0114 |
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| 20 | #define MT6397_WRP_CKPDN 0x011A |
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| 21 | #define MT6397_WRP_RST_CON 0x0120 |
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| 22 | #define MT6397_TOP_RST_MISC 0x0126 |
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| 23 | #define MT6397_TOP_CKCON1 0x0128 |
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| 24 | #define MT6397_TOP_CKCON2 0x012A |
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| 25 | #define MT6397_TOP_CKTST1 0x012C |
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| 26 | #define MT6397_TOP_CKTST2 0x012E |
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| 27 | #define MT6397_OC_DEG_EN 0x0130 |
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| 28 | #define MT6397_OC_CTL0 0x0132 |
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| 29 | #define MT6397_OC_CTL1 0x0134 |
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| 30 | #define MT6397_OC_CTL2 0x0136 |
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| 31 | #define MT6397_INT_RSV 0x0138 |
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| 32 | #define MT6397_TEST_CON0 0x013A |
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| 33 | #define MT6397_TEST_CON1 0x013C |
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| 34 | #define MT6397_STATUS0 0x013E |
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| 35 | #define MT6397_STATUS1 0x0140 |
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| 36 | #define MT6397_PGSTATUS 0x0142 |
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| 37 | #define MT6397_CHRSTATUS 0x0144 |
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| 38 | #define MT6397_OCSTATUS0 0x0146 |
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| 39 | #define MT6397_OCSTATUS1 0x0148 |
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| 40 | #define MT6397_OCSTATUS2 0x014A |
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| 41 | #define MT6397_HDMI_PAD_IE 0x014C |
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| 42 | #define MT6397_TEST_OUT_L 0x014E |
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| 43 | #define MT6397_TEST_OUT_H 0x0150 |
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| 44 | #define MT6397_TDSEL_CON 0x0152 |
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| 45 | #define MT6397_RDSEL_CON 0x0154 |
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| 46 | #define MT6397_GPIO_SMT_CON0 0x0156 |
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| 47 | #define MT6397_GPIO_SMT_CON1 0x0158 |
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| 48 | #define MT6397_GPIO_SMT_CON2 0x015A |
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| 49 | #define MT6397_GPIO_SMT_CON3 0x015C |
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| 50 | #define MT6397_DRV_CON0 0x015E |
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| 51 | #define MT6397_DRV_CON1 0x0160 |
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| 52 | #define MT6397_DRV_CON2 0x0162 |
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| 53 | #define MT6397_DRV_CON3 0x0164 |
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| 54 | #define MT6397_DRV_CON4 0x0166 |
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| 55 | #define MT6397_DRV_CON5 0x0168 |
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| 56 | #define MT6397_DRV_CON6 0x016A |
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| 57 | #define MT6397_DRV_CON7 0x016C |
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| 58 | #define MT6397_DRV_CON8 0x016E |
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| 59 | #define MT6397_DRV_CON9 0x0170 |
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| 60 | #define MT6397_DRV_CON10 0x0172 |
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| 61 | #define MT6397_DRV_CON11 0x0174 |
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| 62 | #define MT6397_DRV_CON12 0x0176 |
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| 63 | #define MT6397_INT_CON0 0x0178 |
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| 64 | #define MT6397_INT_CON1 0x017E |
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| 65 | #define MT6397_INT_STATUS0 0x0184 |
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| 66 | #define MT6397_INT_STATUS1 0x0186 |
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| 67 | #define MT6397_FQMTR_CON0 0x0188 |
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| 68 | #define MT6397_FQMTR_CON1 0x018A |
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| 69 | #define MT6397_FQMTR_CON2 0x018C |
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| 70 | #define MT6397_EFUSE_DOUT_0_15 0x01C4 |
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| 71 | #define MT6397_EFUSE_DOUT_16_31 0x01C6 |
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| 72 | #define MT6397_EFUSE_DOUT_32_47 0x01C8 |
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| 73 | #define MT6397_EFUSE_DOUT_48_63 0x01CA |
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| 74 | #define MT6397_SPI_CON 0x01CC |
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| 75 | #define MT6397_TOP_CKPDN3 0x01CE |
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| 76 | #define MT6397_TOP_CKCON3 0x01D4 |
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| 77 | #define MT6397_EFUSE_DOUT_64_79 0x01D6 |
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| 78 | #define MT6397_EFUSE_DOUT_80_95 0x01D8 |
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| 79 | #define MT6397_EFUSE_DOUT_96_111 0x01DA |
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| 80 | #define MT6397_EFUSE_DOUT_112_127 0x01DC |
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| 81 | #define MT6397_EFUSE_DOUT_128_143 0x01DE |
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| 82 | #define MT6397_EFUSE_DOUT_144_159 0x01E0 |
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| 83 | #define MT6397_EFUSE_DOUT_160_175 0x01E2 |
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| 84 | #define MT6397_EFUSE_DOUT_176_191 0x01E4 |
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| 85 | #define MT6397_EFUSE_DOUT_192_207 0x01E6 |
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| 86 | #define MT6397_EFUSE_DOUT_208_223 0x01E8 |
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| 87 | #define MT6397_EFUSE_DOUT_224_239 0x01EA |
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| 88 | #define MT6397_EFUSE_DOUT_240_255 0x01EC |
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| 89 | #define MT6397_EFUSE_DOUT_256_271 0x01EE |
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| 90 | #define MT6397_EFUSE_DOUT_272_287 0x01F0 |
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| 91 | #define MT6397_EFUSE_DOUT_288_300 0x01F2 |
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| 92 | #define MT6397_EFUSE_DOUT_304_319 0x01F4 |
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| 93 | #define MT6397_BUCK_CON0 0x0200 |
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| 94 | #define MT6397_BUCK_CON1 0x0202 |
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| 95 | #define MT6397_BUCK_CON2 0x0204 |
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| 96 | #define MT6397_BUCK_CON3 0x0206 |
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| 97 | #define MT6397_BUCK_CON4 0x0208 |
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| 98 | #define MT6397_BUCK_CON5 0x020A |
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| 99 | #define MT6397_BUCK_CON6 0x020C |
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| 100 | #define MT6397_BUCK_CON7 0x020E |
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| 101 | #define MT6397_BUCK_CON8 0x0210 |
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| 102 | #define MT6397_BUCK_CON9 0x0212 |
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| 103 | #define MT6397_VCA15_CON0 0x0214 |
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| 104 | #define MT6397_VCA15_CON1 0x0216 |
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| 105 | #define MT6397_VCA15_CON2 0x0218 |
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| 106 | #define MT6397_VCA15_CON3 0x021A |
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| 107 | #define MT6397_VCA15_CON4 0x021C |
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| 108 | #define MT6397_VCA15_CON5 0x021E |
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| 109 | #define MT6397_VCA15_CON6 0x0220 |
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| 110 | #define MT6397_VCA15_CON7 0x0222 |
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| 111 | #define MT6397_VCA15_CON8 0x0224 |
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| 112 | #define MT6397_VCA15_CON9 0x0226 |
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| 113 | #define MT6397_VCA15_CON10 0x0228 |
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| 114 | #define MT6397_VCA15_CON11 0x022A |
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| 115 | #define MT6397_VCA15_CON12 0x022C |
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| 116 | #define MT6397_VCA15_CON13 0x022E |
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| 117 | #define MT6397_VCA15_CON14 0x0230 |
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| 118 | #define MT6397_VCA15_CON15 0x0232 |
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| 119 | #define MT6397_VCA15_CON16 0x0234 |
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| 120 | #define MT6397_VCA15_CON17 0x0236 |
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| 121 | #define MT6397_VCA15_CON18 0x0238 |
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| 122 | #define MT6397_VSRMCA15_CON0 0x023A |
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| 123 | #define MT6397_VSRMCA15_CON1 0x023C |
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| 124 | #define MT6397_VSRMCA15_CON2 0x023E |
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| 125 | #define MT6397_VSRMCA15_CON3 0x0240 |
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| 126 | #define MT6397_VSRMCA15_CON4 0x0242 |
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| 127 | #define MT6397_VSRMCA15_CON5 0x0244 |
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| 128 | #define MT6397_VSRMCA15_CON6 0x0246 |
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| 129 | #define MT6397_VSRMCA15_CON7 0x0248 |
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| 130 | #define MT6397_VSRMCA15_CON8 0x024A |
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| 131 | #define MT6397_VSRMCA15_CON9 0x024C |
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| 132 | #define MT6397_VSRMCA15_CON10 0x024E |
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| 133 | #define MT6397_VSRMCA15_CON11 0x0250 |
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| 134 | #define MT6397_VSRMCA15_CON12 0x0252 |
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| 135 | #define MT6397_VSRMCA15_CON13 0x0254 |
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| 136 | #define MT6397_VSRMCA15_CON14 0x0256 |
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| 137 | #define MT6397_VSRMCA15_CON15 0x0258 |
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| 138 | #define MT6397_VSRMCA15_CON16 0x025A |
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| 139 | #define MT6397_VSRMCA15_CON17 0x025C |
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| 140 | #define MT6397_VSRMCA15_CON18 0x025E |
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| 141 | #define MT6397_VSRMCA15_CON19 0x0260 |
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| 142 | #define MT6397_VSRMCA15_CON20 0x0262 |
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| 143 | #define MT6397_VSRMCA15_CON21 0x0264 |
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| 144 | #define MT6397_VCORE_CON0 0x0266 |
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| 145 | #define MT6397_VCORE_CON1 0x0268 |
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| 146 | #define MT6397_VCORE_CON2 0x026A |
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| 147 | #define MT6397_VCORE_CON3 0x026C |
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| 148 | #define MT6397_VCORE_CON4 0x026E |
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| 149 | #define MT6397_VCORE_CON5 0x0270 |
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| 150 | #define MT6397_VCORE_CON6 0x0272 |
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| 151 | #define MT6397_VCORE_CON7 0x0274 |
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| 152 | #define MT6397_VCORE_CON8 0x0276 |
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| 153 | #define MT6397_VCORE_CON9 0x0278 |
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| 154 | #define MT6397_VCORE_CON10 0x027A |
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| 155 | #define MT6397_VCORE_CON11 0x027C |
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| 156 | #define MT6397_VCORE_CON12 0x027E |
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| 157 | #define MT6397_VCORE_CON13 0x0280 |
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| 158 | #define MT6397_VCORE_CON14 0x0282 |
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| 159 | #define MT6397_VCORE_CON15 0x0284 |
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| 160 | #define MT6397_VCORE_CON16 0x0286 |
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| 161 | #define MT6397_VCORE_CON17 0x0288 |
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| 162 | #define MT6397_VCORE_CON18 0x028A |
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| 163 | #define MT6397_VGPU_CON0 0x028C |
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| 164 | #define MT6397_VGPU_CON1 0x028E |
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| 165 | #define MT6397_VGPU_CON2 0x0290 |
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| 166 | #define MT6397_VGPU_CON3 0x0292 |
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| 167 | #define MT6397_VGPU_CON4 0x0294 |
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| 168 | #define MT6397_VGPU_CON5 0x0296 |
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| 169 | #define MT6397_VGPU_CON6 0x0298 |
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| 170 | #define MT6397_VGPU_CON7 0x029A |
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| 171 | #define MT6397_VGPU_CON8 0x029C |
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| 172 | #define MT6397_VGPU_CON9 0x029E |
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| 173 | #define MT6397_VGPU_CON10 0x02A0 |
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| 174 | #define MT6397_VGPU_CON11 0x02A2 |
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| 175 | #define MT6397_VGPU_CON12 0x02A4 |
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| 176 | #define MT6397_VGPU_CON13 0x02A6 |
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| 177 | #define MT6397_VGPU_CON14 0x02A8 |
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| 178 | #define MT6397_VGPU_CON15 0x02AA |
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| 179 | #define MT6397_VGPU_CON16 0x02AC |
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| 180 | #define MT6397_VGPU_CON17 0x02AE |
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| 181 | #define MT6397_VGPU_CON18 0x02B0 |
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| 182 | #define MT6397_VIO18_CON0 0x0300 |
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| 183 | #define MT6397_VIO18_CON1 0x0302 |
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| 184 | #define MT6397_VIO18_CON2 0x0304 |
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| 185 | #define MT6397_VIO18_CON3 0x0306 |
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| 186 | #define MT6397_VIO18_CON4 0x0308 |
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| 187 | #define MT6397_VIO18_CON5 0x030A |
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| 188 | #define MT6397_VIO18_CON6 0x030C |
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| 189 | #define MT6397_VIO18_CON7 0x030E |
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| 190 | #define MT6397_VIO18_CON8 0x0310 |
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| 191 | #define MT6397_VIO18_CON9 0x0312 |
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| 192 | #define MT6397_VIO18_CON10 0x0314 |
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| 193 | #define MT6397_VIO18_CON11 0x0316 |
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| 194 | #define MT6397_VIO18_CON12 0x0318 |
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| 195 | #define MT6397_VIO18_CON13 0x031A |
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| 196 | #define MT6397_VIO18_CON14 0x031C |
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| 197 | #define MT6397_VIO18_CON15 0x031E |
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| 198 | #define MT6397_VIO18_CON16 0x0320 |
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| 199 | #define MT6397_VIO18_CON17 0x0322 |
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| 200 | #define MT6397_VIO18_CON18 0x0324 |
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| 201 | #define MT6397_VPCA7_CON0 0x0326 |
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| 202 | #define MT6397_VPCA7_CON1 0x0328 |
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| 203 | #define MT6397_VPCA7_CON2 0x032A |
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| 204 | #define MT6397_VPCA7_CON3 0x032C |
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| 205 | #define MT6397_VPCA7_CON4 0x032E |
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| 206 | #define MT6397_VPCA7_CON5 0x0330 |
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| 207 | #define MT6397_VPCA7_CON6 0x0332 |
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| 208 | #define MT6397_VPCA7_CON7 0x0334 |
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| 209 | #define MT6397_VPCA7_CON8 0x0336 |
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| 210 | #define MT6397_VPCA7_CON9 0x0338 |
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| 211 | #define MT6397_VPCA7_CON10 0x033A |
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| 212 | #define MT6397_VPCA7_CON11 0x033C |
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| 213 | #define MT6397_VPCA7_CON12 0x033E |
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| 214 | #define MT6397_VPCA7_CON13 0x0340 |
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| 215 | #define MT6397_VPCA7_CON14 0x0342 |
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| 216 | #define MT6397_VPCA7_CON15 0x0344 |
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| 217 | #define MT6397_VPCA7_CON16 0x0346 |
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| 218 | #define MT6397_VPCA7_CON17 0x0348 |
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| 219 | #define MT6397_VPCA7_CON18 0x034A |
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| 220 | #define MT6397_VSRMCA7_CON0 0x034C |
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| 221 | #define MT6397_VSRMCA7_CON1 0x034E |
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| 222 | #define MT6397_VSRMCA7_CON2 0x0350 |
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| 223 | #define MT6397_VSRMCA7_CON3 0x0352 |
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| 224 | #define MT6397_VSRMCA7_CON4 0x0354 |
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| 225 | #define MT6397_VSRMCA7_CON5 0x0356 |
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| 226 | #define MT6397_VSRMCA7_CON6 0x0358 |
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| 227 | #define MT6397_VSRMCA7_CON7 0x035A |
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| 228 | #define MT6397_VSRMCA7_CON8 0x035C |
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| 229 | #define MT6397_VSRMCA7_CON9 0x035E |
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| 230 | #define MT6397_VSRMCA7_CON10 0x0360 |
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| 231 | #define MT6397_VSRMCA7_CON11 0x0362 |
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| 232 | #define MT6397_VSRMCA7_CON12 0x0364 |
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| 233 | #define MT6397_VSRMCA7_CON13 0x0366 |
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| 234 | #define MT6397_VSRMCA7_CON14 0x0368 |
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| 235 | #define MT6397_VSRMCA7_CON15 0x036A |
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| 236 | #define MT6397_VSRMCA7_CON16 0x036C |
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| 237 | #define MT6397_VSRMCA7_CON17 0x036E |
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| 238 | #define MT6397_VSRMCA7_CON18 0x0370 |
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| 239 | #define MT6397_VSRMCA7_CON19 0x0372 |
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| 240 | #define MT6397_VSRMCA7_CON20 0x0374 |
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| 241 | #define MT6397_VSRMCA7_CON21 0x0376 |
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| 242 | #define MT6397_VDRM_CON0 0x0378 |
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| 243 | #define MT6397_VDRM_CON1 0x037A |
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| 244 | #define MT6397_VDRM_CON2 0x037C |
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| 245 | #define MT6397_VDRM_CON3 0x037E |
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| 246 | #define MT6397_VDRM_CON4 0x0380 |
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| 247 | #define MT6397_VDRM_CON5 0x0382 |
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| 248 | #define MT6397_VDRM_CON6 0x0384 |
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| 249 | #define MT6397_VDRM_CON7 0x0386 |
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| 250 | #define MT6397_VDRM_CON8 0x0388 |
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| 251 | #define MT6397_VDRM_CON9 0x038A |
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| 252 | #define MT6397_VDRM_CON10 0x038C |
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| 253 | #define MT6397_VDRM_CON11 0x038E |
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| 254 | #define MT6397_VDRM_CON12 0x0390 |
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| 255 | #define MT6397_VDRM_CON13 0x0392 |
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| 256 | #define MT6397_VDRM_CON14 0x0394 |
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| 257 | #define MT6397_VDRM_CON15 0x0396 |
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| 258 | #define MT6397_VDRM_CON16 0x0398 |
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| 259 | #define MT6397_VDRM_CON17 0x039A |
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| 260 | #define MT6397_VDRM_CON18 0x039C |
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| 261 | #define MT6397_BUCK_K_CON0 0x039E |
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| 262 | #define MT6397_BUCK_K_CON1 0x03A0 |
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| 263 | #define MT6397_ANALDO_CON0 0x0400 |
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| 264 | #define MT6397_ANALDO_CON1 0x0402 |
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| 265 | #define MT6397_ANALDO_CON2 0x0404 |
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| 266 | #define MT6397_ANALDO_CON3 0x0406 |
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| 267 | #define MT6397_ANALDO_CON4 0x0408 |
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| 268 | #define MT6397_ANALDO_CON5 0x040A |
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| 269 | #define MT6397_ANALDO_CON6 0x040C |
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| 270 | #define MT6397_ANALDO_CON7 0x040E |
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| 271 | #define MT6397_DIGLDO_CON0 0x0410 |
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| 272 | #define MT6397_DIGLDO_CON1 0x0412 |
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| 273 | #define MT6397_DIGLDO_CON2 0x0414 |
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| 274 | #define MT6397_DIGLDO_CON3 0x0416 |
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| 275 | #define MT6397_DIGLDO_CON4 0x0418 |
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| 276 | #define MT6397_DIGLDO_CON5 0x041A |
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| 277 | #define MT6397_DIGLDO_CON6 0x041C |
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| 278 | #define MT6397_DIGLDO_CON7 0x041E |
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| 279 | #define MT6397_DIGLDO_CON8 0x0420 |
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| 280 | #define MT6397_DIGLDO_CON9 0x0422 |
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| 281 | #define MT6397_DIGLDO_CON10 0x0424 |
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| 282 | #define MT6397_DIGLDO_CON11 0x0426 |
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| 283 | #define MT6397_DIGLDO_CON12 0x0428 |
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| 284 | #define MT6397_DIGLDO_CON13 0x042A |
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| 285 | #define MT6397_DIGLDO_CON14 0x042C |
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| 286 | #define MT6397_DIGLDO_CON15 0x042E |
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| 287 | #define MT6397_DIGLDO_CON16 0x0430 |
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| 288 | #define MT6397_DIGLDO_CON17 0x0432 |
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| 289 | #define MT6397_DIGLDO_CON18 0x0434 |
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| 290 | #define MT6397_DIGLDO_CON19 0x0436 |
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| 291 | #define MT6397_DIGLDO_CON20 0x0438 |
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| 292 | #define MT6397_DIGLDO_CON21 0x043A |
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| 293 | #define MT6397_DIGLDO_CON22 0x043C |
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| 294 | #define MT6397_DIGLDO_CON23 0x043E |
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| 295 | #define MT6397_DIGLDO_CON24 0x0440 |
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| 296 | #define MT6397_DIGLDO_CON25 0x0442 |
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| 297 | #define MT6397_DIGLDO_CON26 0x0444 |
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| 298 | #define MT6397_DIGLDO_CON27 0x0446 |
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| 299 | #define MT6397_DIGLDO_CON28 0x0448 |
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| 300 | #define MT6397_DIGLDO_CON29 0x044A |
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| 301 | #define MT6397_DIGLDO_CON30 0x044C |
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| 302 | #define MT6397_DIGLDO_CON31 0x044E |
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| 303 | #define MT6397_DIGLDO_CON32 0x0450 |
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| 304 | #define MT6397_DIGLDO_CON33 0x045A |
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| 305 | #define MT6397_SPK_CON0 0x0600 |
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| 306 | #define MT6397_SPK_CON1 0x0602 |
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| 307 | #define MT6397_SPK_CON2 0x0604 |
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| 308 | #define MT6397_SPK_CON3 0x0606 |
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| 309 | #define MT6397_SPK_CON4 0x0608 |
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| 310 | #define MT6397_SPK_CON5 0x060A |
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| 311 | #define MT6397_SPK_CON6 0x060C |
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| 312 | #define MT6397_SPK_CON7 0x060E |
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| 313 | #define MT6397_SPK_CON8 0x0610 |
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| 314 | #define MT6397_SPK_CON9 0x0612 |
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| 315 | #define MT6397_SPK_CON10 0x0614 |
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| 316 | #define MT6397_SPK_CON11 0x0616 |
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| 317 | #define MT6397_AUDDAC_CON0 0x0700 |
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| 318 | #define MT6397_AUDBUF_CFG0 0x0702 |
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| 319 | #define MT6397_AUDBUF_CFG1 0x0704 |
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| 320 | #define MT6397_AUDBUF_CFG2 0x0706 |
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| 321 | #define MT6397_AUDBUF_CFG3 0x0708 |
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| 322 | #define MT6397_AUDBUF_CFG4 0x070A |
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| 323 | #define MT6397_IBIASDIST_CFG0 0x070C |
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| 324 | #define MT6397_AUDACCDEPOP_CFG0 0x070E |
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| 325 | #define MT6397_AUD_IV_CFG0 0x0710 |
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| 326 | #define MT6397_AUDCLKGEN_CFG0 0x0712 |
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| 327 | #define MT6397_AUDLDO_CFG0 0x0714 |
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| 328 | #define MT6397_AUDLDO_CFG1 0x0716 |
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| 329 | #define MT6397_AUDNVREGGLB_CFG0 0x0718 |
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| 330 | #define MT6397_AUD_NCP0 0x071A |
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| 331 | #define MT6397_AUDPREAMP_CON0 0x071C |
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| 332 | #define MT6397_AUDADC_CON0 0x071E |
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| 333 | #define MT6397_AUDADC_CON1 0x0720 |
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| 334 | #define MT6397_AUDADC_CON2 0x0722 |
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| 335 | #define MT6397_AUDADC_CON3 0x0724 |
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| 336 | #define MT6397_AUDADC_CON4 0x0726 |
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| 337 | #define MT6397_AUDADC_CON5 0x0728 |
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| 338 | #define MT6397_AUDADC_CON6 0x072A |
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| 339 | #define MT6397_AUDDIGMI_CON0 0x072C |
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| 340 | #define MT6397_AUDLSBUF_CON0 0x072E |
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| 341 | #define MT6397_AUDLSBUF_CON1 0x0730 |
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| 342 | #define MT6397_AUDENCSPARE_CON0 0x0732 |
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| 343 | #define MT6397_AUDENCCLKSQ_CON0 0x0734 |
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| 344 | #define MT6397_AUDPREAMPGAIN_CON0 0x0736 |
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| 345 | #define MT6397_ZCD_CON0 0x0738 |
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| 346 | #define MT6397_ZCD_CON1 0x073A |
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| 347 | #define MT6397_ZCD_CON2 0x073C |
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| 348 | #define MT6397_ZCD_CON3 0x073E |
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| 349 | #define MT6397_ZCD_CON4 0x0740 |
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| 350 | #define MT6397_ZCD_CON5 0x0742 |
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| 351 | #define MT6397_NCP_CLKDIV_CON0 0x0744 |
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| 352 | #define MT6397_NCP_CLKDIV_CON1 0x0746 |
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| 353 | |
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| 354 | #endif /* __MFD_MT6397_REGISTERS_H__ */ |
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| 355 | |
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