1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8#ifndef __LINUX_MTD_SPINAND_H
9#define __LINUX_MTD_SPINAND_H
10
11#include <linux/mutex.h>
12#include <linux/bitops.h>
13#include <linux/device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/spi/spi.h>
17#include <linux/spi/spi-mem.h>
18
19/**
20 * Standard SPI NAND flash operations
21 */
22
23#define SPINAND_RESET_1S_0_0_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29#define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35#define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_ADDR(naddr, 0, 1), \
38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40
41#define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46
47#define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52
53#define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA)
58
59#define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, ...) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf, 1), \
70 SPI_MEM_OP_MAX_FREQ(__VA_ARGS__ + 0))
71
72#define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len) \
73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
74 SPI_MEM_OP_ADDR(2, addr, 1), \
75 SPI_MEM_OP_DUMMY(ndummy, 1), \
76 SPI_MEM_OP_DATA_IN(len, buf, 1))
77
78#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len) \
79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
80 SPI_MEM_OP_ADDR(3, addr, 1), \
81 SPI_MEM_OP_DUMMY(ndummy, 1), \
82 SPI_MEM_OP_DATA_IN(len, buf, 1))
83
84#define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len) \
85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
86 SPI_MEM_OP_ADDR(3, addr, 1), \
87 SPI_MEM_OP_DUMMY(ndummy, 1), \
88 SPI_MEM_OP_DATA_IN(len, buf, 1))
89
90#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \
91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
92 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
93 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
94 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
95 SPI_MEM_OP_MAX_FREQ(freq))
96
97#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len) \
98 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
99 SPI_MEM_OP_ADDR(2, addr, 1), \
100 SPI_MEM_OP_DUMMY(ndummy, 1), \
101 SPI_MEM_OP_DATA_IN(len, buf, 2))
102
103#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len) \
104 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
105 SPI_MEM_OP_ADDR(3, addr, 1), \
106 SPI_MEM_OP_DUMMY(ndummy, 1), \
107 SPI_MEM_OP_DATA_IN(len, buf, 2))
108
109#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \
110 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
111 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
112 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
113 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
114 SPI_MEM_OP_MAX_FREQ(freq))
115
116#define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len) \
117 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
118 SPI_MEM_OP_ADDR(2, addr, 2), \
119 SPI_MEM_OP_DUMMY(ndummy, 2), \
120 SPI_MEM_OP_DATA_IN(len, buf, 2))
121
122#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len) \
123 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
124 SPI_MEM_OP_ADDR(3, addr, 2), \
125 SPI_MEM_OP_DUMMY(ndummy, 2), \
126 SPI_MEM_OP_DATA_IN(len, buf, 2))
127
128#define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \
129 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
130 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
131 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
132 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
133 SPI_MEM_OP_MAX_FREQ(freq))
134
135#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len) \
136 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
137 SPI_MEM_OP_ADDR(2, addr, 1), \
138 SPI_MEM_OP_DUMMY(ndummy, 1), \
139 SPI_MEM_OP_DATA_IN(len, buf, 4))
140
141#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len) \
142 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
143 SPI_MEM_OP_ADDR(3, addr, 1), \
144 SPI_MEM_OP_DUMMY(ndummy, 1), \
145 SPI_MEM_OP_DATA_IN(len, buf, 4))
146
147#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \
148 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
149 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
150 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
151 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
152 SPI_MEM_OP_MAX_FREQ(freq))
153
154#define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len) \
155 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
156 SPI_MEM_OP_ADDR(2, addr, 4), \
157 SPI_MEM_OP_DUMMY(ndummy, 4), \
158 SPI_MEM_OP_DATA_IN(len, buf, 4))
159
160#define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len) \
161 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
162 SPI_MEM_OP_ADDR(3, addr, 4), \
163 SPI_MEM_OP_DUMMY(ndummy, 4), \
164 SPI_MEM_OP_DATA_IN(len, buf, 4))
165
166#define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \
167 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
168 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
169 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
170 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
171 SPI_MEM_OP_MAX_FREQ(freq))
172
173#define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \
174 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
175 SPI_MEM_OP_ADDR(2, addr, 1), \
176 SPI_MEM_OP_DUMMY(ndummy, 1), \
177 SPI_MEM_OP_DATA_IN(len, buf, 8), \
178 SPI_MEM_OP_MAX_FREQ(freq))
179
180#define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \
181 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \
182 SPI_MEM_OP_ADDR(2, addr, 8), \
183 SPI_MEM_OP_DUMMY(ndummy, 8), \
184 SPI_MEM_OP_DATA_IN(len, buf, 8), \
185 SPI_MEM_OP_MAX_FREQ(freq))
186
187#define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \
188 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \
189 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
190 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
191 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
192 SPI_MEM_OP_MAX_FREQ(freq))
193
194#define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \
195 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
196 SPI_MEM_OP_ADDR(3, addr, 1), \
197 SPI_MEM_OP_NO_DUMMY, \
198 SPI_MEM_OP_NO_DATA)
199
200#define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \
201 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
202 SPI_MEM_OP_ADDR(2, addr, 1), \
203 SPI_MEM_OP_NO_DUMMY, \
204 SPI_MEM_OP_DATA_OUT(len, buf, 1))
205
206#define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \
207 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
208 SPI_MEM_OP_ADDR(2, addr, 1), \
209 SPI_MEM_OP_NO_DUMMY, \
210 SPI_MEM_OP_DATA_OUT(len, buf, 4))
211
212#define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \
213 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \
214 SPI_MEM_OP_ADDR(2, addr, 1), \
215 SPI_MEM_OP_NO_DUMMY, \
216 SPI_MEM_OP_DATA_OUT(len, buf, 8))
217
218#define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \
219 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \
220 SPI_MEM_OP_ADDR(2, addr, 8), \
221 SPI_MEM_OP_NO_DUMMY, \
222 SPI_MEM_OP_DATA_OUT(len, buf, 8))
223
224/**
225 * Standard SPI NAND flash commands
226 */
227#define SPINAND_CMD_PROG_LOAD_X4 0x32
228#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
229
230/* feature register */
231#define REG_BLOCK_LOCK 0xa0
232#define BL_ALL_UNLOCKED 0x00
233
234/* configuration register */
235#define REG_CFG 0xb0
236#define CFG_OTP_ENABLE BIT(6)
237#define CFG_ECC_ENABLE BIT(4)
238#define CFG_QUAD_ENABLE BIT(0)
239
240/* status register */
241#define REG_STATUS 0xc0
242#define STATUS_BUSY BIT(0)
243#define STATUS_ERASE_FAILED BIT(2)
244#define STATUS_PROG_FAILED BIT(3)
245#define STATUS_ECC_MASK GENMASK(5, 4)
246#define STATUS_ECC_NO_BITFLIPS (0 << 4)
247#define STATUS_ECC_HAS_BITFLIPS (1 << 4)
248#define STATUS_ECC_UNCOR_ERROR (2 << 4)
249
250struct spinand_op;
251struct spinand_device;
252
253#define SPINAND_MAX_ID_LEN 5
254/*
255 * For erase, write and read operation, we got the following timings :
256 * tBERS (erase) 1ms to 4ms
257 * tPROG 300us to 400us
258 * tREAD 25us to 100us
259 * In order to minimize latency, the min value is divided by 4 for the
260 * initial delay, and dividing by 20 for the poll delay.
261 * For reset, 5us/10us/500us if the device is respectively
262 * reading/programming/erasing when the RESET occurs. Since we always
263 * issue a RESET when the device is IDLE, 5us is selected for both initial
264 * and poll delay.
265 */
266#define SPINAND_READ_INITIAL_DELAY_US 6
267#define SPINAND_READ_POLL_DELAY_US 5
268#define SPINAND_RESET_INITIAL_DELAY_US 5
269#define SPINAND_RESET_POLL_DELAY_US 5
270#define SPINAND_WRITE_INITIAL_DELAY_US 75
271#define SPINAND_WRITE_POLL_DELAY_US 15
272#define SPINAND_ERASE_INITIAL_DELAY_US 250
273#define SPINAND_ERASE_POLL_DELAY_US 50
274
275#define SPINAND_WAITRDY_TIMEOUT_MS 400
276
277/**
278 * struct spinand_id - SPI NAND id structure
279 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
280 * be extended if required
281 * @len: ID length
282 */
283struct spinand_id {
284 u8 data[SPINAND_MAX_ID_LEN];
285 int len;
286};
287
288enum spinand_readid_method {
289 SPINAND_READID_METHOD_OPCODE,
290 SPINAND_READID_METHOD_OPCODE_ADDR,
291 SPINAND_READID_METHOD_OPCODE_DUMMY,
292};
293
294/**
295 * struct spinand_devid - SPI NAND device id structure
296 * @id: device id of current chip
297 * @len: number of bytes in device id
298 * @method: method to read chip id
299 * There are 3 possible variants:
300 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
301 * after read_id opcode.
302 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
303 * read_id opcode + 1-byte address.
304 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
305 * read_id opcode + 1 dummy byte.
306 */
307struct spinand_devid {
308 const u8 *id;
309 const u8 len;
310 const enum spinand_readid_method method;
311};
312
313/**
314 * struct manufacurer_ops - SPI NAND manufacturer specific operations
315 * @init: initialize a SPI NAND device
316 * @cleanup: cleanup a SPI NAND device
317 *
318 * Each SPI NAND manufacturer driver should implement this interface so that
319 * NAND chips coming from this vendor can be initialized properly.
320 */
321struct spinand_manufacturer_ops {
322 int (*init)(struct spinand_device *spinand);
323 void (*cleanup)(struct spinand_device *spinand);
324};
325
326/**
327 * struct spinand_manufacturer - SPI NAND manufacturer instance
328 * @id: manufacturer ID
329 * @name: manufacturer name
330 * @devid_len: number of bytes in device ID
331 * @chips: supported SPI NANDs under current manufacturer
332 * @nchips: number of SPI NANDs available in chips array
333 * @ops: manufacturer operations
334 */
335struct spinand_manufacturer {
336 u8 id;
337 char *name;
338 const struct spinand_info *chips;
339 const size_t nchips;
340 const struct spinand_manufacturer_ops *ops;
341};
342
343/* SPI NAND manufacturers */
344extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
345extern const struct spinand_manufacturer ato_spinand_manufacturer;
346extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
347extern const struct spinand_manufacturer foresee_spinand_manufacturer;
348extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
349extern const struct spinand_manufacturer macronix_spinand_manufacturer;
350extern const struct spinand_manufacturer micron_spinand_manufacturer;
351extern const struct spinand_manufacturer paragon_spinand_manufacturer;
352extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
353extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
354extern const struct spinand_manufacturer winbond_spinand_manufacturer;
355extern const struct spinand_manufacturer xtx_spinand_manufacturer;
356
357/**
358 * struct spinand_op_variants - SPI NAND operation variants
359 * @ops: the list of variants for a given operation
360 * @nops: the number of variants
361 *
362 * Some operations like read-from-cache/write-to-cache have several variants
363 * depending on the number of IO lines you use to transfer data or address
364 * cycles. This structure is a way to describe the different variants supported
365 * by a chip and let the core pick the best one based on the SPI mem controller
366 * capabilities.
367 */
368struct spinand_op_variants {
369 const struct spi_mem_op *ops;
370 unsigned int nops;
371};
372
373#define SPINAND_OP_VARIANTS(name, ...) \
374 const struct spinand_op_variants name = { \
375 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
376 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
377 sizeof(struct spi_mem_op), \
378 }
379
380/**
381 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
382 * chip
383 * @get_status: get the ECC status. Should return a positive number encoding
384 * the number of corrected bitflips if correction was possible or
385 * -EBADMSG if there are uncorrectable errors. I can also return
386 * other negative error codes if the error is not caused by
387 * uncorrectable bitflips
388 * @ooblayout: the OOB layout used by the on-die ECC implementation
389 */
390struct spinand_ecc_info {
391 int (*get_status)(struct spinand_device *spinand, u8 status);
392 const struct mtd_ooblayout_ops *ooblayout;
393};
394
395#define SPINAND_HAS_QE_BIT BIT(0)
396#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
397#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
398#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
399#define SPINAND_NO_RAW_ACCESS BIT(4)
400
401/**
402 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
403 * @status: status of the last wait operation that will be used in case
404 * ->get_status() is not populated by the spinand device.
405 */
406struct spinand_ondie_ecc_conf {
407 u8 status;
408};
409
410/**
411 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area
412 * @npages: number of pages in the OTP
413 * @start_page: start page of the user/factory OTP area.
414 */
415struct spinand_otp_layout {
416 unsigned int npages;
417 unsigned int start_page;
418};
419
420/**
421 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area
422 * @info: get the OTP area information
423 * @read: read from the SPI NAND OTP area
424 */
425struct spinand_fact_otp_ops {
426 int (*info)(struct spinand_device *spinand, size_t len,
427 struct otp_info *buf, size_t *retlen);
428 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
429 size_t *retlen, u8 *buf);
430};
431
432/**
433 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area
434 * @info: get the OTP area information
435 * @lock: lock an OTP region
436 * @erase: erase an OTP region
437 * @read: read from the SPI NAND OTP area
438 * @write: write to the SPI NAND OTP area
439 */
440struct spinand_user_otp_ops {
441 int (*info)(struct spinand_device *spinand, size_t len,
442 struct otp_info *buf, size_t *retlen);
443 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len);
444 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len);
445 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
446 size_t *retlen, u8 *buf);
447 int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
448 size_t *retlen, const u8 *buf);
449};
450
451/**
452 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area
453 * @layout: OTP region layout
454 * @ops: OTP access ops
455 */
456struct spinand_fact_otp {
457 const struct spinand_otp_layout layout;
458 const struct spinand_fact_otp_ops *ops;
459};
460
461/**
462 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area
463 * @layout: OTP region layout
464 * @ops: OTP access ops
465 */
466struct spinand_user_otp {
467 const struct spinand_otp_layout layout;
468 const struct spinand_user_otp_ops *ops;
469};
470
471/**
472 * struct spinand_info - Structure used to describe SPI NAND chips
473 * @model: model name
474 * @devid: device ID
475 * @flags: OR-ing of the SPINAND_XXX flags
476 * @memorg: memory organization
477 * @eccreq: ECC requirements
478 * @eccinfo: on-die ECC info
479 * @op_variants: operations variants
480 * @op_variants.read_cache: variants of the read-cache operation
481 * @op_variants.write_cache: variants of the write-cache operation
482 * @op_variants.update_cache: variants of the update-cache operation
483 * @select_target: function used to select a target/die. Required only for
484 * multi-die chips
485 * @set_cont_read: enable/disable continuous cached reads
486 * @fact_otp: SPI NAND factory OTP info.
487 * @user_otp: SPI NAND user OTP info.
488 * @read_retries: the number of read retry modes supported
489 * @set_read_retry: enable/disable read retry for data recovery
490 *
491 * Each SPI NAND manufacturer driver should have a spinand_info table
492 * describing all the chips supported by the driver.
493 */
494struct spinand_info {
495 const char *model;
496 struct spinand_devid devid;
497 u32 flags;
498 struct nand_memory_organization memorg;
499 struct nand_ecc_props eccreq;
500 struct spinand_ecc_info eccinfo;
501 struct {
502 const struct spinand_op_variants *read_cache;
503 const struct spinand_op_variants *write_cache;
504 const struct spinand_op_variants *update_cache;
505 } op_variants;
506 int (*select_target)(struct spinand_device *spinand,
507 unsigned int target);
508 int (*set_cont_read)(struct spinand_device *spinand,
509 bool enable);
510 struct spinand_fact_otp fact_otp;
511 struct spinand_user_otp user_otp;
512 unsigned int read_retries;
513 int (*set_read_retry)(struct spinand_device *spinand,
514 unsigned int read_retry);
515};
516
517#define SPINAND_ID(__method, ...) \
518 { \
519 .id = (const u8[]){ __VA_ARGS__ }, \
520 .len = sizeof((u8[]){ __VA_ARGS__ }), \
521 .method = __method, \
522 }
523
524#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
525 { \
526 .read_cache = __read, \
527 .write_cache = __write, \
528 .update_cache = __update, \
529 }
530
531#define SPINAND_ECCINFO(__ooblayout, __get_status) \
532 .eccinfo = { \
533 .ooblayout = __ooblayout, \
534 .get_status = __get_status, \
535 }
536
537#define SPINAND_SELECT_TARGET(__func) \
538 .select_target = __func
539
540#define SPINAND_CONT_READ(__set_cont_read) \
541 .set_cont_read = __set_cont_read
542
543#define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \
544 .fact_otp = { \
545 .layout = { \
546 .npages = __npages, \
547 .start_page = __start_page, \
548 }, \
549 .ops = __ops, \
550 }
551
552#define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \
553 .user_otp = { \
554 .layout = { \
555 .npages = __npages, \
556 .start_page = __start_page, \
557 }, \
558 .ops = __ops, \
559 }
560
561#define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \
562 .read_retries = __read_retries, \
563 .set_read_retry = __set_read_retry
564
565#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
566 __flags, ...) \
567 { \
568 .model = __model, \
569 .devid = __id, \
570 .memorg = __memorg, \
571 .eccreq = __eccreq, \
572 .op_variants = __op_variants, \
573 .flags = __flags, \
574 __VA_ARGS__ \
575 }
576
577struct spinand_dirmap {
578 struct spi_mem_dirmap_desc *wdesc;
579 struct spi_mem_dirmap_desc *rdesc;
580 struct spi_mem_dirmap_desc *wdesc_ecc;
581 struct spi_mem_dirmap_desc *rdesc_ecc;
582};
583
584/**
585 * struct spinand_device - SPI NAND device instance
586 * @base: NAND device instance
587 * @spimem: pointer to the SPI mem object
588 * @lock: lock used to serialize accesses to the NAND
589 * @id: NAND ID as returned by READ_ID
590 * @flags: NAND flags
591 * @op_templates: various SPI mem op templates
592 * @op_templates.read_cache: read cache op template
593 * @op_templates.write_cache: write cache op template
594 * @op_templates.update_cache: update cache op template
595 * @select_target: select a specific target/die. Usually called before sending
596 * a command addressing a page or an eraseblock embedded in
597 * this die. Only required if your chip exposes several dies
598 * @cur_target: currently selected target/die
599 * @eccinfo: on-die ECC information
600 * @cfg_cache: config register cache. One entry per die
601 * @databuf: bounce buffer for data
602 * @oobbuf: bounce buffer for OOB data
603 * @scratchbuf: buffer used for everything but page accesses. This is needed
604 * because the spi-mem interface explicitly requests that buffers
605 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
606 * the stack
607 * @manufacturer: SPI NAND manufacturer information
608 * @cont_read_possible: Field filled by the core once the whole system
609 * configuration is known to tell whether continuous reads are
610 * suitable to use or not in general with this chip/configuration.
611 * A per-transfer check must of course be done to ensure it is
612 * actually relevant to enable this feature.
613 * @set_cont_read: Enable/disable the continuous read feature
614 * @priv: manufacturer private data
615 * @fact_otp: SPI NAND factory OTP info.
616 * @user_otp: SPI NAND user OTP info.
617 * @read_retries: the number of read retry modes supported
618 * @set_read_retry: Enable/disable the read retry feature
619 */
620struct spinand_device {
621 struct nand_device base;
622 struct spi_mem *spimem;
623 struct mutex lock;
624 struct spinand_id id;
625 u32 flags;
626
627 struct {
628 const struct spi_mem_op *read_cache;
629 const struct spi_mem_op *write_cache;
630 const struct spi_mem_op *update_cache;
631 } op_templates;
632
633 struct spinand_dirmap *dirmaps;
634
635 int (*select_target)(struct spinand_device *spinand,
636 unsigned int target);
637 unsigned int cur_target;
638
639 struct spinand_ecc_info eccinfo;
640
641 u8 *cfg_cache;
642 u8 *databuf;
643 u8 *oobbuf;
644 u8 *scratchbuf;
645 const struct spinand_manufacturer *manufacturer;
646 void *priv;
647
648 bool cont_read_possible;
649 int (*set_cont_read)(struct spinand_device *spinand,
650 bool enable);
651
652 const struct spinand_fact_otp *fact_otp;
653 const struct spinand_user_otp *user_otp;
654
655 unsigned int read_retries;
656 int (*set_read_retry)(struct spinand_device *spinand,
657 unsigned int retry_mode);
658};
659
660/**
661 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
662 * @mtd: MTD instance
663 *
664 * Return: the SPI NAND device attached to @mtd.
665 */
666static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
667{
668 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
669}
670
671/**
672 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
673 * @spinand: SPI NAND device
674 *
675 * Return: the MTD device embedded in @spinand.
676 */
677static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
678{
679 return nanddev_to_mtd(nand: &spinand->base);
680}
681
682/**
683 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
684 * @nand: NAND object
685 *
686 * Return: the SPI NAND device embedding @nand.
687 */
688static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
689{
690 return container_of(nand, struct spinand_device, base);
691}
692
693/**
694 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
695 * @spinand: SPI NAND device
696 *
697 * Return: the NAND device embedded in @spinand.
698 */
699static inline struct nand_device *
700spinand_to_nand(struct spinand_device *spinand)
701{
702 return &spinand->base;
703}
704
705/**
706 * spinand_set_of_node - Attach a DT node to a SPI NAND device
707 * @spinand: SPI NAND device
708 * @np: DT node
709 *
710 * Attach a DT node to a SPI NAND device.
711 */
712static inline void spinand_set_of_node(struct spinand_device *spinand,
713 struct device_node *np)
714{
715 nanddev_set_of_node(nand: &spinand->base, np);
716}
717
718int spinand_match_and_init(struct spinand_device *spinand,
719 const struct spinand_info *table,
720 unsigned int table_size,
721 enum spinand_readid_method rdid_method);
722
723int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
724int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
725int spinand_select_target(struct spinand_device *spinand, unsigned int target);
726
727int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us,
728 unsigned long poll_delay_us, u8 *s);
729
730int spinand_read_page(struct spinand_device *spinand,
731 const struct nand_page_io_req *req);
732
733int spinand_write_page(struct spinand_device *spinand,
734 const struct nand_page_io_req *req);
735
736size_t spinand_otp_page_size(struct spinand_device *spinand);
737size_t spinand_fact_otp_size(struct spinand_device *spinand);
738size_t spinand_user_otp_size(struct spinand_device *spinand);
739
740int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs,
741 size_t len, size_t *retlen, u8 *buf);
742int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs,
743 size_t len, size_t *retlen, u8 *buf);
744int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs,
745 size_t len, size_t *retlen, const u8 *buf);
746
747int spinand_set_mtd_otp_ops(struct spinand_device *spinand);
748
749#endif /* __LINUX_MTD_SPINAND_H */
750

source code of linux/include/linux/mtd/spinand.h