1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * OMAP Smartreflex Defines and Routines |
4 | * |
5 | * Author: Thara Gopinath <thara@ti.com> |
6 | * |
7 | * Copyright (C) 2010 Texas Instruments, Inc. |
8 | * Thara Gopinath <thara@ti.com> |
9 | * |
10 | * Copyright (C) 2008 Nokia Corporation |
11 | * Kalle Jokiniemi |
12 | * |
13 | * Copyright (C) 2007 Texas Instruments, Inc. |
14 | * Lesly A M <x0080970@ti.com> |
15 | */ |
16 | |
17 | #ifndef __POWER_SMARTREFLEX_H |
18 | #define __POWER_SMARTREFLEX_H |
19 | |
20 | #include <linux/types.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/delay.h> |
23 | #include <linux/platform_data/voltage-omap.h> |
24 | |
25 | /* |
26 | * Different Smartreflex IPs version. The v1 is the 65nm version used in |
27 | * OMAP3430. The v2 is the update for the 45nm version of the IP |
28 | * used in OMAP3630 and OMAP4430 |
29 | */ |
30 | #define SR_TYPE_V1 1 |
31 | #define SR_TYPE_V2 2 |
32 | |
33 | /* SMART REFLEX REG ADDRESS OFFSET */ |
34 | #define SRCONFIG 0x00 |
35 | #define SRSTATUS 0x04 |
36 | #define SENVAL 0x08 |
37 | #define SENMIN 0x0C |
38 | #define SENMAX 0x10 |
39 | #define SENAVG 0x14 |
40 | #define AVGWEIGHT 0x18 |
41 | #define NVALUERECIPROCAL 0x1c |
42 | #define SENERROR_V1 0x20 |
43 | #define ERRCONFIG_V1 0x24 |
44 | #define IRQ_EOI 0x20 |
45 | #define IRQSTATUS_RAW 0x24 |
46 | #define IRQSTATUS 0x28 |
47 | #define IRQENABLE_SET 0x2C |
48 | #define IRQENABLE_CLR 0x30 |
49 | #define SENERROR_V2 0x34 |
50 | #define ERRCONFIG_V2 0x38 |
51 | |
52 | /* Bit/Shift Positions */ |
53 | |
54 | /* SRCONFIG */ |
55 | #define SRCONFIG_ACCUMDATA_SHIFT 22 |
56 | #define SRCONFIG_SRCLKLENGTH_SHIFT 12 |
57 | #define SRCONFIG_SENNENABLE_V1_SHIFT 5 |
58 | #define SRCONFIG_SENPENABLE_V1_SHIFT 3 |
59 | #define SRCONFIG_SENNENABLE_V2_SHIFT 1 |
60 | #define SRCONFIG_SENPENABLE_V2_SHIFT 0 |
61 | #define SRCONFIG_CLKCTRL_SHIFT 0 |
62 | |
63 | #define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22) |
64 | |
65 | #define SRCONFIG_SRENABLE BIT(11) |
66 | #define SRCONFIG_SENENABLE BIT(10) |
67 | #define SRCONFIG_ERRGEN_EN BIT(9) |
68 | #define SRCONFIG_MINMAXAVG_EN BIT(8) |
69 | #define SRCONFIG_DELAYCTRL BIT(2) |
70 | |
71 | /* AVGWEIGHT */ |
72 | #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2 |
73 | #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0 |
74 | |
75 | /* NVALUERECIPROCAL */ |
76 | #define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 |
77 | #define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 |
78 | #define NVALUERECIPROCAL_RNSENP_SHIFT 8 |
79 | #define NVALUERECIPROCAL_RNSENN_SHIFT 0 |
80 | |
81 | /* ERRCONFIG */ |
82 | #define ERRCONFIG_ERRWEIGHT_SHIFT 16 |
83 | #define ERRCONFIG_ERRMAXLIMIT_SHIFT 8 |
84 | #define ERRCONFIG_ERRMINLIMIT_SHIFT 0 |
85 | |
86 | #define SR_ERRWEIGHT_MASK (0x07 << 16) |
87 | #define SR_ERRMAXLIMIT_MASK (0xff << 8) |
88 | #define SR_ERRMINLIMIT_MASK (0xff << 0) |
89 | |
90 | #define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31) |
91 | #define ERRCONFIG_VPBOUNDINTST_V1 BIT(30) |
92 | #define ERRCONFIG_MCUACCUMINTEN BIT(29) |
93 | #define ERRCONFIG_MCUACCUMINTST BIT(28) |
94 | #define ERRCONFIG_MCUVALIDINTEN BIT(27) |
95 | #define ERRCONFIG_MCUVALIDINTST BIT(26) |
96 | #define ERRCONFIG_MCUBOUNDINTEN BIT(25) |
97 | #define ERRCONFIG_MCUBOUNDINTST BIT(24) |
98 | #define ERRCONFIG_MCUDISACKINTEN BIT(23) |
99 | #define ERRCONFIG_VPBOUNDINTST_V2 BIT(23) |
100 | #define ERRCONFIG_MCUDISACKINTST BIT(22) |
101 | #define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22) |
102 | |
103 | #define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \ |
104 | ERRCONFIG_MCUACCUMINTST | \ |
105 | ERRCONFIG_MCUVALIDINTST | \ |
106 | ERRCONFIG_MCUBOUNDINTST | \ |
107 | ERRCONFIG_MCUDISACKINTST) |
108 | /* IRQSTATUS */ |
109 | #define IRQSTATUS_MCUACCUMINT BIT(3) |
110 | #define IRQSTATUS_MCVALIDINT BIT(2) |
111 | #define IRQSTATUS_MCBOUNDSINT BIT(1) |
112 | #define IRQSTATUS_MCUDISABLEACKINT BIT(0) |
113 | |
114 | /* IRQENABLE_SET and IRQENABLE_CLEAR */ |
115 | #define IRQENABLE_MCUACCUMINT BIT(3) |
116 | #define IRQENABLE_MCUVALIDINT BIT(2) |
117 | #define IRQENABLE_MCUBOUNDSINT BIT(1) |
118 | #define IRQENABLE_MCUDISABLEACKINT BIT(0) |
119 | |
120 | /* Common Bit values */ |
121 | |
122 | #define SRCLKLENGTH_12MHZ_SYSCLK 0x3c |
123 | #define SRCLKLENGTH_13MHZ_SYSCLK 0x41 |
124 | #define SRCLKLENGTH_19MHZ_SYSCLK 0x60 |
125 | #define SRCLKLENGTH_26MHZ_SYSCLK 0x82 |
126 | #define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 |
127 | |
128 | /* |
129 | * 3430 specific values. Maybe these should be passed from board file or |
130 | * pmic structures. |
131 | */ |
132 | #define OMAP3430_SR_ACCUMDATA 0x1f4 |
133 | |
134 | #define OMAP3430_SR1_SENPAVGWEIGHT 0x03 |
135 | #define OMAP3430_SR1_SENNAVGWEIGHT 0x03 |
136 | |
137 | #define OMAP3430_SR2_SENPAVGWEIGHT 0x01 |
138 | #define OMAP3430_SR2_SENNAVGWEIGHT 0x01 |
139 | |
140 | #define OMAP3430_SR_ERRWEIGHT 0x04 |
141 | #define OMAP3430_SR_ERRMAXLIMIT 0x02 |
142 | |
143 | enum sr_instance { |
144 | OMAP_SR_MPU, /* shared with iva on omap3 */ |
145 | OMAP_SR_CORE, |
146 | OMAP_SR_IVA, |
147 | OMAP_SR_NR, |
148 | }; |
149 | |
150 | struct omap_sr { |
151 | char *name; |
152 | struct list_head node; |
153 | struct platform_device *pdev; |
154 | struct omap_sr_nvalue_table *nvalue_table; |
155 | struct voltagedomain *voltdm; |
156 | struct dentry *dbg_dir; |
157 | unsigned int irq; |
158 | struct clk *fck; |
159 | int srid; |
160 | int ip_type; |
161 | int nvalue_count; |
162 | bool autocomp_active; |
163 | u32 clk_length; |
164 | u32 err_weight; |
165 | u32 err_minlimit; |
166 | u32 err_maxlimit; |
167 | u32 accum_data; |
168 | u32 senn_avgweight; |
169 | u32 senp_avgweight; |
170 | u32 senp_mod; |
171 | u32 senn_mod; |
172 | void __iomem *base; |
173 | unsigned long enabled:1; |
174 | }; |
175 | |
176 | /** |
177 | * test_cond_timeout - busy-loop, testing a condition |
178 | * @cond: condition to test until it evaluates to true |
179 | * @timeout: maximum number of microseconds in the timeout |
180 | * @index: loop index (integer) |
181 | * |
182 | * Loop waiting for @cond to become true or until at least @timeout |
183 | * microseconds have passed. To use, define some integer @index in the |
184 | * calling code. After running, if @index == @timeout, then the loop has |
185 | * timed out. |
186 | * |
187 | * Copied from omap_test_timeout */ |
188 | #define sr_test_cond_timeout(cond, timeout, index) \ |
189 | ({ \ |
190 | for (index = 0; index < timeout; index++) { \ |
191 | if (cond) \ |
192 | break; \ |
193 | udelay(1); \ |
194 | } \ |
195 | }) |
196 | |
197 | /** |
198 | * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass |
199 | * pmic specific info to smartreflex driver |
200 | * |
201 | * @sr_pmic_init: API to initialize smartreflex on the PMIC side. |
202 | */ |
203 | struct omap_sr_pmic_data { |
204 | void (*sr_pmic_init) (void); |
205 | }; |
206 | |
207 | /** |
208 | * struct omap_smartreflex_dev_attr - Smartreflex Device attribute. |
209 | * |
210 | * @sensor_voltdm_name: Name of voltdomain of SR instance |
211 | */ |
212 | struct omap_smartreflex_dev_attr { |
213 | const char *sensor_voltdm_name; |
214 | }; |
215 | |
216 | /* |
217 | * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. |
218 | * The smartreflex class driver should pass the class type. |
219 | * Should be used to populate the class_type field of the |
220 | * omap_smartreflex_class_data structure. |
221 | */ |
222 | #define SR_CLASS1 0x1 |
223 | #define SR_CLASS2 0x2 |
224 | #define SR_CLASS3 0x3 |
225 | |
226 | /** |
227 | * struct omap_sr_class_data - Smartreflex class driver info |
228 | * |
229 | * @enable: API to enable a particular class smaartreflex. |
230 | * @disable: API to disable a particular class smartreflex. |
231 | * @configure: API to configure a particular class smartreflex. |
232 | * @notify: API to notify the class driver about an event in SR. |
233 | * Not needed for class3. |
234 | * @notify_flags: specify the events to be notified to the class driver |
235 | * @class_type: specify which smartreflex class. |
236 | * Can be used by the SR driver to take any class |
237 | * based decisions. |
238 | */ |
239 | struct omap_sr_class_data { |
240 | int (*enable)(struct omap_sr *sr); |
241 | int (*disable)(struct omap_sr *sr, int is_volt_reset); |
242 | int (*configure)(struct omap_sr *sr); |
243 | int (*notify)(struct omap_sr *sr, u32 status); |
244 | u8 notify_flags; |
245 | u8 class_type; |
246 | }; |
247 | |
248 | /** |
249 | * struct omap_sr_nvalue_table - Smartreflex n-target value info |
250 | * |
251 | * @efuse_offs: The offset of the efuse where n-target values are stored. |
252 | * @nvalue: The n-target value. |
253 | * @errminlimit: The value of the ERRMINLIMIT bitfield for this n-target |
254 | * @volt_nominal: microvolts DC that the VDD is initially programmed to |
255 | */ |
256 | struct omap_sr_nvalue_table { |
257 | u32 efuse_offs; |
258 | u32 nvalue; |
259 | u32 errminlimit; |
260 | unsigned long volt_nominal; |
261 | }; |
262 | |
263 | /** |
264 | * struct omap_sr_data - Smartreflex platform data. |
265 | * |
266 | * @name: instance name |
267 | * @ip_type: Smartreflex IP type. |
268 | * @senp_mod: SENPENABLE value of the sr CONFIG register |
269 | * @senn_mod: SENNENABLE value for sr CONFIG register |
270 | * @err_weight ERRWEIGHT value of the sr ERRCONFIG register |
271 | * @err_maxlimit ERRMAXLIMIT value of the sr ERRCONFIG register |
272 | * @accum_data ACCUMDATA value of the sr CONFIG register |
273 | * @senn_avgweight SENNAVGWEIGHT value of the sr AVGWEIGHT register |
274 | * @senp_avgweight SENPAVGWEIGHT value of the sr AVGWEIGHT register |
275 | * @nvalue_count: Number of distinct nvalues in the nvalue table |
276 | * @nvalue_table: table containing the efuse offsets and nvalues |
277 | * corresponding to them. |
278 | * @voltdm: Pointer to the voltage domain associated with the SR |
279 | */ |
280 | struct omap_sr_data { |
281 | const char *name; |
282 | int ip_type; |
283 | u32 senp_mod; |
284 | u32 senn_mod; |
285 | u32 err_weight; |
286 | u32 err_maxlimit; |
287 | u32 accum_data; |
288 | u32 senn_avgweight; |
289 | u32 senp_avgweight; |
290 | int nvalue_count; |
291 | struct omap_sr_nvalue_table *nvalue_table; |
292 | struct voltagedomain *voltdm; |
293 | }; |
294 | |
295 | |
296 | extern struct omap_sr_data omap_sr_pdata[OMAP_SR_NR]; |
297 | |
298 | #ifdef CONFIG_POWER_AVS_OMAP |
299 | |
300 | /* Smartreflex module enable/disable interface */ |
301 | void omap_sr_enable(struct voltagedomain *voltdm); |
302 | void omap_sr_disable(struct voltagedomain *voltdm); |
303 | void omap_sr_disable_reset_volt(struct voltagedomain *voltdm); |
304 | |
305 | /* Smartreflex driver hooks to be called from Smartreflex class driver */ |
306 | int sr_enable(struct omap_sr *sr, unsigned long volt); |
307 | void sr_disable(struct omap_sr *sr); |
308 | int sr_configure_errgen(struct omap_sr *sr); |
309 | int sr_disable_errgen(struct omap_sr *sr); |
310 | int sr_configure_minmax(struct omap_sr *sr); |
311 | |
312 | /* API to register the smartreflex class driver with the smartreflex driver */ |
313 | int sr_register_class(struct omap_sr_class_data *class_data); |
314 | #else |
315 | static inline void omap_sr_enable(struct voltagedomain *voltdm) {} |
316 | static inline void omap_sr_disable(struct voltagedomain *voltdm) {} |
317 | static inline void omap_sr_disable_reset_volt( |
318 | struct voltagedomain *voltdm) {} |
319 | #endif |
320 | #endif |
321 | |