1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Simple Reset Controller ops |
4 | * |
5 | * Based on Allwinner SoCs Reset Controller driver |
6 | * |
7 | * Copyright 2013 Maxime Ripard |
8 | * |
9 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
10 | */ |
11 | |
12 | #ifndef __RESET_SIMPLE_H__ |
13 | #define __RESET_SIMPLE_H__ |
14 | |
15 | #include <linux/io.h> |
16 | #include <linux/reset-controller.h> |
17 | #include <linux/spinlock.h> |
18 | |
19 | /** |
20 | * struct reset_simple_data - driver data for simple reset controllers |
21 | * @lock: spinlock to protect registers during read-modify-write cycles |
22 | * @membase: memory mapped I/O register range |
23 | * @rcdev: reset controller device base structure |
24 | * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits |
25 | * are set to assert the reset. Note that this says nothing about |
26 | * the voltage level of the actual reset line. |
27 | * @status_active_low: if true, bits read back as cleared while the reset is |
28 | * asserted. Otherwise, bits read back as set while the |
29 | * reset is asserted. |
30 | * @reset_us: Minimum delay in microseconds needed that needs to be |
31 | * waited for between an assert and a deassert to reset the |
32 | * device. If multiple consumers with different delay |
33 | * requirements are connected to this controller, it must |
34 | * be the largest minimum delay. 0 means that such a delay is |
35 | * unknown and the reset operation is unsupported. |
36 | */ |
37 | struct reset_simple_data { |
38 | spinlock_t lock; |
39 | void __iomem *membase; |
40 | struct reset_controller_dev rcdev; |
41 | bool active_low; |
42 | bool status_active_low; |
43 | unsigned int reset_us; |
44 | }; |
45 | |
46 | extern const struct reset_control_ops reset_simple_ops; |
47 | |
48 | #endif /* __RESET_SIMPLE_H__ */ |
49 | |