1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #ifndef _LINUX_QCOM_GENI_SE |
7 | #define _LINUX_QCOM_GENI_SE |
8 | |
9 | #include <linux/interconnect.h> |
10 | |
11 | /** |
12 | * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines |
13 | * |
14 | * @GENI_SE_INVALID: Invalid mode |
15 | * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO |
16 | * by programmed IO method |
17 | * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred |
18 | * with SE by DMAengine internal to SE |
19 | * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine |
20 | * configured by a firmware residing on a GSI engine. This DMA name is |
21 | * interchangeably used as GSI or GPI which seem to imply the same DMAengine |
22 | */ |
23 | |
24 | enum geni_se_xfer_mode { |
25 | GENI_SE_INVALID, |
26 | GENI_SE_FIFO, |
27 | GENI_SE_DMA, |
28 | GENI_GPI_DMA, |
29 | }; |
30 | |
31 | /* Protocols supported by GENI Serial Engines */ |
32 | enum geni_se_protocol_type { |
33 | GENI_SE_NONE, |
34 | GENI_SE_SPI, |
35 | GENI_SE_UART, |
36 | GENI_SE_I2C, |
37 | GENI_SE_I3C, |
38 | GENI_SE_SPI_SLAVE, |
39 | }; |
40 | |
41 | struct geni_wrapper; |
42 | struct clk; |
43 | |
44 | enum geni_icc_path_index { |
45 | GENI_TO_CORE, |
46 | CPU_TO_GENI, |
47 | GENI_TO_DDR |
48 | }; |
49 | |
50 | struct geni_icc_path { |
51 | struct icc_path *path; |
52 | unsigned int avg_bw; |
53 | }; |
54 | |
55 | /** |
56 | * struct geni_se - GENI Serial Engine |
57 | * @base: Base Address of the Serial Engine's register block |
58 | * @dev: Pointer to the Serial Engine device |
59 | * @wrapper: Pointer to the parent QUP Wrapper core |
60 | * @clk: Handle to the core serial engine clock |
61 | * @num_clk_levels: Number of valid clock levels in clk_perf_tbl |
62 | * @clk_perf_tbl: Table of clock frequency input to serial engine clock |
63 | * @icc_paths: Array of ICC paths for SE |
64 | */ |
65 | struct geni_se { |
66 | void __iomem *base; |
67 | struct device *dev; |
68 | struct geni_wrapper *wrapper; |
69 | struct clk *clk; |
70 | unsigned int num_clk_levels; |
71 | unsigned long *clk_perf_tbl; |
72 | struct geni_icc_path icc_paths[3]; |
73 | }; |
74 | |
75 | /* Common SE registers */ |
76 | #define GENI_FORCE_DEFAULT_REG 0x20 |
77 | #define GENI_OUTPUT_CTRL 0x24 |
78 | #define SE_GENI_STATUS 0x40 |
79 | #define GENI_SER_M_CLK_CFG 0x48 |
80 | #define GENI_SER_S_CLK_CFG 0x4c |
81 | #define GENI_IF_DISABLE_RO 0x64 |
82 | #define GENI_FW_REVISION_RO 0x68 |
83 | #define SE_GENI_CLK_SEL 0x7c |
84 | #define SE_GENI_CFG_SEQ_START 0x84 |
85 | #define SE_GENI_DMA_MODE_EN 0x258 |
86 | #define SE_GENI_M_CMD0 0x600 |
87 | #define SE_GENI_M_CMD_CTRL_REG 0x604 |
88 | #define SE_GENI_M_IRQ_STATUS 0x610 |
89 | #define SE_GENI_M_IRQ_EN 0x614 |
90 | #define SE_GENI_M_IRQ_CLEAR 0x618 |
91 | #define SE_GENI_S_CMD0 0x630 |
92 | #define SE_GENI_S_CMD_CTRL_REG 0x634 |
93 | #define SE_GENI_S_IRQ_STATUS 0x640 |
94 | #define SE_GENI_S_IRQ_EN 0x644 |
95 | #define SE_GENI_S_IRQ_CLEAR 0x648 |
96 | #define SE_GENI_TX_FIFOn 0x700 |
97 | #define SE_GENI_RX_FIFOn 0x780 |
98 | #define SE_GENI_TX_FIFO_STATUS 0x800 |
99 | #define SE_GENI_RX_FIFO_STATUS 0x804 |
100 | #define SE_GENI_TX_WATERMARK_REG 0x80c |
101 | #define SE_GENI_RX_WATERMARK_REG 0x810 |
102 | #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 |
103 | #define SE_GENI_IOS 0x908 |
104 | #define SE_DMA_TX_IRQ_STAT 0xc40 |
105 | #define SE_DMA_TX_IRQ_CLR 0xc44 |
106 | #define SE_DMA_TX_FSM_RST 0xc58 |
107 | #define SE_DMA_RX_IRQ_STAT 0xd40 |
108 | #define SE_DMA_RX_IRQ_CLR 0xd44 |
109 | #define SE_DMA_RX_LEN_IN 0xd54 |
110 | #define SE_DMA_RX_FSM_RST 0xd58 |
111 | #define SE_HW_PARAM_0 0xe24 |
112 | #define SE_HW_PARAM_1 0xe28 |
113 | |
114 | /* GENI_FORCE_DEFAULT_REG fields */ |
115 | #define FORCE_DEFAULT BIT(0) |
116 | |
117 | /* GENI_OUTPUT_CTRL fields */ |
118 | #define GENI_IO_MUX_0_EN BIT(0) |
119 | |
120 | /* GENI_STATUS fields */ |
121 | #define M_GENI_CMD_ACTIVE BIT(0) |
122 | #define S_GENI_CMD_ACTIVE BIT(12) |
123 | |
124 | /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ |
125 | #define SER_CLK_EN BIT(0) |
126 | #define CLK_DIV_MSK GENMASK(15, 4) |
127 | #define CLK_DIV_SHFT 4 |
128 | |
129 | /* GENI_IF_DISABLE_RO fields */ |
130 | #define FIFO_IF_DISABLE (BIT(0)) |
131 | |
132 | /* GENI_FW_REVISION_RO fields */ |
133 | #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) |
134 | #define FW_REV_PROTOCOL_SHFT 8 |
135 | |
136 | /* GENI_CLK_SEL fields */ |
137 | #define CLK_SEL_MSK GENMASK(2, 0) |
138 | |
139 | /* SE_GENI_CFG_SEQ_START fields */ |
140 | #define START_TRIGGER BIT(0) |
141 | |
142 | /* SE_GENI_DMA_MODE_EN */ |
143 | #define GENI_DMA_MODE_EN BIT(0) |
144 | |
145 | /* GENI_M_CMD0 fields */ |
146 | #define M_OPCODE_MSK GENMASK(31, 27) |
147 | #define M_OPCODE_SHFT 27 |
148 | #define M_PARAMS_MSK GENMASK(26, 0) |
149 | |
150 | /* GENI_M_CMD_CTRL_REG */ |
151 | #define M_GENI_CMD_CANCEL BIT(2) |
152 | #define M_GENI_CMD_ABORT BIT(1) |
153 | #define M_GENI_DISABLE BIT(0) |
154 | |
155 | /* GENI_S_CMD0 fields */ |
156 | #define S_OPCODE_MSK GENMASK(31, 27) |
157 | #define S_OPCODE_SHFT 27 |
158 | #define S_PARAMS_MSK GENMASK(26, 0) |
159 | |
160 | /* GENI_S_CMD_CTRL_REG */ |
161 | #define S_GENI_CMD_CANCEL BIT(2) |
162 | #define S_GENI_CMD_ABORT BIT(1) |
163 | #define S_GENI_DISABLE BIT(0) |
164 | |
165 | /* GENI_M_IRQ_EN fields */ |
166 | #define M_CMD_DONE_EN BIT(0) |
167 | #define M_CMD_OVERRUN_EN BIT(1) |
168 | #define M_ILLEGAL_CMD_EN BIT(2) |
169 | #define M_CMD_FAILURE_EN BIT(3) |
170 | #define M_CMD_CANCEL_EN BIT(4) |
171 | #define M_CMD_ABORT_EN BIT(5) |
172 | #define M_TIMESTAMP_EN BIT(6) |
173 | #define M_RX_IRQ_EN BIT(7) |
174 | #define M_GP_SYNC_IRQ_0_EN BIT(8) |
175 | #define M_GP_IRQ_0_EN BIT(9) |
176 | #define M_GP_IRQ_1_EN BIT(10) |
177 | #define M_GP_IRQ_2_EN BIT(11) |
178 | #define M_GP_IRQ_3_EN BIT(12) |
179 | #define M_GP_IRQ_4_EN BIT(13) |
180 | #define M_GP_IRQ_5_EN BIT(14) |
181 | #define M_TX_FIFO_NOT_EMPTY_EN BIT(21) |
182 | #define M_IO_DATA_DEASSERT_EN BIT(22) |
183 | #define M_IO_DATA_ASSERT_EN BIT(23) |
184 | #define M_RX_FIFO_RD_ERR_EN BIT(24) |
185 | #define M_RX_FIFO_WR_ERR_EN BIT(25) |
186 | #define M_RX_FIFO_WATERMARK_EN BIT(26) |
187 | #define M_RX_FIFO_LAST_EN BIT(27) |
188 | #define M_TX_FIFO_RD_ERR_EN BIT(28) |
189 | #define M_TX_FIFO_WR_ERR_EN BIT(29) |
190 | #define M_TX_FIFO_WATERMARK_EN BIT(30) |
191 | #define M_SEC_IRQ_EN BIT(31) |
192 | #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ |
193 | M_IO_DATA_DEASSERT_EN | \ |
194 | M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ |
195 | M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ |
196 | M_TX_FIFO_WR_ERR_EN) |
197 | |
198 | /* GENI_S_IRQ_EN fields */ |
199 | #define S_CMD_DONE_EN BIT(0) |
200 | #define S_CMD_OVERRUN_EN BIT(1) |
201 | #define S_ILLEGAL_CMD_EN BIT(2) |
202 | #define S_CMD_FAILURE_EN BIT(3) |
203 | #define S_CMD_CANCEL_EN BIT(4) |
204 | #define S_CMD_ABORT_EN BIT(5) |
205 | #define S_GP_SYNC_IRQ_0_EN BIT(8) |
206 | #define S_GP_IRQ_0_EN BIT(9) |
207 | #define S_GP_IRQ_1_EN BIT(10) |
208 | #define S_GP_IRQ_2_EN BIT(11) |
209 | #define S_GP_IRQ_3_EN BIT(12) |
210 | #define S_GP_IRQ_4_EN BIT(13) |
211 | #define S_GP_IRQ_5_EN BIT(14) |
212 | #define S_IO_DATA_DEASSERT_EN BIT(22) |
213 | #define S_IO_DATA_ASSERT_EN BIT(23) |
214 | #define S_RX_FIFO_RD_ERR_EN BIT(24) |
215 | #define S_RX_FIFO_WR_ERR_EN BIT(25) |
216 | #define S_RX_FIFO_WATERMARK_EN BIT(26) |
217 | #define S_RX_FIFO_LAST_EN BIT(27) |
218 | #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ |
219 | S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) |
220 | |
221 | /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ |
222 | #define WATERMARK_MSK GENMASK(5, 0) |
223 | |
224 | /* GENI_TX_FIFO_STATUS fields */ |
225 | #define TX_FIFO_WC GENMASK(27, 0) |
226 | |
227 | /* GENI_RX_FIFO_STATUS fields */ |
228 | #define RX_LAST BIT(31) |
229 | #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) |
230 | #define RX_LAST_BYTE_VALID_SHFT 28 |
231 | #define RX_FIFO_WC_MSK GENMASK(24, 0) |
232 | |
233 | /* SE_GENI_IOS fields */ |
234 | #define IO2_DATA_IN BIT(1) |
235 | #define RX_DATA_IN BIT(0) |
236 | |
237 | /* SE_DMA_TX_IRQ_STAT Register fields */ |
238 | #define TX_DMA_DONE BIT(0) |
239 | #define TX_EOT BIT(1) |
240 | #define TX_SBE BIT(2) |
241 | #define TX_RESET_DONE BIT(3) |
242 | |
243 | /* SE_DMA_RX_IRQ_STAT Register fields */ |
244 | #define RX_DMA_DONE BIT(0) |
245 | #define RX_EOT BIT(1) |
246 | #define RX_SBE BIT(2) |
247 | #define RX_RESET_DONE BIT(3) |
248 | #define RX_FLUSH_DONE BIT(4) |
249 | #define RX_DMA_PARITY_ERR BIT(5) |
250 | #define RX_DMA_BREAK GENMASK(8, 7) |
251 | #define RX_GENI_GP_IRQ GENMASK(10, 5) |
252 | #define RX_GENI_CANCEL_IRQ BIT(11) |
253 | #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) |
254 | |
255 | /* SE_HW_PARAM_0 fields */ |
256 | #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) |
257 | #define TX_FIFO_WIDTH_SHFT 24 |
258 | /* |
259 | * For QUP HW Version >= 3.10 Tx fifo depth support is increased |
260 | * to 256bytes and corresponding bits are 16 to 23 |
261 | */ |
262 | #define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) |
263 | #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) |
264 | #define TX_FIFO_DEPTH_SHFT 16 |
265 | |
266 | /* SE_HW_PARAM_1 fields */ |
267 | #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) |
268 | #define RX_FIFO_WIDTH_SHFT 24 |
269 | /* |
270 | * For QUP HW Version >= 3.10 Rx fifo depth support is increased |
271 | * to 256bytes and corresponding bits are 16 to 23 |
272 | */ |
273 | #define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) |
274 | #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) |
275 | #define RX_FIFO_DEPTH_SHFT 16 |
276 | |
277 | #define HW_VER_MAJOR_MASK GENMASK(31, 28) |
278 | #define HW_VER_MAJOR_SHFT 28 |
279 | #define HW_VER_MINOR_MASK GENMASK(27, 16) |
280 | #define HW_VER_MINOR_SHFT 16 |
281 | #define HW_VER_STEP_MASK GENMASK(15, 0) |
282 | |
283 | #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) |
284 | #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) |
285 | #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) |
286 | |
287 | /* QUP SE VERSION value for major number 2 and minor number 5 */ |
288 | #define QUP_SE_VERSION_2_5 0x20050000 |
289 | |
290 | /* |
291 | * Define bandwidth thresholds that cause the underlying Core 2X interconnect |
292 | * clock to run at the named frequency. These baseline values are recommended |
293 | * by the hardware team, and are not dynamically scaled with GENI bandwidth |
294 | * beyond basic on/off. |
295 | */ |
296 | #define CORE_2X_19_2_MHZ 960 |
297 | #define CORE_2X_50_MHZ 2500 |
298 | #define CORE_2X_100_MHZ 5000 |
299 | #define CORE_2X_150_MHZ 7500 |
300 | #define CORE_2X_200_MHZ 10000 |
301 | #define CORE_2X_236_MHZ 16383 |
302 | |
303 | #define GENI_DEFAULT_BW Bps_to_icc(1000) |
304 | |
305 | #if IS_ENABLED(CONFIG_QCOM_GENI_SE) |
306 | |
307 | u32 geni_se_get_qup_hw_version(struct geni_se *se); |
308 | |
309 | /** |
310 | * geni_se_read_proto() - Read the protocol configured for a serial engine |
311 | * @se: Pointer to the concerned serial engine. |
312 | * |
313 | * Return: Protocol value as configured in the serial engine. |
314 | */ |
315 | static inline u32 geni_se_read_proto(struct geni_se *se) |
316 | { |
317 | u32 val; |
318 | |
319 | val = readl_relaxed(se->base + GENI_FW_REVISION_RO); |
320 | |
321 | return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; |
322 | } |
323 | |
324 | /** |
325 | * geni_se_setup_m_cmd() - Setup the primary sequencer |
326 | * @se: Pointer to the concerned serial engine. |
327 | * @cmd: Command/Operation to setup in the primary sequencer. |
328 | * @params: Parameter for the sequencer command. |
329 | * |
330 | * This function is used to configure the primary sequencer with the |
331 | * command and its associated parameters. |
332 | */ |
333 | static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) |
334 | { |
335 | u32 m_cmd; |
336 | |
337 | m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); |
338 | writel(val: m_cmd, addr: se->base + SE_GENI_M_CMD0); |
339 | } |
340 | |
341 | /** |
342 | * geni_se_setup_s_cmd() - Setup the secondary sequencer |
343 | * @se: Pointer to the concerned serial engine. |
344 | * @cmd: Command/Operation to setup in the secondary sequencer. |
345 | * @params: Parameter for the sequencer command. |
346 | * |
347 | * This function is used to configure the secondary sequencer with the |
348 | * command and its associated parameters. |
349 | */ |
350 | static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) |
351 | { |
352 | u32 s_cmd; |
353 | |
354 | s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); |
355 | s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); |
356 | s_cmd |= (cmd << S_OPCODE_SHFT); |
357 | s_cmd |= (params & S_PARAMS_MSK); |
358 | writel(val: s_cmd, addr: se->base + SE_GENI_S_CMD0); |
359 | } |
360 | |
361 | /** |
362 | * geni_se_cancel_m_cmd() - Cancel the command configured in the primary |
363 | * sequencer |
364 | * @se: Pointer to the concerned serial engine. |
365 | * |
366 | * This function is used to cancel the currently configured command in the |
367 | * primary sequencer. |
368 | */ |
369 | static inline void geni_se_cancel_m_cmd(struct geni_se *se) |
370 | { |
371 | writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); |
372 | } |
373 | |
374 | /** |
375 | * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary |
376 | * sequencer |
377 | * @se: Pointer to the concerned serial engine. |
378 | * |
379 | * This function is used to cancel the currently configured command in the |
380 | * secondary sequencer. |
381 | */ |
382 | static inline void geni_se_cancel_s_cmd(struct geni_se *se) |
383 | { |
384 | writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); |
385 | } |
386 | |
387 | /** |
388 | * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer |
389 | * @se: Pointer to the concerned serial engine. |
390 | * |
391 | * This function is used to force abort the currently configured command in the |
392 | * primary sequencer. |
393 | */ |
394 | static inline void geni_se_abort_m_cmd(struct geni_se *se) |
395 | { |
396 | writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); |
397 | } |
398 | |
399 | /** |
400 | * geni_se_abort_s_cmd() - Abort the command configured in the secondary |
401 | * sequencer |
402 | * @se: Pointer to the concerned serial engine. |
403 | * |
404 | * This function is used to force abort the currently configured command in the |
405 | * secondary sequencer. |
406 | */ |
407 | static inline void geni_se_abort_s_cmd(struct geni_se *se) |
408 | { |
409 | writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); |
410 | } |
411 | |
412 | /** |
413 | * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine |
414 | * based on QUP HW version |
415 | * @se: Pointer to the concerned serial engine. |
416 | * |
417 | * This function is used to get the depth i.e. number of elements in the |
418 | * TX fifo of the serial engine. |
419 | * |
420 | * Return: TX fifo depth in units of FIFO words. |
421 | */ |
422 | static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) |
423 | { |
424 | u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; |
425 | |
426 | hw_version = geni_se_get_qup_hw_version(se); |
427 | hw_major = GENI_SE_VERSION_MAJOR(hw_version); |
428 | hw_minor = GENI_SE_VERSION_MINOR(hw_version); |
429 | |
430 | if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) |
431 | tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; |
432 | else |
433 | tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; |
434 | |
435 | val = readl_relaxed(se->base + SE_HW_PARAM_0); |
436 | |
437 | return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; |
438 | } |
439 | |
440 | /** |
441 | * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine |
442 | * @se: Pointer to the concerned serial engine. |
443 | * |
444 | * This function is used to get the width i.e. word size per element in the |
445 | * TX fifo of the serial engine. |
446 | * |
447 | * Return: TX fifo width in bits |
448 | */ |
449 | static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) |
450 | { |
451 | u32 val; |
452 | |
453 | val = readl_relaxed(se->base + SE_HW_PARAM_0); |
454 | |
455 | return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; |
456 | } |
457 | |
458 | /** |
459 | * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine |
460 | * based on QUP HW version |
461 | * @se: Pointer to the concerned serial engine. |
462 | * |
463 | * This function is used to get the depth i.e. number of elements in the |
464 | * RX fifo of the serial engine. |
465 | * |
466 | * Return: RX fifo depth in units of FIFO words |
467 | */ |
468 | static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) |
469 | { |
470 | u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; |
471 | |
472 | hw_version = geni_se_get_qup_hw_version(se); |
473 | hw_major = GENI_SE_VERSION_MAJOR(hw_version); |
474 | hw_minor = GENI_SE_VERSION_MINOR(hw_version); |
475 | |
476 | if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) |
477 | rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; |
478 | else |
479 | rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; |
480 | |
481 | val = readl_relaxed(se->base + SE_HW_PARAM_1); |
482 | |
483 | return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; |
484 | } |
485 | |
486 | void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); |
487 | |
488 | void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); |
489 | |
490 | void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, |
491 | bool msb_to_lsb, bool tx_cfg, bool rx_cfg); |
492 | |
493 | int geni_se_resources_off(struct geni_se *se); |
494 | |
495 | int geni_se_resources_on(struct geni_se *se); |
496 | |
497 | int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); |
498 | |
499 | int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, |
500 | unsigned int *index, unsigned long *res_freq, |
501 | bool exact); |
502 | |
503 | void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); |
504 | |
505 | int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, |
506 | dma_addr_t *iova); |
507 | |
508 | void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); |
509 | |
510 | int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, |
511 | dma_addr_t *iova); |
512 | |
513 | void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); |
514 | |
515 | void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); |
516 | |
517 | int geni_icc_get(struct geni_se *se, const char *icc_ddr); |
518 | |
519 | int geni_icc_set_bw(struct geni_se *se); |
520 | void geni_icc_set_tag(struct geni_se *se, u32 tag); |
521 | |
522 | int geni_icc_enable(struct geni_se *se); |
523 | |
524 | int geni_icc_disable(struct geni_se *se); |
525 | #endif |
526 | #endif |
527 | |