| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. |
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| 4 | * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __WCD939X_H__ |
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| 8 | #define __WCD939X_H__ |
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| 9 | #include <linux/soundwire/sdw.h> |
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| 10 | #include <linux/soundwire/sdw_type.h> |
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| 11 | |
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| 12 | #define WCD939X_BASE (0x3000) |
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| 13 | #define WCD939X_ANA_PAGE (0x3000) |
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| 14 | #define WCD939X_ANA_BIAS (0x3001) |
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| 15 | #define WCD939X_BIAS_ANALOG_BIAS_EN BIT(7) |
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| 16 | #define WCD939X_BIAS_PRECHRG_EN BIT(6) |
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| 17 | #define WCD939X_BIAS_PRECHRG_CTL_MODE BIT(5) |
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| 18 | #define WCD939X_ANA_RX_SUPPLIES (0x3008) |
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| 19 | #define WCD939X_RX_SUPPLIES_VPOS_EN BIT(7) |
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| 20 | #define WCD939X_RX_SUPPLIES_VNEG_EN BIT(6) |
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| 21 | #define WCD939X_RX_SUPPLIES_VPOS_PWR_LVL BIT(3) |
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| 22 | #define WCD939X_RX_SUPPLIES_VNEG_PWR_LVL BIT(2) |
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| 23 | #define WCD939X_RX_SUPPLIES_REGULATOR_MODE BIT(1) |
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| 24 | #define WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE BIT(0) |
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| 25 | #define WCD939X_ANA_HPH (0x3009) |
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| 26 | #define WCD939X_HPH_HPHL_ENABLE BIT(7) |
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| 27 | #define WCD939X_HPH_HPHR_ENABLE BIT(6) |
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| 28 | #define WCD939X_HPH_HPHL_REF_ENABLE BIT(5) |
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| 29 | #define WCD939X_HPH_HPHR_REF_ENABLE BIT(4) |
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| 30 | #define WCD939X_HPH_PWR_LEVEL GENMASK(3, 2) |
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| 31 | #define WCD939X_ANA_EAR (0x300a) |
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| 32 | #define WCD939X_ANA_EAR_COMPANDER_CTL (0x300b) |
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| 33 | #define WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG BIT(7) |
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| 34 | #define WCD939X_EAR_COMPANDER_CTL_EAR_GAIN GENMASK(6, 2) |
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| 35 | #define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_BYP BIT(1) |
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| 36 | #define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_CLK_EDGE BIT(0) |
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| 37 | #define WCD939X_ANA_TX_CH1 (0x300e) |
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| 38 | #define WCD939X_ANA_TX_CH2 (0x300f) |
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| 39 | #define WCD939X_TX_CH2_ENABLE BIT(7) |
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| 40 | #define WCD939X_TX_CH2_HPF1_INIT BIT(6) |
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| 41 | #define WCD939X_TX_CH2_HPF2_INIT BIT(5) |
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| 42 | #define WCD939X_TX_CH2_GAIN GENMASK(4, 0) |
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| 43 | #define WCD939X_ANA_TX_CH3 (0x3010) |
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| 44 | #define WCD939X_ANA_TX_CH4 (0x3011) |
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| 45 | #define WCD939X_TX_CH4_ENABLE BIT(7) |
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| 46 | #define WCD939X_TX_CH4_HPF3_INIT BIT(6) |
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| 47 | #define WCD939X_TX_CH4_HPF4_INIT BIT(5) |
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| 48 | #define WCD939X_TX_CH4_GAIN GENMASK(4, 0) |
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| 49 | #define WCD939X_ANA_MICB1_MICB2_DSP_EN_LOGIC (0x3012) |
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| 50 | #define WCD939X_ANA_MICB3_DSP_EN_LOGIC (0x3013) |
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| 51 | #define WCD939X_ANA_MBHC_MECH (0x3014) |
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| 52 | #define WCD939X_MBHC_MECH_L_DET_EN BIT(7) |
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| 53 | #define WCD939X_MBHC_MECH_GND_DET_EN BIT(6) |
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| 54 | #define WCD939X_MBHC_MECH_MECH_DETECT_TYPE BIT(5) |
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| 55 | #define WCD939X_MBHC_MECH_HPHL_PLUG_TYPE BIT(4) |
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| 56 | #define WCD939X_MBHC_MECH_GND_PLUG_TYPE BIT(3) |
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| 57 | #define WCD939X_MBHC_MECH_MECH_HS_L_PULLUP_COMP_EN BIT(2) |
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| 58 | #define WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN BIT(1) |
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| 59 | #define WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND BIT(0) |
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| 60 | #define WCD939X_ANA_MBHC_ELECT (0x3015) |
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| 61 | #define WCD939X_MBHC_ELECT_FSM_EN BIT(7) |
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| 62 | #define WCD939X_MBHC_ELECT_BTNDET_ISRC_CTL GENMASK(6, 4) |
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| 63 | #define WCD939X_MBHC_ELECT_ELECT_DET_TYPE BIT(3) |
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| 64 | #define WCD939X_MBHC_ELECT_ELECT_SCHMT_ISRC_CTL GENMASK(2, 1) |
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| 65 | #define WCD939X_MBHC_ELECT_BIAS_EN BIT(0) |
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| 66 | #define WCD939X_ANA_MBHC_ZDET (0x3016) |
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| 67 | #define WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN BIT(7) |
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| 68 | #define WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN BIT(6) |
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| 69 | #define WCD939X_MBHC_ZDET_ZDET_CHG_EN BIT(5) |
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| 70 | #define WCD939X_MBHC_ZDET_ZDET_ILEAK_COMP_EN BIT(4) |
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| 71 | #define WCD939X_MBHC_ZDET_ELECT_ISRC_EN BIT(1) |
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| 72 | #define WCD939X_ANA_MBHC_RESULT_1 (0x3017) |
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| 73 | #define WCD939X_MBHC_RESULT_1_Z_RESULT_LSB GENMASK(7, 0) |
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| 74 | #define WCD939X_ANA_MBHC_RESULT_2 (0x3018) |
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| 75 | #define WCD939X_MBHC_RESULT_2_Z_RESULT_MSB GENMASK(7, 0) |
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| 76 | #define WCD939X_ANA_MBHC_RESULT_3 (0x3019) |
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| 77 | #define WCD939X_ANA_MBHC_BTN0 (0x301a) |
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| 78 | #define WCD939X_MBHC_BTN0_VTH GENMASK(7, 2) |
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| 79 | #define WCD939X_ANA_MBHC_BTN1 (0x301b) |
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| 80 | #define WCD939X_MBHC_BTN1_VTH GENMASK(7, 2) |
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| 81 | #define WCD939X_ANA_MBHC_BTN2 (0x301c) |
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| 82 | #define WCD939X_MBHC_BTN2_VTH GENMASK(7, 2) |
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| 83 | #define WCD939X_ANA_MBHC_BTN3 (0x301d) |
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| 84 | #define WCD939X_MBHC_BTN3_VTH GENMASK(7, 2) |
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| 85 | #define WCD939X_ANA_MBHC_BTN4 (0x301e) |
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| 86 | #define WCD939X_MBHC_BTN4_VTH GENMASK(7, 2) |
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| 87 | #define WCD939X_ANA_MBHC_BTN5 (0x301f) |
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| 88 | #define WCD939X_MBHC_BTN5_VTH GENMASK(7, 2) |
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| 89 | #define WCD939X_ANA_MBHC_BTN6 (0x3020) |
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| 90 | #define WCD939X_MBHC_BTN6_VTH GENMASK(7, 2) |
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| 91 | #define WCD939X_ANA_MBHC_BTN7 (0x3021) |
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| 92 | #define WCD939X_MBHC_BTN7_VTH GENMASK(7, 2) |
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| 93 | #define WCD939X_ANA_MICB1 (0x3022) |
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| 94 | #define WCD939X_MICB1_ENABLE GENMASK(7, 6) |
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| 95 | #define WCD939X_MICB1_VOUT_CTL GENMASK(5, 0) |
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| 96 | #define WCD939X_ANA_MICB2 (0x3023) |
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| 97 | #define WCD939X_MICB2_ENABLE GENMASK(7, 6) |
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| 98 | #define WCD939X_MICB2_VOUT_CTL GENMASK(5, 0) |
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| 99 | #define WCD939X_ANA_MICB2_RAMP (0x3024) |
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| 100 | #define WCD939X_MICB2_RAMP_RAMP_ENABLE BIT(7) |
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| 101 | #define WCD939X_MICB2_RAMP_MB2_IN2P_SHORT_ENABLE BIT(6) |
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| 102 | #define WCD939X_MICB2_RAMP_ALLSW_OVRD_ENABLE BIT(5) |
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| 103 | #define WCD939X_MICB2_RAMP_SHIFT_CTL GENMASK(4, 2) |
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| 104 | #define WCD939X_MICB2_RAMP_USB_MGDET_MICB2_RAMP GENMASK(1, 0) |
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| 105 | #define WCD939X_ANA_MICB3 (0x3025) |
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| 106 | #define WCD939X_MICB3_ENABLE GENMASK(7, 6) |
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| 107 | #define WCD939X_MICB3_VOUT_CTL GENMASK(5, 0) |
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| 108 | #define WCD939X_ANA_MICB4 (0x3026) |
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| 109 | #define WCD939X_MICB4_ENABLE GENMASK(7, 6) |
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| 110 | #define WCD939X_MICB4_VOUT_CTL GENMASK(5, 0) |
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| 111 | #define WCD939X_BIAS_CTL (0x3028) |
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| 112 | #define WCD939X_BIAS_VBG_FINE_ADJ (0x3029) |
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| 113 | #define WCD939X_LDOL_VDDCX_ADJUST (0x3040) |
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| 114 | #define WCD939X_LDOL_DISABLE_LDOL (0x3041) |
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| 115 | #define WCD939X_MBHC_CTL_CLK (0x3056) |
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| 116 | #define WCD939X_MBHC_CTL_ANA (0x3057) |
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| 117 | #define WCD939X_MBHC_ZDET_VNEG_CTL (0x3058) |
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| 118 | #define WCD939X_MBHC_ZDET_BIAS_CTL (0x3059) |
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| 119 | #define WCD939X_MBHC_CTL_BCS (0x305a) |
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| 120 | #define WCD939X_MBHC_MOISTURE_DET_FSM_STATUS (0x305b) |
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| 121 | #define WCD939X_MBHC_TEST_CTL (0x305c) |
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| 122 | #define WCD939X_LDOH_MODE (0x3067) |
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| 123 | #define WCD939X_MODE_LDOH_EN BIT(7) |
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| 124 | #define WCD939X_MODE_PWRDN_STATE BIT(6) |
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| 125 | #define WCD939X_MODE_SLOWRAMP_EN BIT(5) |
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| 126 | #define WCD939X_MODE_VOUT_ADJUST GENMASK(4, 3) |
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| 127 | #define WCD939X_MODE_VOUT_COARSE_ADJ GENMASK(2, 0) |
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| 128 | #define WCD939X_LDOH_BIAS (0x3068) |
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| 129 | #define WCD939X_LDOH_STB_LOADS (0x3069) |
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| 130 | #define WCD939X_LDOH_SLOWRAMP (0x306a) |
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| 131 | #define WCD939X_MICB1_TEST_CTL_1 (0x306b) |
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| 132 | #define WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL GENMASK(7, 5) |
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| 133 | #define WCD939X_TEST_CTL_1_EN_VREFGEN BIT(4) |
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| 134 | #define WCD939X_TEST_CTL_1_EN_LDO BIT(3) |
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| 135 | #define WCD939X_TEST_CTL_1_LDO_BLEEDER_I_CTRL GENMASK(2, 0) |
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| 136 | #define WCD939X_MICB1_TEST_CTL_2 (0x306c) |
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| 137 | #define WCD939X_TEST_CTL_2_IBIAS_VREFGEN GENMASK(7, 6) |
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| 138 | #define WCD939X_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS BIT(5) |
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| 139 | #define WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER GENMASK(2, 0) |
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| 140 | #define WCD939X_MICB1_TEST_CTL_3 (0x306d) |
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| 141 | #define WCD939X_TEST_CTL_3_CFILT_REF_EN BIT(7) |
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| 142 | #define WCD939X_TEST_CTL_3_RZ_LDO_VAL GENMASK(6, 4) |
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| 143 | #define WCD939X_TEST_CTL_3_IBIAS_LDO_STG3 GENMASK(3, 2) |
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| 144 | #define WCD939X_TEST_CTL_3_ATEST_CTRL GENMASK(1, 0) |
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| 145 | #define WCD939X_MICB2_TEST_CTL_1 (0x306e) |
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| 146 | #define WCD939X_MICB2_TEST_CTL_2 (0x306f) |
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| 147 | #define WCD939X_MICB2_TEST_CTL_3 (0x3070) |
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| 148 | #define WCD939X_MICB3_TEST_CTL_1 (0x3071) |
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| 149 | #define WCD939X_MICB3_TEST_CTL_2 (0x3072) |
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| 150 | #define WCD939X_MICB3_TEST_CTL_3 (0x3073) |
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| 151 | #define WCD939X_MICB4_TEST_CTL_1 (0x3074) |
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| 152 | #define WCD939X_MICB4_TEST_CTL_2 (0x3075) |
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| 153 | #define WCD939X_MICB4_TEST_CTL_3 (0x3076) |
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| 154 | #define WCD939X_TX_COM_ADC_VCM (0x3077) |
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| 155 | #define WCD939X_TX_COM_BIAS_ATEST (0x3078) |
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| 156 | #define WCD939X_TX_COM_SPARE1 (0x3079) |
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| 157 | #define WCD939X_TX_COM_SPARE2 (0x307a) |
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| 158 | #define WCD939X_TX_COM_TXFE_DIV_CTL (0x307b) |
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| 159 | #define WCD939X_TX_COM_TXFE_DIV_START (0x307c) |
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| 160 | #define WCD939X_TX_COM_SPARE3 (0x307d) |
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| 161 | #define WCD939X_TX_COM_SPARE4 (0x307e) |
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| 162 | #define WCD939X_TX_1_2_TEST_EN (0x307f) |
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| 163 | #define WCD939X_TX_1_2_ADC_IB (0x3080) |
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| 164 | #define WCD939X_TX_1_2_ATEST_REFCTL (0x3081) |
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| 165 | #define WCD939X_TX_1_2_TEST_CTL (0x3082) |
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| 166 | #define WCD939X_TX_1_2_TEST_BLK_EN1 (0x3083) |
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| 167 | #define WCD939X_TX_1_2_TXFE1_CLKDIV (0x3084) |
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| 168 | #define WCD939X_TX_1_2_SAR2_ERR (0x3085) |
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| 169 | #define WCD939X_TX_1_2_SAR1_ERR (0x3086) |
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| 170 | #define WCD939X_TX_3_4_TEST_EN (0x3087) |
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| 171 | #define WCD939X_TX_3_4_ADC_IB (0x3088) |
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| 172 | #define WCD939X_TX_3_4_ATEST_REFCTL (0x3089) |
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| 173 | #define WCD939X_TX_3_4_TEST_CTL (0x308a) |
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| 174 | #define WCD939X_TX_3_4_TEST_BLK_EN3 (0x308b) |
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| 175 | #define WCD939X_TX_3_4_TXFE3_CLKDIV (0x308c) |
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| 176 | #define WCD939X_TX_3_4_SAR4_ERR (0x308d) |
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| 177 | #define WCD939X_TX_3_4_SAR3_ERR (0x308e) |
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| 178 | #define WCD939X_TX_3_4_TEST_BLK_EN2 (0x308f) |
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| 179 | #define WCD939X_TEST_BLK_EN2_ADC2_INT1_EN BIT(7) |
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| 180 | #define WCD939X_TEST_BLK_EN2_ADC2_INT2_EN BIT(6) |
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| 181 | #define WCD939X_TEST_BLK_EN2_ADC2_SAR_EN BIT(5) |
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| 182 | #define WCD939X_TEST_BLK_EN2_ADC2_CMGEN_EN BIT(4) |
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| 183 | #define WCD939X_TEST_BLK_EN2_ADC2_CLKGEN_EN BIT(3) |
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| 184 | #define WCD939X_TEST_BLK_EN2_ADC12_VREF_NONL2 GENMASK(2, 1) |
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| 185 | #define WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN BIT(0) |
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| 186 | #define WCD939X_TX_3_4_TXFE2_CLKDIV (0x3090) |
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| 187 | #define WCD939X_TX_3_4_SPARE1 (0x3091) |
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| 188 | #define WCD939X_TX_3_4_TEST_BLK_EN4 (0x3092) |
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| 189 | #define WCD939X_TX_3_4_TXFE4_CLKDIV (0x3093) |
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| 190 | #define WCD939X_TX_3_4_SPARE2 (0x3094) |
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| 191 | #define WCD939X_CLASSH_MODE_1 (0x3097) |
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| 192 | #define WCD939X_CLASSH_MODE_2 (0x3098) |
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| 193 | #define WCD939X_CLASSH_MODE_3 (0x3099) |
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| 194 | #define WCD939X_CLASSH_CTRL_VCL_1 (0x309a) |
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| 195 | #define WCD939X_CLASSH_CTRL_VCL_2 (0x309b) |
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| 196 | #define WCD939X_CLASSH_CTRL_CCL_1 (0x309c) |
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| 197 | #define WCD939X_CLASSH_CTRL_CCL_2 (0x309d) |
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| 198 | #define WCD939X_CLASSH_CTRL_CCL_3 (0x309e) |
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| 199 | #define WCD939X_CLASSH_CTRL_CCL_4 (0x309f) |
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| 200 | #define WCD939X_CLASSH_CTRL_CCL_5 (0x30a0) |
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| 201 | #define WCD939X_CLASSH_BUCK_TMUX_A_D (0x30a1) |
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| 202 | #define WCD939X_CLASSH_BUCK_SW_DRV_CNTL (0x30a2) |
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| 203 | #define WCD939X_CLASSH_SPARE (0x30a3) |
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| 204 | #define WCD939X_FLYBACK_EN (0x30a4) |
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| 205 | #define WCD939X_FLYBACK_VNEG_CTRL_1 (0x30a5) |
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| 206 | #define WCD939X_FLYBACK_VNEG_CTRL_2 (0x30a6) |
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| 207 | #define WCD939X_FLYBACK_VNEG_CTRL_3 (0x30a7) |
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| 208 | #define WCD939X_FLYBACK_VNEG_CTRL_4 (0x30a8) |
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| 209 | #define WCD939X_VNEG_CTRL_4_ILIM_SEL GENMASK(7, 4) |
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| 210 | #define WCD939X_VNEG_CTRL_4_PW_BUF_POS GENMASK(3, 2) |
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| 211 | #define WCD939X_VNEG_CTRL_4_PW_BUF_NEG GENMASK(1, 0) |
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| 212 | #define WCD939X_FLYBACK_VNEG_CTRL_5 (0x30a9) |
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| 213 | #define WCD939X_FLYBACK_VNEG_CTRL_6 (0x30aa) |
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| 214 | #define WCD939X_FLYBACK_VNEG_CTRL_7 (0x30ab) |
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| 215 | #define WCD939X_FLYBACK_VNEG_CTRL_8 (0x30ac) |
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| 216 | #define WCD939X_FLYBACK_VNEG_CTRL_9 (0x30ad) |
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| 217 | #define WCD939X_FLYBACK_VNEGDAC_CTRL_1 (0x30ae) |
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| 218 | #define WCD939X_FLYBACK_VNEGDAC_CTRL_2 (0x30af) |
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| 219 | #define WCD939X_FLYBACK_VNEGDAC_CTRL_3 (0x30b0) |
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| 220 | #define WCD939X_FLYBACK_CTRL_1 (0x30b1) |
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| 221 | #define WCD939X_FLYBACK_TEST_CTL (0x30b2) |
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| 222 | #define WCD939X_RX_AUX_SW_CTL (0x30b3) |
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| 223 | #define WCD939X_RX_PA_AUX_IN_CONN (0x30b4) |
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| 224 | #define WCD939X_RX_TIMER_DIV (0x30b5) |
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| 225 | #define WCD939X_RX_OCP_CTL (0x30b6) |
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| 226 | #define WCD939X_RX_OCP_COUNT (0x30b7) |
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| 227 | #define WCD939X_RX_BIAS_EAR_DAC (0x30b8) |
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| 228 | #define WCD939X_RX_BIAS_EAR_AMP (0x30b9) |
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| 229 | #define WCD939X_RX_BIAS_HPH_LDO (0x30ba) |
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| 230 | #define WCD939X_RX_BIAS_HPH_PA (0x30bb) |
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| 231 | #define WCD939X_RX_BIAS_HPH_RDACBUFF_CNP2 (0x30bc) |
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| 232 | #define WCD939X_RX_BIAS_HPH_RDAC_LDO (0x30bd) |
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| 233 | #define WCD939X_RX_BIAS_HPH_CNP1 (0x30be) |
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| 234 | #define WCD939X_RX_BIAS_HPH_LOWPOWER (0x30bf) |
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| 235 | #define WCD939X_RX_BIAS_AUX_DAC (0x30c0) |
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| 236 | #define WCD939X_RX_BIAS_AUX_AMP (0x30c1) |
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| 237 | #define WCD939X_RX_BIAS_VNEGDAC_BLEEDER (0x30c2) |
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| 238 | #define WCD939X_RX_BIAS_MISC (0x30c3) |
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| 239 | #define WCD939X_RX_BIAS_BUCK_RST (0x30c4) |
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| 240 | #define WCD939X_RX_BIAS_BUCK_VREF_ERRAMP (0x30c5) |
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| 241 | #define WCD939X_RX_BIAS_FLYB_ERRAMP (0x30c6) |
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| 242 | #define WCD939X_RX_BIAS_FLYB_BUFF (0x30c7) |
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| 243 | #define WCD939X_RX_BIAS_FLYB_MID_RST (0x30c8) |
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| 244 | #define WCD939X_HPH_L_STATUS (0x30c9) |
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| 245 | #define WCD939X_HPH_R_STATUS (0x30ca) |
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| 246 | #define WCD939X_HPH_CNP_EN (0x30cb) |
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| 247 | #define WCD939X_HPH_CNP_WG_CTL (0x30cc) |
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| 248 | #define WCD939X_HPH_CNP_WG_TIME (0x30cd) |
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| 249 | #define WCD939X_HPH_OCP_CTL (0x30ce) |
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| 250 | #define WCD939X_OCP_CTL_OCP_CURR_LIMIT GENMASK(7, 5) |
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| 251 | #define WCD939X_OCP_CTL_OCP_FSM_EN BIT(4) |
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| 252 | #define WCD939X_OCP_CTL_SPARE_BITS BIT(3) |
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| 253 | #define WCD939X_OCP_CTL_SCD_OP_EN BIT(1) |
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| 254 | #define WCD939X_HPH_AUTO_CHOP (0x30cf) |
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| 255 | #define WCD939X_HPH_CHOP_CTL (0x30d0) |
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| 256 | #define WCD939X_HPH_PA_CTL1 (0x30d1) |
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| 257 | #define WCD939X_HPH_PA_CTL2 (0x30d2) |
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| 258 | #define WCD939X_PA_CTL2_HPHPA_GND_R BIT(6) |
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| 259 | #define WCD939X_PA_CTL2_HPHPA_GND_L BIT(4) |
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| 260 | #define WCD939X_PA_CTL2_GM3_CASCODE_CTL_NORMAL GENMASK(1, 0) |
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| 261 | #define WCD939X_HPH_L_EN (0x30d3) |
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| 262 | #define WCD939X_L_EN_CONST_SEL_L GENMASK(7, 6) |
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| 263 | #define WCD939X_L_EN_GAIN_SOURCE_SEL BIT(5) |
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| 264 | #define WCD939X_L_EN_SPARE_BITS GENMASK(4, 0) |
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| 265 | #define WCD939X_HPH_L_TEST (0x30d4) |
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| 266 | #define WCD939X_HPH_L_ATEST (0x30d5) |
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| 267 | #define WCD939X_HPH_R_EN (0x30d6) |
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| 268 | #define WCD939X_R_EN_CONST_SEL_R GENMASK(7, 6) |
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| 269 | #define WCD939X_R_EN_GAIN_SOURCE_SEL BIT(5) |
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| 270 | #define WCD939X_R_EN_SPARE_BITS GENMASK(4, 0) |
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| 271 | #define WCD939X_HPH_R_TEST (0x30d7) |
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| 272 | #define WCD939X_HPH_R_ATEST (0x30d8) |
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| 273 | #define WCD939X_R_ATEST_DACR_REF_ATEST1_CONN BIT(7) |
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| 274 | #define WCD939X_R_ATEST_LDO1_R_ATEST2_CONN BIT(6) |
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| 275 | #define WCD939X_R_ATEST_LDO_R_ATEST2_CAL BIT(5) |
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| 276 | #define WCD939X_R_ATEST_LDO2_R_ATEST2_CONN BIT(4) |
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| 277 | #define WCD939X_R_ATEST_LDO_1P65V_ATEST1_CONN BIT(3) |
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| 278 | #define WCD939X_R_ATEST_HPH_GND_OVR BIT(1) |
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| 279 | #define WCD939X_HPH_RDAC_CLK_CTL1 (0x30d9) |
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| 280 | #define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN BIT(7) |
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| 281 | #define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL GENMASK(6, 4) |
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| 282 | #define WCD939X_RDAC_CLK_CTL1_SPARE_BITS GENMASK(3, 0) |
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| 283 | #define WCD939X_HPH_RDAC_CLK_CTL2 (0x30da) |
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| 284 | #define WCD939X_HPH_RDAC_LDO_CTL (0x30db) |
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| 285 | #define WCD939X_HPH_RDAC_CHOP_CLK_LP_CTL (0x30dc) |
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| 286 | #define WCD939X_HPH_REFBUFF_UHQA_CTL (0x30dd) |
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| 287 | #define WCD939X_REFBUFF_UHQA_CTL_SPARE_BITS GENMASK(7, 6) |
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| 288 | #define WCD939X_REFBUFF_UHQA_CTL_HPH_VNEGREG2_COMP_CTL_OV BIT(5) |
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| 289 | #define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_RBIAS_ADJUST BIT(4) |
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| 290 | #define WCD939X_REFBUFF_UHQA_CTL_REFBUFP_IOUT_CTL GENMASK(3, 2) |
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| 291 | #define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_IOUT_CTL GENMASK(1, 0) |
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| 292 | #define WCD939X_HPH_REFBUFF_LP_CTL (0x30de) |
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| 293 | #define WCD939X_REFBUFF_LP_CTL_HPH_VNEGREG2_CURR_COMP GENMASK(7, 6) |
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| 294 | #define WCD939X_REFBUFF_LP_CTL_SPARE_BITS GENMASK(5, 4) |
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| 295 | #define WCD939X_REFBUFF_LP_CTL_EN_PREREF_FILT_STARTUP_CLKDIV BIT(3) |
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| 296 | #define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_STARTUP_CLKDIV_CTL GENMASK(2, 1) |
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| 297 | #define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS BIT(0) |
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| 298 | #define WCD939X_HPH_L_DAC_CTL (0x30df) |
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| 299 | #define WCD939X_HPH_R_DAC_CTL (0x30e0) |
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| 300 | #define WCD939X_HPH_SURGE_COMP_SEL (0x30e1) |
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| 301 | #define WCD939X_HPH_SURGE_EN (0x30e2) |
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| 302 | #define WCD939X_EN_EN_SURGE_PROTECTION_HPHL BIT(7) |
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| 303 | #define WCD939X_EN_EN_SURGE_PROTECTION_HPHR BIT(6) |
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| 304 | #define WCD939X_EN_SEL_SURGE_COMP_IQ GENMASK(5, 4) |
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| 305 | #define WCD939X_EN_SURGE_VOLT_MODE_SHUTOFF_EN BIT(3) |
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| 306 | #define WCD939X_EN_LATCH_INTR_OP_STG_HIZ_EN BIT(2) |
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| 307 | #define WCD939X_EN_SURGE_LATCH_REG_RESET BIT(1) |
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| 308 | #define WCD939X_EN_SWTICH_VN_VNDAC_NSURGE_EN BIT(0) |
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| 309 | #define WCD939X_HPH_SURGE_MISC1 (0x30e3) |
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| 310 | #define WCD939X_HPH_SURGE_STATUS (0x30e4) |
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| 311 | #define WCD939X_EAR_EN (0x30e9) |
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| 312 | #define WCD939X_EAR_PA_CON (0x30ea) |
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| 313 | #define WCD939X_EAR_SP_CON (0x30eb) |
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| 314 | #define WCD939X_EAR_DAC_CON (0x30ec) |
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| 315 | #define WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL BIT(7) |
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| 316 | #define WCD939X_DAC_CON_REF_DBG_EN BIT(6) |
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| 317 | #define WCD939X_DAC_CON_REF_DBG_GAIN GENMASK(5, 3) |
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| 318 | #define WCD939X_DAC_CON_GAIN_DAC GENMASK(2, 1) |
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| 319 | #define WCD939X_DAC_CON_INV_DATA BIT(0) |
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| 320 | #define WCD939X_EAR_CNP_FSM_CON (0x30ed) |
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| 321 | #define WCD939X_EAR_TEST_CTL (0x30ee) |
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| 322 | #define WCD939X_EAR_STATUS_REG_1 (0x30ef) |
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| 323 | #define WCD939X_EAR_STATUS_REG_2 (0x30f0) |
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| 324 | #define WCD939X_FLYBACK_NEW_CTRL_2 (0x30f6) |
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| 325 | #define WCD939X_FLYBACK_NEW_CTRL_3 (0x30f7) |
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| 326 | #define WCD939X_FLYBACK_NEW_CTRL_4 (0x30f8) |
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| 327 | #define WCD939X_ANA_NEW_PAGE (0x3100) |
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| 328 | #define WCD939X_HPH_NEW_ANA_HPH2 (0x3101) |
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| 329 | #define WCD939X_HPH_NEW_ANA_HPH3 (0x3102) |
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| 330 | #define WCD939X_SLEEP_CTL (0x3103) |
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| 331 | #define WCD939X_SLEEP_WATCHDOG_CTL (0x3104) |
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| 332 | #define WCD939X_MBHC_NEW_ELECT_REM_CLAMP_CTL (0x311f) |
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| 333 | #define WCD939X_MBHC_NEW_CTL_1 (0x3120) |
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| 334 | #define WCD939X_CTL_1_RCO_EN BIT(7) |
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| 335 | #define WCD939X_CTL_1_ADC_MODE BIT(4) |
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| 336 | #define WCD939X_CTL_1_ADC_ENABLE BIT(3) |
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| 337 | #define WCD939X_CTL_1_DETECTION_DONE BIT(2) |
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| 338 | #define WCD939X_CTL_1_BTN_DBNC_CTL GENMASK(1, 0) |
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| 339 | #define WCD939X_MBHC_NEW_CTL_2 (0x3121) |
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| 340 | #define WCD939X_CTL_2_MUX_CTL GENMASK(6, 4) |
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| 341 | #define WCD939X_CTL_2_M_RTH_CTL GENMASK(3, 2) |
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| 342 | #define WCD939X_CTL_2_HS_VREF_CTL GENMASK(1, 0) |
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| 343 | #define WCD939X_MBHC_NEW_PLUG_DETECT_CTL (0x3122) |
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| 344 | #define WCD939X_MBHC_NEW_ZDET_ANA_CTL (0x3123) |
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| 345 | #define WCD939X_ZDET_ANA_CTL_AVERAGING_EN BIT(7) |
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| 346 | #define WCD939X_ZDET_ANA_CTL_MAXV_CTL GENMASK(6, 4) |
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| 347 | #define WCD939X_ZDET_ANA_CTL_RANGE_CTL GENMASK(3, 0) |
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| 348 | #define WCD939X_MBHC_NEW_ZDET_RAMP_CTL (0x3124) |
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| 349 | #define WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL GENMASK(6, 4) |
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| 350 | #define WCD939X_ZDET_RAMP_CTL_TIME_CTL GENMASK(3, 0) |
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| 351 | #define WCD939X_MBHC_NEW_FSM_STATUS (0x3125) |
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| 352 | #define WCD939X_FSM_STATUS_ADC_TIMEOUT BIT(7) |
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| 353 | #define WCD939X_FSM_STATUS_ADC_COMPLETE BIT(6) |
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| 354 | #define WCD939X_FSM_STATUS_HS_M_COMP_STATUS BIT(5) |
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| 355 | #define WCD939X_FSM_STATUS_FAST_PRESS_FLAG_STATUS BIT(4) |
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| 356 | #define WCD939X_FSM_STATUS_FAST_REMOVAL_FLAG_STATUS BIT(3) |
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| 357 | #define WCD939X_FSM_STATUS_REMOVAL_FLAG_STATUS BIT(2) |
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| 358 | #define WCD939X_FSM_STATUS_ELECT_REM_RT_STATUS BIT(1) |
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| 359 | #define WCD939X_FSM_STATUS_BTN_STATUS BIT(0) |
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| 360 | #define WCD939X_MBHC_NEW_ADC_RESULT (0x3126) |
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| 361 | #define WCD939X_ADC_RESULT_VALUE GENMASK(7, 0) |
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| 362 | #define WCD939X_TX_NEW_CH12_MUX (0x3127) |
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| 363 | #define WCD939X_TX_NEW_CH34_MUX (0x3128) |
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| 364 | #define WCD939X_DIE_CRACK_DET_EN (0x312c) |
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| 365 | #define WCD939X_DIE_CRACK_DET_OUT (0x312d) |
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| 366 | #define WCD939X_HPH_NEW_INT_RDAC_GAIN_CTL (0x3132) |
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| 367 | #define WCD939X_HPH_NEW_INT_PA_GAIN_CTL_L (0x3133) |
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| 368 | #define WCD939X_PA_GAIN_CTL_L_EN_HPHPA_2VPK BIT(7) |
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| 369 | #define WCD939X_PA_GAIN_CTL_L_RX_SUPPLY_LEVEL BIT(6) |
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| 370 | #define WCD939X_PA_GAIN_CTL_L_DAC_DR_BOOST BIT(5) |
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| 371 | #define WCD939X_PA_GAIN_CTL_L_VALUE GENMASK(4, 0) |
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| 372 | #define WCD939X_HPH_NEW_INT_RDAC_VREF_CTL (0x3134) |
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| 373 | #define WCD939X_HPH_NEW_INT_RDAC_OVERRIDE_CTL (0x3135) |
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| 374 | #define WCD939X_HPH_NEW_INT_PA_GAIN_CTL_R (0x3136) |
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| 375 | #define WCD939X_PA_GAIN_CTL_R_D_RCO_CLK_EN BIT(7) |
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| 376 | #define WCD939X_PA_GAIN_CTL_R_SPARE_BITS GENMASK(6, 5) |
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| 377 | #define WCD939X_PA_GAIN_CTL_R_VALUE GENMASK(4, 0) |
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| 378 | #define WCD939X_HPH_NEW_INT_PA_MISC1 (0x3137) |
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| 379 | #define WCD939X_HPH_NEW_INT_PA_MISC2 (0x3138) |
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| 380 | #define WCD939X_HPH_NEW_INT_PA_RDAC_MISC (0x3139) |
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| 381 | #define WCD939X_HPH_NEW_INT_TIMER1 (0x313a) |
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| 382 | #define WCD939X_TIMER1_CURR_IDIV_CTL_CMPDR_OFF GENMASK(7, 5) |
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| 383 | #define WCD939X_TIMER1_CURR_IDIV_CTL_AUTOCHOP GENMASK(4, 2) |
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| 384 | #define WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN BIT(1) |
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| 385 | #define WCD939X_HPH_NEW_INT_TIMER2 (0x313b) |
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| 386 | #define WCD939X_HPH_NEW_INT_TIMER3 (0x313c) |
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| 387 | #define WCD939X_HPH_NEW_INT_TIMER4 (0x313d) |
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| 388 | #define WCD939X_HPH_NEW_INT_PA_RDAC_MISC2 (0x313e) |
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| 389 | #define WCD939X_HPH_NEW_INT_PA_RDAC_MISC3 (0x313f) |
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| 390 | #define WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L (0x3140) |
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| 391 | #define WCD939X_RDAC_HD2_CTL_L_EN_HD2_RES_DIV_L BIT(7) |
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| 392 | #define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_PULLGND_L BIT(6) |
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| 393 | #define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L GENMASK(5, 0) |
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| 394 | #define WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R (0x3141) |
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| 395 | #define WCD939X_RDAC_HD2_CTL_R_EN_HD2_RES_DIV_R BIT(7) |
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| 396 | #define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_PULLGND_L BIT(6) |
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| 397 | #define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R GENMASK(5, 0) |
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| 398 | #define WCD939X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (0x3145) |
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| 399 | #define WCD939X_RX_NEW_INT_HPH_RDAC_BIAS_ULP (0x3146) |
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| 400 | #define WCD939X_RX_NEW_INT_HPH_RDAC_LDO_LP (0x3147) |
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| 401 | #define WCD939X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (0x31af) |
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| 402 | #define WCD939X_MOISTURE_DET_DC_CTRL_ONCOUNT GENMASK(6, 5) |
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| 403 | #define WCD939X_MOISTURE_DET_DC_CTRL_OFFCOUNT GENMASK(4, 0) |
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| 404 | #define WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (0x31b0) |
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| 405 | #define WCD939X_MOISTURE_DET_POLLING_CTRL_HPHL_PA_EN BIT(6) |
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| 406 | #define WCD939X_MOISTURE_DET_POLLING_CTRL_DTEST_EN GENMASK(5, 4) |
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| 407 | #define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_OVRD_POLLING BIT(3) |
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| 408 | #define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING BIT(2) |
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| 409 | #define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_DBNC_TIME GENMASK(1, 0) |
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| 410 | #define WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT (0x31b1) |
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| 411 | #define WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL GENMASK(4, 0) |
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| 412 | #define WCD939X_MBHC_NEW_INT_ZDET_CLK_AND_MOISTURE_CTL_NEW (0x31b2) |
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| 413 | #define WCD939X_EAR_INT_NEW_CHOPPER_CON (0x31b7) |
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| 414 | #define WCD939X_EAR_INT_NEW_CNP_VCM_CON1 (0x31b8) |
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| 415 | #define WCD939X_EAR_INT_NEW_CNP_VCM_CON2 (0x31b9) |
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| 416 | #define WCD939X_EAR_INT_NEW_DYNAMIC_BIAS (0x31ba) |
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| 417 | #define WCD939X_SLEEP_INT_WATCHDOG_CTL_1 (0x31d0) |
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| 418 | #define WCD939X_SLEEP_INT_WATCHDOG_CTL_2 (0x31d1) |
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| 419 | #define WCD939X_DIE_CRACK_INT_DET_INT1 (0x31d3) |
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| 420 | #define WCD939X_DIE_CRACK_INT_DET_INT2 (0x31d4) |
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| 421 | #define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_L2 (0x31d5) |
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| 422 | #define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_L1 (0x31d6) |
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| 423 | #define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_L0 (0x31d7) |
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| 424 | #define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_ULP1P2M (0x31d8) |
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| 425 | #define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_ULP0P6M (0x31d9) |
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| 426 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG1_L2L1 (0x31da) |
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| 427 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG1_L0 (0x31db) |
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| 428 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG1_ULP (0x31dc) |
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| 429 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_L2L1 (0x31dd) |
|---|
| 430 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_L0 (0x31de) |
|---|
| 431 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP (0x31df) |
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| 432 | #define WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE GENMASK(4, 0) |
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| 433 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_L2L1L0 (0x31e0) |
|---|
| 434 | #define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP (0x31e1) |
|---|
| 435 | #define WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M GENMASK(7, 4) |
|---|
| 436 | #define WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE GENMASK(3, 0) |
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| 437 | #define WCD939X_TX_COM_NEW_INT_ADC_SCBIAS_L2L1 (0x31e2) |
|---|
| 438 | #define WCD939X_TX_COM_NEW_INT_ADC_SCBIAS_L0ULP (0x31e3) |
|---|
| 439 | #define WCD939X_TX_COM_NEW_INT_ADC_INT_L2 (0x31e4) |
|---|
| 440 | #define WCD939X_TX_COM_NEW_INT_ADC_INT_L1 (0x31e5) |
|---|
| 441 | #define WCD939X_TX_COM_NEW_INT_ADC_INT_L0 (0x31e6) |
|---|
| 442 | #define WCD939X_TX_COM_NEW_INT_ADC_INT_ULP (0x31e7) |
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| 443 | #define WCD939X_DIGITAL_PAGE (0x3400) |
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| 444 | #define WCD939X_DIGITAL_CHIP_ID0 (0x3401) |
|---|
| 445 | #define WCD939X_DIGITAL_CHIP_ID1 (0x3402) |
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| 446 | #define WCD939X_DIGITAL_CHIP_ID2 (0x3403) |
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| 447 | #define WCD939X_DIGITAL_CHIP_ID3 (0x3404) |
|---|
| 448 | #define WCD939X_DIGITAL_SWR_TX_CLK_RATE (0x3405) |
|---|
| 449 | #define WCD939X_DIGITAL_CDC_RST_CTL (0x3406) |
|---|
| 450 | #define WCD939X_DIGITAL_TOP_CLK_CFG (0x3407) |
|---|
| 451 | #define WCD939X_DIGITAL_CDC_ANA_CLK_CTL (0x3408) |
|---|
| 452 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV4_CLK_EN BIT(5) |
|---|
| 453 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN BIT(4) |
|---|
| 454 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN BIT(3) |
|---|
| 455 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN BIT(2) |
|---|
| 456 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN BIT(1) |
|---|
| 457 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN BIT(0) |
|---|
| 458 | #define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN BIT(4) |
|---|
| 459 | #define WCD939X_DIGITAL_CDC_DIG_CLK_CTL (0x3409) |
|---|
| 460 | #define WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN BIT(7) |
|---|
| 461 | #define WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN BIT(6) |
|---|
| 462 | #define WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN BIT(5) |
|---|
| 463 | #define WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN BIT(4) |
|---|
| 464 | #define WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN BIT(2) |
|---|
| 465 | #define WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN BIT(1) |
|---|
| 466 | #define WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN BIT(0) |
|---|
| 467 | #define WCD939X_DIGITAL_SWR_RST_EN (0x340a) |
|---|
| 468 | #define WCD939X_DIGITAL_CDC_PATH_MODE (0x340b) |
|---|
| 469 | #define WCD939X_DIGITAL_CDC_RX_RST (0x340c) |
|---|
| 470 | #define WCD939X_DIGITAL_CDC_RX0_CTL (0x340d) |
|---|
| 471 | #define WCD939X_DIGITAL_CDC_RX1_CTL (0x340e) |
|---|
| 472 | #define WCD939X_DIGITAL_CDC_RX2_CTL (0x340f) |
|---|
| 473 | #define WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1 (0x3410) |
|---|
| 474 | #define WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE GENMASK(7, 4) |
|---|
| 475 | #define WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE GENMASK(3, 0) |
|---|
| 476 | #define WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3 (0x3411) |
|---|
| 477 | #define WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE GENMASK(7, 4) |
|---|
| 478 | #define WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE GENMASK(3, 0) |
|---|
| 479 | #define WCD939X_DIGITAL_CDC_COMP_CTL_0 (0x3414) |
|---|
| 480 | #define WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN BIT(1) |
|---|
| 481 | #define WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN BIT(0) |
|---|
| 482 | #define WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL (0x3417) |
|---|
| 483 | #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_MBHC_1P2M_CLK_EN BIT(5) |
|---|
| 484 | #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX3_ADC_CLK_EN BIT(4) |
|---|
| 485 | #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX2_ADC_CLK_EN BIT(3) |
|---|
| 486 | #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX1_ADC_CLK_EN BIT(2) |
|---|
| 487 | #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX0_ADC_CLK_EN BIT(1) |
|---|
| 488 | #define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN BIT(0) |
|---|
| 489 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A1_0 (0x3418) |
|---|
| 490 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A1_1 (0x3419) |
|---|
| 491 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A2_0 (0x341a) |
|---|
| 492 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A2_1 (0x341b) |
|---|
| 493 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A3_0 (0x341c) |
|---|
| 494 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A3_1 (0x341d) |
|---|
| 495 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A4_0 (0x341e) |
|---|
| 496 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A4_1 (0x341f) |
|---|
| 497 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A5_0 (0x3420) |
|---|
| 498 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A5_1 (0x3421) |
|---|
| 499 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A6_0 (0x3422) |
|---|
| 500 | #define WCD939X_DIGITAL_CDC_HPH_DSM_A7_0 (0x3423) |
|---|
| 501 | #define WCD939X_DIGITAL_CDC_HPH_DSM_C_0 (0x3424) |
|---|
| 502 | #define WCD939X_DIGITAL_CDC_HPH_DSM_C_1 (0x3425) |
|---|
| 503 | #define WCD939X_DIGITAL_CDC_HPH_DSM_C_2 (0x3426) |
|---|
| 504 | #define WCD939X_DIGITAL_CDC_HPH_DSM_C_3 (0x3427) |
|---|
| 505 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R1 (0x3428) |
|---|
| 506 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R2 (0x3429) |
|---|
| 507 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R3 (0x342a) |
|---|
| 508 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R4 (0x342b) |
|---|
| 509 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R5 (0x342c) |
|---|
| 510 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R6 (0x342d) |
|---|
| 511 | #define WCD939X_DIGITAL_CDC_HPH_DSM_R7 (0x342e) |
|---|
| 512 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A1_0 (0x342f) |
|---|
| 513 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A1_1 (0x3430) |
|---|
| 514 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A2_0 (0x3431) |
|---|
| 515 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A2_1 (0x3432) |
|---|
| 516 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A3_0 (0x3433) |
|---|
| 517 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A3_1 (0x3434) |
|---|
| 518 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A4_0 (0x3435) |
|---|
| 519 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A4_1 (0x3436) |
|---|
| 520 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A5_0 (0x3437) |
|---|
| 521 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A5_1 (0x3438) |
|---|
| 522 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A6_0 (0x3439) |
|---|
| 523 | #define WCD939X_DIGITAL_CDC_EAR_DSM_A7_0 (0x343a) |
|---|
| 524 | #define WCD939X_DIGITAL_CDC_EAR_DSM_C_0 (0x343b) |
|---|
| 525 | #define WCD939X_DIGITAL_CDC_EAR_DSM_C_1 (0x343c) |
|---|
| 526 | #define WCD939X_DIGITAL_CDC_EAR_DSM_C_2 (0x343d) |
|---|
| 527 | #define WCD939X_DIGITAL_CDC_EAR_DSM_C_3 (0x343e) |
|---|
| 528 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R1 (0x343f) |
|---|
| 529 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R2 (0x3440) |
|---|
| 530 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R3 (0x3441) |
|---|
| 531 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R4 (0x3442) |
|---|
| 532 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R5 (0x3443) |
|---|
| 533 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R6 (0x3444) |
|---|
| 534 | #define WCD939X_DIGITAL_CDC_EAR_DSM_R7 (0x3445) |
|---|
| 535 | #define WCD939X_DIGITAL_CDC_HPH_GAIN_RX_0 (0x3446) |
|---|
| 536 | #define WCD939X_DIGITAL_CDC_HPH_GAIN_RX_1 (0x3447) |
|---|
| 537 | #define WCD939X_DIGITAL_CDC_HPH_GAIN_DSD_0 (0x3448) |
|---|
| 538 | #define WCD939X_DIGITAL_CDC_HPH_GAIN_DSD_1 (0x3449) |
|---|
| 539 | #define WCD939X_DIGITAL_CDC_HPH_GAIN_DSD_2 (0x344a) |
|---|
| 540 | #define WCD939X_DIGITAL_CDC_EAR_GAIN_DSD_0 (0x344b) |
|---|
| 541 | #define WCD939X_DIGITAL_CDC_EAR_GAIN_DSD_1 (0x344c) |
|---|
| 542 | #define WCD939X_DIGITAL_CDC_EAR_GAIN_DSD_2 (0x344d) |
|---|
| 543 | #define WCD939X_DIGITAL_CDC_HPH_GAIN_CTL (0x344e) |
|---|
| 544 | #define WCD939X_CDC_HPH_GAIN_CTL_HPH_STEREO_EN BIT(4) |
|---|
| 545 | #define WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN BIT(3) |
|---|
| 546 | #define WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN BIT(2) |
|---|
| 547 | #define WCD939X_CDC_HPH_GAIN_CTL_HPHR_DSD_EN BIT(1) |
|---|
| 548 | #define WCD939X_CDC_HPH_GAIN_CTL_HPHL_DSD_EN BIT(0) |
|---|
| 549 | #define WCD939X_DIGITAL_CDC_EAR_GAIN_CTL (0x344f) |
|---|
| 550 | #define WCD939X_CDC_EAR_GAIN_CTL_EAR_EN BIT(0) |
|---|
| 551 | #define WCD939X_DIGITAL_CDC_EAR_PATH_CTL (0x3450) |
|---|
| 552 | #define WCD939X_DIGITAL_CDC_SWR_CLH (0x3451) |
|---|
| 553 | #define WCD939X_CDC_SWR_CLH_CLH_CTL GENMASK(7, 0) |
|---|
| 554 | #define WCD939X_DIGITAL_SWR_CLH_BYP (0x3452) |
|---|
| 555 | #define WCD939X_DIGITAL_CDC_TX0_CTL (0x3453) |
|---|
| 556 | #define WCD939X_DIGITAL_CDC_TX1_CTL (0x3454) |
|---|
| 557 | #define WCD939X_DIGITAL_CDC_TX2_CTL (0x3455) |
|---|
| 558 | #define WCD939X_DIGITAL_CDC_TX_RST (0x3456) |
|---|
| 559 | #define WCD939X_DIGITAL_CDC_REQ_CTL (0x3457) |
|---|
| 560 | #define WCD939X_CDC_REQ_CTL_TX3_WIDE_BAND BIT(5) |
|---|
| 561 | #define WCD939X_CDC_REQ_CTL_TX2_WIDE_BAND BIT(4) |
|---|
| 562 | #define WCD939X_CDC_REQ_CTL_TX1_WIDE_BAND BIT(3) |
|---|
| 563 | #define WCD939X_CDC_REQ_CTL_TX0_WIDE_BAND BIT(2) |
|---|
| 564 | #define WCD939X_CDC_REQ_CTL_FS_RATE_4P8 BIT(1) |
|---|
| 565 | #define WCD939X_CDC_REQ_CTL_NO_NOTCH BIT(0) |
|---|
| 566 | #define WCD939X_DIGITAL_CDC_RST (0x3458) |
|---|
| 567 | #define WCD939X_DIGITAL_CDC_AMIC_CTL (0x345a) |
|---|
| 568 | #define WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL BIT(3) |
|---|
| 569 | #define WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL BIT(2) |
|---|
| 570 | #define WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL BIT(1) |
|---|
| 571 | #define WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL BIT(0) |
|---|
| 572 | #define WCD939X_DIGITAL_CDC_DMIC_CTL (0x345b) |
|---|
| 573 | #define WCD939X_CDC_DMIC_CTL_DMIC_LEGACY_SW_MODE BIT(3) |
|---|
| 574 | #define WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN BIT(2) |
|---|
| 575 | #define WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN BIT(1) |
|---|
| 576 | #define WCD939X_CDC_DMIC_CTL_SOFT_RESET BIT(0) |
|---|
| 577 | #define WCD939X_DIGITAL_CDC_DMIC1_CTL (0x345c) |
|---|
| 578 | #define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4) |
|---|
| 579 | #define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN BIT(3) |
|---|
| 580 | #define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SEL GENMASK(2, 0) |
|---|
| 581 | #define WCD939X_DIGITAL_CDC_DMIC2_CTL (0x345d) |
|---|
| 582 | #define WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN BIT(7) |
|---|
| 583 | #define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4) |
|---|
| 584 | #define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN BIT(3) |
|---|
| 585 | #define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SEL GENMASK(2, 0) |
|---|
| 586 | #define WCD939X_DIGITAL_CDC_DMIC3_CTL (0x345e) |
|---|
| 587 | #define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4) |
|---|
| 588 | #define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN BIT(3) |
|---|
| 589 | #define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SEL GENMASK(2, 0) |
|---|
| 590 | #define WCD939X_DIGITAL_CDC_DMIC4_CTL (0x345f) |
|---|
| 591 | #define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4) |
|---|
| 592 | #define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN BIT(3) |
|---|
| 593 | #define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SEL GENMASK(2, 0) |
|---|
| 594 | #define WCD939X_DIGITAL_EFUSE_PRG_CTL (0x3460) |
|---|
| 595 | #define WCD939X_DIGITAL_EFUSE_CTL (0x3461) |
|---|
| 596 | #define WCD939X_DIGITAL_CDC_DMIC_RATE_1_2 (0x3462) |
|---|
| 597 | #define WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE GENMASK(7, 4) |
|---|
| 598 | #define WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE GENMASK(3, 0) |
|---|
| 599 | #define WCD939X_DIGITAL_CDC_DMIC_RATE_3_4 (0x3463) |
|---|
| 600 | #define WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE GENMASK(7, 4) |
|---|
| 601 | #define WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE GENMASK(3, 0) |
|---|
| 602 | #define WCD939X_DIGITAL_PDM_WD_CTL0 (0x3465) |
|---|
| 603 | #define WCD939X_PDM_WD_CTL0_HOLD_OFF BIT(4) |
|---|
| 604 | #define WCD939X_PDM_WD_CTL0_TIME_OUT_SEL BIT(3) |
|---|
| 605 | #define WCD939X_PDM_WD_CTL0_PDM_WD_EN GENMASK(2, 0) |
|---|
| 606 | #define WCD939X_DIGITAL_PDM_WD_CTL1 (0x3466) |
|---|
| 607 | #define WCD939X_PDM_WD_CTL1_HOLD_OFF BIT(4) |
|---|
| 608 | #define WCD939X_PDM_WD_CTL1_TIME_OUT_SEL BIT(3) |
|---|
| 609 | #define WCD939X_PDM_WD_CTL1_PDM_WD_EN GENMASK(2, 0) |
|---|
| 610 | #define WCD939X_DIGITAL_PDM_WD_CTL2 (0x3467) |
|---|
| 611 | #define WCD939X_DIGITAL_INTR_MODE (0x346a) |
|---|
| 612 | #define WCD939X_DIGITAL_INTR_MASK_0 (0x346b) |
|---|
| 613 | #define WCD939X_DIGITAL_INTR_MASK_1 (0x346c) |
|---|
| 614 | #define WCD939X_DIGITAL_INTR_MASK_2 (0x346d) |
|---|
| 615 | #define WCD939X_DIGITAL_INTR_STATUS_0 (0x346e) |
|---|
| 616 | #define WCD939X_DIGITAL_INTR_STATUS_1 (0x346f) |
|---|
| 617 | #define WCD939X_DIGITAL_INTR_STATUS_2 (0x3470) |
|---|
| 618 | #define WCD939X_DIGITAL_INTR_CLEAR_0 (0x3471) |
|---|
| 619 | #define WCD939X_DIGITAL_INTR_CLEAR_1 (0x3472) |
|---|
| 620 | #define WCD939X_DIGITAL_INTR_CLEAR_2 (0x3473) |
|---|
| 621 | #define WCD939X_DIGITAL_INTR_LEVEL_0 (0x3474) |
|---|
| 622 | #define WCD939X_DIGITAL_INTR_LEVEL_1 (0x3475) |
|---|
| 623 | #define WCD939X_DIGITAL_INTR_LEVEL_2 (0x3476) |
|---|
| 624 | #define WCD939X_DIGITAL_INTR_SET_0 (0x3477) |
|---|
| 625 | #define WCD939X_DIGITAL_INTR_SET_1 (0x3478) |
|---|
| 626 | #define WCD939X_DIGITAL_INTR_SET_2 (0x3479) |
|---|
| 627 | #define WCD939X_DIGITAL_INTR_TEST_0 (0x347a) |
|---|
| 628 | #define WCD939X_DIGITAL_INTR_TEST_1 (0x347b) |
|---|
| 629 | #define WCD939X_DIGITAL_INTR_TEST_2 (0x347c) |
|---|
| 630 | #define WCD939X_DIGITAL_TX_MODE_DBG_EN (0x347f) |
|---|
| 631 | #define WCD939X_DIGITAL_TX_MODE_DBG_0_1 (0x3480) |
|---|
| 632 | #define WCD939X_DIGITAL_TX_MODE_DBG_2_3 (0x3481) |
|---|
| 633 | #define WCD939X_DIGITAL_LB_IN_SEL_CTL (0x3482) |
|---|
| 634 | #define WCD939X_DIGITAL_LOOP_BACK_MODE (0x3483) |
|---|
| 635 | #define WCD939X_DIGITAL_SWR_DAC_TEST (0x3484) |
|---|
| 636 | #define WCD939X_DIGITAL_SWR_HM_TEST_RX_0 (0x3485) |
|---|
| 637 | #define WCD939X_DIGITAL_SWR_HM_TEST_TX_0 (0x3486) |
|---|
| 638 | #define WCD939X_DIGITAL_SWR_HM_TEST_RX_1 (0x3487) |
|---|
| 639 | #define WCD939X_DIGITAL_SWR_HM_TEST_TX_1 (0x3488) |
|---|
| 640 | #define WCD939X_DIGITAL_SWR_HM_TEST_TX_2 (0x3489) |
|---|
| 641 | #define WCD939X_DIGITAL_SWR_HM_TEST_0 (0x348a) |
|---|
| 642 | #define WCD939X_DIGITAL_SWR_HM_TEST_1 (0x348b) |
|---|
| 643 | #define WCD939X_DIGITAL_PAD_CTL_SWR_0 (0x348c) |
|---|
| 644 | #define WCD939X_DIGITAL_PAD_CTL_SWR_1 (0x348d) |
|---|
| 645 | #define WCD939X_DIGITAL_I2C_CTL (0x348e) |
|---|
| 646 | #define WCD939X_DIGITAL_CDC_TX_TANGGU_SW_MODE (0x348f) |
|---|
| 647 | #define WCD939X_DIGITAL_EFUSE_TEST_CTL_0 (0x3490) |
|---|
| 648 | #define WCD939X_DIGITAL_EFUSE_TEST_CTL_1 (0x3491) |
|---|
| 649 | #define WCD939X_DIGITAL_EFUSE_T_DATA_0 (0x3492) |
|---|
| 650 | #define WCD939X_DIGITAL_EFUSE_T_DATA_1 (0x3493) |
|---|
| 651 | #define WCD939X_DIGITAL_PAD_CTL_PDM_RX0 (0x3494) |
|---|
| 652 | #define WCD939X_DIGITAL_PAD_CTL_PDM_RX1 (0x3495) |
|---|
| 653 | #define WCD939X_DIGITAL_PAD_CTL_PDM_TX0 (0x3496) |
|---|
| 654 | #define WCD939X_DIGITAL_PAD_CTL_PDM_TX1 (0x3497) |
|---|
| 655 | #define WCD939X_DIGITAL_PAD_CTL_PDM_TX2 (0x3498) |
|---|
| 656 | #define WCD939X_DIGITAL_PAD_INP_DIS_0 (0x3499) |
|---|
| 657 | #define WCD939X_DIGITAL_PAD_INP_DIS_1 (0x349a) |
|---|
| 658 | #define WCD939X_DIGITAL_DRIVE_STRENGTH_0 (0x349b) |
|---|
| 659 | #define WCD939X_DIGITAL_DRIVE_STRENGTH_1 (0x349c) |
|---|
| 660 | #define WCD939X_DIGITAL_DRIVE_STRENGTH_2 (0x349d) |
|---|
| 661 | #define WCD939X_DIGITAL_RX_DATA_EDGE_CTL (0x349e) |
|---|
| 662 | #define WCD939X_DIGITAL_TX_DATA_EDGE_CTL (0x349f) |
|---|
| 663 | #define WCD939X_DIGITAL_GPIO_MODE (0x34a0) |
|---|
| 664 | #define WCD939X_DIGITAL_PIN_CTL_OE (0x34a1) |
|---|
| 665 | #define WCD939X_DIGITAL_PIN_CTL_DATA_0 (0x34a2) |
|---|
| 666 | #define WCD939X_DIGITAL_PIN_CTL_DATA_1 (0x34a3) |
|---|
| 667 | #define WCD939X_DIGITAL_PIN_STATUS_0 (0x34a4) |
|---|
| 668 | #define WCD939X_DIGITAL_PIN_STATUS_1 (0x34a5) |
|---|
| 669 | #define WCD939X_DIGITAL_DIG_DEBUG_CTL (0x34a6) |
|---|
| 670 | #define WCD939X_DIGITAL_DIG_DEBUG_EN (0x34a7) |
|---|
| 671 | #define WCD939X_DIGITAL_ANA_CSR_DBG_ADD (0x34a8) |
|---|
| 672 | #define WCD939X_DIGITAL_ANA_CSR_DBG_CTL (0x34a9) |
|---|
| 673 | #define WCD939X_DIGITAL_SSP_DBG (0x34aa) |
|---|
| 674 | #define WCD939X_DIGITAL_MODE_STATUS_0 (0x34ab) |
|---|
| 675 | #define WCD939X_DIGITAL_MODE_STATUS_1 (0x34ac) |
|---|
| 676 | #define WCD939X_DIGITAL_SPARE_0 (0x34ad) |
|---|
| 677 | #define WCD939X_DIGITAL_SPARE_1 (0x34ae) |
|---|
| 678 | #define WCD939X_DIGITAL_SPARE_2 (0x34af) |
|---|
| 679 | #define WCD939X_DIGITAL_EFUSE_REG_0 (0x34b0) |
|---|
| 680 | #define WCD939X_EFUSE_REG_0_WCD939X_ID GENMASK(4, 1) |
|---|
| 681 | #define WCD939X_EFUSE_REG_0_EFUSE_BLOWN BIT(0) |
|---|
| 682 | #define WCD939X_DIGITAL_EFUSE_REG_1 (0x34b1) |
|---|
| 683 | #define WCD939X_DIGITAL_EFUSE_REG_2 (0x34b2) |
|---|
| 684 | #define WCD939X_DIGITAL_EFUSE_REG_3 (0x34b3) |
|---|
| 685 | #define WCD939X_DIGITAL_EFUSE_REG_4 (0x34b4) |
|---|
| 686 | #define WCD939X_DIGITAL_EFUSE_REG_5 (0x34b5) |
|---|
| 687 | #define WCD939X_DIGITAL_EFUSE_REG_6 (0x34b6) |
|---|
| 688 | #define WCD939X_DIGITAL_EFUSE_REG_7 (0x34b7) |
|---|
| 689 | #define WCD939X_DIGITAL_EFUSE_REG_8 (0x34b8) |
|---|
| 690 | #define WCD939X_DIGITAL_EFUSE_REG_9 (0x34b9) |
|---|
| 691 | #define WCD939X_DIGITAL_EFUSE_REG_10 (0x34ba) |
|---|
| 692 | #define WCD939X_DIGITAL_EFUSE_REG_11 (0x34bb) |
|---|
| 693 | #define WCD939X_DIGITAL_EFUSE_REG_12 (0x34bc) |
|---|
| 694 | #define WCD939X_DIGITAL_EFUSE_REG_13 (0x34bd) |
|---|
| 695 | #define WCD939X_DIGITAL_EFUSE_REG_14 (0x34be) |
|---|
| 696 | #define WCD939X_DIGITAL_EFUSE_REG_15 (0x34bf) |
|---|
| 697 | #define WCD939X_DIGITAL_EFUSE_REG_16 (0x34c0) |
|---|
| 698 | #define WCD939X_DIGITAL_EFUSE_REG_17 (0x34c1) |
|---|
| 699 | #define WCD939X_DIGITAL_EFUSE_REG_18 (0x34c2) |
|---|
| 700 | #define WCD939X_DIGITAL_EFUSE_REG_19 (0x34c3) |
|---|
| 701 | #define WCD939X_DIGITAL_EFUSE_REG_20 (0x34c4) |
|---|
| 702 | #define WCD939X_DIGITAL_EFUSE_REG_21 (0x34c5) |
|---|
| 703 | #define WCD939X_DIGITAL_EFUSE_REG_22 (0x34c6) |
|---|
| 704 | #define WCD939X_DIGITAL_EFUSE_REG_23 (0x34c7) |
|---|
| 705 | #define WCD939X_DIGITAL_EFUSE_REG_24 (0x34c8) |
|---|
| 706 | #define WCD939X_DIGITAL_EFUSE_REG_25 (0x34c9) |
|---|
| 707 | #define WCD939X_DIGITAL_EFUSE_REG_26 (0x34ca) |
|---|
| 708 | #define WCD939X_DIGITAL_EFUSE_REG_27 (0x34cb) |
|---|
| 709 | #define WCD939X_DIGITAL_EFUSE_REG_28 (0x34cc) |
|---|
| 710 | #define WCD939X_DIGITAL_EFUSE_REG_29 (0x34cd) |
|---|
| 711 | #define WCD939X_DIGITAL_EFUSE_REG_30 (0x34ce) |
|---|
| 712 | #define WCD939X_DIGITAL_EFUSE_REG_31 (0x34cf) |
|---|
| 713 | #define WCD939X_DIGITAL_TX_REQ_FB_CTL_0 (0x34d0) |
|---|
| 714 | #define WCD939X_DIGITAL_TX_REQ_FB_CTL_1 (0x34d1) |
|---|
| 715 | #define WCD939X_DIGITAL_TX_REQ_FB_CTL_2 (0x34d2) |
|---|
| 716 | #define WCD939X_DIGITAL_TX_REQ_FB_CTL_3 (0x34d3) |
|---|
| 717 | #define WCD939X_DIGITAL_TX_REQ_FB_CTL_4 (0x34d4) |
|---|
| 718 | #define WCD939X_DIGITAL_DEM_BYPASS_DATA0 (0x34d5) |
|---|
| 719 | #define WCD939X_DIGITAL_DEM_BYPASS_DATA1 (0x34d6) |
|---|
| 720 | #define WCD939X_DIGITAL_DEM_BYPASS_DATA2 (0x34d7) |
|---|
| 721 | #define WCD939X_DIGITAL_DEM_BYPASS_DATA3 (0x34d8) |
|---|
| 722 | #define WCD939X_DIGITAL_DEM_SECOND_ORDER (0x34d9) |
|---|
| 723 | #define WCD939X_DIGITAL_DSM_CTRL (0x34da) |
|---|
| 724 | #define WCD939X_DIGITAL_DSM_0_STATIC_DATA_0 (0x34db) |
|---|
| 725 | #define WCD939X_DIGITAL_DSM_0_STATIC_DATA_1 (0x34dc) |
|---|
| 726 | #define WCD939X_DIGITAL_DSM_0_STATIC_DATA_2 (0x34dd) |
|---|
| 727 | #define WCD939X_DIGITAL_DSM_0_STATIC_DATA_3 (0x34de) |
|---|
| 728 | #define WCD939X_DIGITAL_DSM_1_STATIC_DATA_0 (0x34df) |
|---|
| 729 | #define WCD939X_DIGITAL_DSM_1_STATIC_DATA_1 (0x34e0) |
|---|
| 730 | #define WCD939X_DIGITAL_DSM_1_STATIC_DATA_2 (0x34e1) |
|---|
| 731 | #define WCD939X_DIGITAL_DSM_1_STATIC_DATA_3 (0x34e2) |
|---|
| 732 | #define WCD939X_RX_TOP_PAGE (0x3500) |
|---|
| 733 | #define WCD939X_RX_TOP_TOP_CFG0 (0x3501) |
|---|
| 734 | #define WCD939X_TOP_CFG0_HPH_DAC_RATE_SEL BIT(1) |
|---|
| 735 | #define WCD939X_TOP_CFG0_PGA_UPDATE BIT(0) |
|---|
| 736 | #define WCD939X_RX_TOP_HPHL_COMP_WR_LSB (0x3502) |
|---|
| 737 | #define WCD939X_RX_TOP_HPHL_COMP_WR_MSB (0x3503) |
|---|
| 738 | #define WCD939X_RX_TOP_HPHL_COMP_LUT (0x3504) |
|---|
| 739 | #define WCD939X_RX_TOP_HPHL_COMP_RD_LSB (0x3505) |
|---|
| 740 | #define WCD939X_RX_TOP_HPHL_COMP_RD_MSB (0x3506) |
|---|
| 741 | #define WCD939X_RX_TOP_HPHR_COMP_WR_LSB (0x3507) |
|---|
| 742 | #define WCD939X_RX_TOP_HPHR_COMP_WR_MSB (0x3508) |
|---|
| 743 | #define WCD939X_RX_TOP_HPHR_COMP_LUT (0x3509) |
|---|
| 744 | #define WCD939X_RX_TOP_HPHR_COMP_RD_LSB (0x350a) |
|---|
| 745 | #define WCD939X_RX_TOP_HPHR_COMP_RD_MSB (0x350b) |
|---|
| 746 | #define WCD939X_RX_TOP_DSD0_DEBUG_CFG1 (0x350c) |
|---|
| 747 | #define WCD939X_RX_TOP_DSD0_DEBUG_CFG2 (0x350d) |
|---|
| 748 | #define WCD939X_RX_TOP_DSD0_DEBUG_CFG3 (0x350e) |
|---|
| 749 | #define WCD939X_RX_TOP_DSD0_DEBUG_CFG4 (0x350f) |
|---|
| 750 | #define WCD939X_RX_TOP_DSD0_DEBUG_CFG5 (0x3510) |
|---|
| 751 | #define WCD939X_RX_TOP_DSD0_DEBUG_CFG6 (0x3511) |
|---|
| 752 | #define WCD939X_RX_TOP_DSD1_DEBUG_CFG1 (0x3512) |
|---|
| 753 | #define WCD939X_RX_TOP_DSD1_DEBUG_CFG2 (0x3513) |
|---|
| 754 | #define WCD939X_RX_TOP_DSD1_DEBUG_CFG3 (0x3514) |
|---|
| 755 | #define WCD939X_RX_TOP_DSD1_DEBUG_CFG4 (0x3515) |
|---|
| 756 | #define WCD939X_RX_TOP_DSD1_DEBUG_CFG5 (0x3516) |
|---|
| 757 | #define WCD939X_RX_TOP_DSD1_DEBUG_CFG6 (0x3517) |
|---|
| 758 | #define WCD939X_RX_TOP_HPHL_PATH_CFG0 (0x351c) |
|---|
| 759 | #define WCD939X_HPHL_PATH_CFG0_INT_EN BIT(1) |
|---|
| 760 | #define WCD939X_HPHL_PATH_CFG0_DLY_ZN_EN BIT(0) |
|---|
| 761 | #define WCD939X_RX_TOP_HPHL_PATH_CFG1 (0x351d) |
|---|
| 762 | #define WCD939X_HPHL_PATH_CFG1_DSM_SOFT_RST BIT(5) |
|---|
| 763 | #define WCD939X_HPHL_PATH_CFG1_INT_SOFT_RST BIT(4) |
|---|
| 764 | #define WCD939X_HPHL_PATH_CFG1_FMT_CONV BIT(3) |
|---|
| 765 | #define WCD939X_HPHL_PATH_CFG1_IDLE_OVRD_EN BIT(2) |
|---|
| 766 | #define WCD939X_HPHL_PATH_CFG1_RX_DC_DROOP_COEFF_SEL GENMASK(1, 0) |
|---|
| 767 | #define WCD939X_RX_TOP_HPHR_PATH_CFG0 (0x351e) |
|---|
| 768 | #define WCD939X_HPHR_PATH_CFG0_INT_EN BIT(2) |
|---|
| 769 | #define WCD939X_HPHR_PATH_CFG0_DLY_ZN_EN BIT(1) |
|---|
| 770 | #define WCD939X_RX_TOP_HPHR_PATH_CFG1 (0x351f) |
|---|
| 771 | #define WCD939X_HPHR_PATH_CFG1_DSM_SOFT_RST BIT(5) |
|---|
| 772 | #define WCD939X_HPHR_PATH_CFG1_INT_SOFT_RST BIT(4) |
|---|
| 773 | #define WCD939X_HPHR_PATH_CFG1_FMT_CONV BIT(3) |
|---|
| 774 | #define WCD939X_HPHR_PATH_CFG1_IDLE_OVRD_EN BIT(2) |
|---|
| 775 | #define WCD939X_HPHR_PATH_CFG1_RX_DC_DROOP_COEFF_SEL GENMASK(1, 0) |
|---|
| 776 | #define WCD939X_RX_TOP_PATH_CFG2 (0x3520) |
|---|
| 777 | #define WCD939X_RX_TOP_HPHL_PATH_SEC0 (0x3521) |
|---|
| 778 | #define WCD939X_RX_TOP_HPHL_PATH_SEC1 (0x3522) |
|---|
| 779 | #define WCD939X_RX_TOP_HPHL_PATH_SEC2 (0x3523) |
|---|
| 780 | #define WCD939X_RX_TOP_HPHL_PATH_SEC3 (0x3524) |
|---|
| 781 | #define WCD939X_RX_TOP_HPHR_PATH_SEC0 (0x3525) |
|---|
| 782 | #define WCD939X_RX_TOP_HPHR_PATH_SEC1 (0x3526) |
|---|
| 783 | #define WCD939X_RX_TOP_HPHR_PATH_SEC2 (0x3527) |
|---|
| 784 | #define WCD939X_RX_TOP_HPHR_PATH_SEC3 (0x3528) |
|---|
| 785 | #define WCD939X_RX_TOP_PATH_SEC4 (0x3529) |
|---|
| 786 | #define WCD939X_RX_TOP_PATH_SEC5 (0x352a) |
|---|
| 787 | #define WCD939X_COMPANDER_HPHL_CTL0 (0x3540) |
|---|
| 788 | #define WCD939X_COMPANDER_HPHL_CTL1 (0x3541) |
|---|
| 789 | #define WCD939X_COMPANDER_HPHL_CTL2 (0x3542) |
|---|
| 790 | #define WCD939X_COMPANDER_HPHL_CTL3 (0x3543) |
|---|
| 791 | #define WCD939X_COMPANDER_HPHL_CTL4 (0x3544) |
|---|
| 792 | #define WCD939X_COMPANDER_HPHL_CTL5 (0x3545) |
|---|
| 793 | #define WCD939X_COMPANDER_HPHL_CTL6 (0x3546) |
|---|
| 794 | #define WCD939X_COMPANDER_HPHL_CTL7 (0x3547) |
|---|
| 795 | #define WCD939X_COMPANDER_HPHL_CTL8 (0x3548) |
|---|
| 796 | #define WCD939X_COMPANDER_HPHL_CTL9 (0x3549) |
|---|
| 797 | #define WCD939X_COMPANDER_HPHL_CTL10 (0x354a) |
|---|
| 798 | #define WCD939X_COMPANDER_HPHL_CTL11 (0x354b) |
|---|
| 799 | #define WCD939X_COMPANDER_HPHL_CTL12 (0x354c) |
|---|
| 800 | #define WCD939X_COMPANDER_HPHL_CTL13 (0x354d) |
|---|
| 801 | #define WCD939X_COMPANDER_HPHL_CTL14 (0x354e) |
|---|
| 802 | #define WCD939X_COMPANDER_HPHL_CTL15 (0x354f) |
|---|
| 803 | #define WCD939X_COMPANDER_HPHL_CTL16 (0x3550) |
|---|
| 804 | #define WCD939X_COMPANDER_HPHL_CTL17 (0x3551) |
|---|
| 805 | #define WCD939X_COMPANDER_HPHL_CTL18 (0x3552) |
|---|
| 806 | #define WCD939X_COMPANDER_HPHL_CTL19 (0x3553) |
|---|
| 807 | #define WCD939X_R_CTL0 (0x3560) |
|---|
| 808 | #define WCD939X_R_CTL1 (0x3561) |
|---|
| 809 | #define WCD939X_R_CTL2 (0x3562) |
|---|
| 810 | #define WCD939X_R_CTL3 (0x3563) |
|---|
| 811 | #define WCD939X_R_CTL4 (0x3564) |
|---|
| 812 | #define WCD939X_R_CTL5 (0x3565) |
|---|
| 813 | #define WCD939X_R_CTL6 (0x3566) |
|---|
| 814 | #define WCD939X_R_CTL7 (0x3567) |
|---|
| 815 | #define WCD939X_R_CTL8 (0x3568) |
|---|
| 816 | #define WCD939X_R_CTL9 (0x3569) |
|---|
| 817 | #define WCD939X_R_CTL10 (0x356a) |
|---|
| 818 | #define WCD939X_R_CTL11 (0x356b) |
|---|
| 819 | #define WCD939X_R_CTL12 (0x356c) |
|---|
| 820 | #define WCD939X_R_CTL13 (0x356d) |
|---|
| 821 | #define WCD939X_R_CTL14 (0x356e) |
|---|
| 822 | #define WCD939X_R_CTL15 (0x356f) |
|---|
| 823 | #define WCD939X_R_CTL16 (0x3570) |
|---|
| 824 | #define WCD939X_R_CTL17 (0x3571) |
|---|
| 825 | #define WCD939X_R_CTL18 (0x3572) |
|---|
| 826 | #define WCD939X_R_CTL19 (0x3573) |
|---|
| 827 | #define WCD939X_E_PATH_CTL (0x3580) |
|---|
| 828 | #define WCD939X_E_CFG0 (0x3581) |
|---|
| 829 | #define WCD939X_CFG0_AUTO_DISABLE_ANC BIT(2) |
|---|
| 830 | #define WCD939X_CFG0_AUTO_DISABLE_DSD BIT(1) |
|---|
| 831 | #define WCD939X_CFG0_IDLE_STEREO BIT(0) |
|---|
| 832 | #define WCD939X_E_CFG1 (0x3582) |
|---|
| 833 | #define WCD939X_E_CFG2 (0x3583) |
|---|
| 834 | #define WCD939X_E_CFG3 (0x3584) |
|---|
| 835 | #define WCD939X_DSD_HPHL_PATH_CTL (0x3590) |
|---|
| 836 | #define WCD939X_DSD_HPHL_CFG0 (0x3591) |
|---|
| 837 | #define WCD939X_DSD_HPHL_CFG1 (0x3592) |
|---|
| 838 | #define WCD939X_DSD_HPHL_CFG2 (0x3593) |
|---|
| 839 | #define WCD939X_DSD_HPHL_CFG3 (0x3594) |
|---|
| 840 | #define WCD939X_DSD_HPHL_CFG4 (0x3595) |
|---|
| 841 | #define WCD939X_DSD_HPHL_CFG5 (0x3596) |
|---|
| 842 | #define WCD939X_DSD_HPHR_PATH_CTL (0x35a0) |
|---|
| 843 | #define WCD939X_DSD_HPHR_CFG0 (0x35a1) |
|---|
| 844 | #define WCD939X_DSD_HPHR_CFG1 (0x35a2) |
|---|
| 845 | #define WCD939X_DSD_HPHR_CFG2 (0x35a3) |
|---|
| 846 | #define WCD939X_DSD_HPHR_CFG3 (0x35a4) |
|---|
| 847 | #define WCD939X_DSD_HPHR_CFG4 (0x35a5) |
|---|
| 848 | #define WCD939X_DSD_HPHR_CFG5 (0x35a6) |
|---|
| 849 | #define WCD939X_MAX_REGISTER (WCD939X_DSD_HPHR_CFG5) |
|---|
| 850 | |
|---|
| 851 | #define WCD939X_MAX_SWR_PORTS (6) |
|---|
| 852 | #define WCD939X_MAX_RX_SWR_PORTS (6) |
|---|
| 853 | #define WCD939X_MAX_TX_SWR_PORTS (4) |
|---|
| 854 | #define WCD939X_MAX_SWR_CH_IDS (15) |
|---|
| 855 | |
|---|
| 856 | struct wcd939x_sdw_ch_info { |
|---|
| 857 | int port_num; |
|---|
| 858 | unsigned int ch_mask; |
|---|
| 859 | }; |
|---|
| 860 | |
|---|
| 861 | #define WCD_SDW_CH(id, pn, cmask) \ |
|---|
| 862 | [id] = { \ |
|---|
| 863 | .port_num = pn, \ |
|---|
| 864 | .ch_mask = cmask, \ |
|---|
| 865 | } |
|---|
| 866 | |
|---|
| 867 | enum wcd939x_tx_sdw_ports { |
|---|
| 868 | WCD939X_ADC_1_4_PORT = 1, |
|---|
| 869 | WCD939X_ADC_DMIC_1_2_PORT, |
|---|
| 870 | WCD939X_DMIC_0_3_MBHC_PORT, |
|---|
| 871 | WCD939X_DMIC_3_7_PORT, |
|---|
| 872 | }; |
|---|
| 873 | |
|---|
| 874 | enum wcd939x_tx_sdw_channels { |
|---|
| 875 | WCD939X_ADC1, |
|---|
| 876 | WCD939X_ADC2, |
|---|
| 877 | WCD939X_ADC3, |
|---|
| 878 | WCD939X_ADC4, |
|---|
| 879 | WCD939X_DMIC0, |
|---|
| 880 | WCD939X_DMIC1, |
|---|
| 881 | WCD939X_MBHC, |
|---|
| 882 | WCD939X_DMIC2, |
|---|
| 883 | WCD939X_DMIC3, |
|---|
| 884 | WCD939X_DMIC4, |
|---|
| 885 | WCD939X_DMIC5, |
|---|
| 886 | WCD939X_DMIC6, |
|---|
| 887 | WCD939X_DMIC7, |
|---|
| 888 | }; |
|---|
| 889 | |
|---|
| 890 | enum wcd939x_rx_sdw_ports { |
|---|
| 891 | WCD939X_HPH_PORT = 1, |
|---|
| 892 | WCD939X_CLSH_PORT, |
|---|
| 893 | WCD939X_COMP_PORT, |
|---|
| 894 | WCD939X_LO_PORT, |
|---|
| 895 | WCD939X_DSD_PORT, |
|---|
| 896 | WCD939X_HIFI_PCM_PORT, |
|---|
| 897 | }; |
|---|
| 898 | |
|---|
| 899 | enum wcd939x_rx_sdw_channels { |
|---|
| 900 | WCD939X_HPH_L, |
|---|
| 901 | WCD939X_HPH_R, |
|---|
| 902 | WCD939X_CLSH, |
|---|
| 903 | WCD939X_COMP_L, |
|---|
| 904 | WCD939X_COMP_R, |
|---|
| 905 | WCD939X_LO, |
|---|
| 906 | WCD939X_DSD_L, |
|---|
| 907 | WCD939X_DSD_R, |
|---|
| 908 | WCD939X_HIFI_PCM_L, |
|---|
| 909 | WCD939X_HIFI_PCM_R, |
|---|
| 910 | }; |
|---|
| 911 | |
|---|
| 912 | enum { |
|---|
| 913 | WCD939X_SDW_DIR_RX, |
|---|
| 914 | WCD939X_SDW_DIR_TX, |
|---|
| 915 | }; |
|---|
| 916 | |
|---|
| 917 | struct wcd939x_priv; |
|---|
| 918 | struct wcd939x_sdw_priv { |
|---|
| 919 | struct sdw_slave *sdev; |
|---|
| 920 | struct sdw_stream_config sconfig; |
|---|
| 921 | struct sdw_stream_runtime *sruntime; |
|---|
| 922 | struct sdw_port_config port_config[WCD939X_MAX_SWR_PORTS]; |
|---|
| 923 | struct wcd939x_sdw_ch_info *ch_info; |
|---|
| 924 | bool port_enable[WCD939X_MAX_SWR_CH_IDS]; |
|---|
| 925 | int active_ports; |
|---|
| 926 | int num_ports; |
|---|
| 927 | bool is_tx; |
|---|
| 928 | struct wcd939x_priv *wcd939x; |
|---|
| 929 | struct irq_domain *slave_irq; |
|---|
| 930 | struct regmap *regmap; |
|---|
| 931 | }; |
|---|
| 932 | |
|---|
| 933 | #if IS_ENABLED(CONFIG_SND_SOC_WCD939X_SDW) |
|---|
| 934 | int wcd939x_sdw_free(struct wcd939x_sdw_priv *wcd, |
|---|
| 935 | struct snd_pcm_substream *substream, |
|---|
| 936 | struct snd_soc_dai *dai); |
|---|
| 937 | int wcd939x_sdw_set_sdw_stream(struct wcd939x_sdw_priv *wcd, |
|---|
| 938 | struct snd_soc_dai *dai, |
|---|
| 939 | void *stream, int direction); |
|---|
| 940 | int wcd939x_sdw_hw_params(struct wcd939x_sdw_priv *wcd, |
|---|
| 941 | struct snd_pcm_substream *substream, |
|---|
| 942 | struct snd_pcm_hw_params *params, |
|---|
| 943 | struct snd_soc_dai *dai); |
|---|
| 944 | |
|---|
| 945 | struct device *wcd939x_sdw_device_get(struct device_node *np); |
|---|
| 946 | unsigned int wcd939x_swr_get_current_bank(struct sdw_slave *sdev); |
|---|
| 947 | |
|---|
| 948 | struct regmap *wcd939x_swr_get_regmap(struct wcd939x_sdw_priv *wcd); |
|---|
| 949 | #else |
|---|
| 950 | |
|---|
| 951 | static inline int wcd939x_sdw_free(struct wcd939x_sdw_priv *wcd, |
|---|
| 952 | struct snd_pcm_substream *substream, |
|---|
| 953 | struct snd_soc_dai *dai) |
|---|
| 954 | { |
|---|
| 955 | return -EOPNOTSUPP; |
|---|
| 956 | } |
|---|
| 957 | |
|---|
| 958 | static inline int wcd939x_sdw_set_sdw_stream(struct wcd939x_sdw_priv *wcd, |
|---|
| 959 | struct snd_soc_dai *dai, |
|---|
| 960 | void *stream, int direction) |
|---|
| 961 | { |
|---|
| 962 | return -EOPNOTSUPP; |
|---|
| 963 | } |
|---|
| 964 | |
|---|
| 965 | static inline int wcd939x_sdw_hw_params(struct wcd939x_sdw_priv *wcd, |
|---|
| 966 | struct snd_pcm_substream *substream, |
|---|
| 967 | struct snd_pcm_hw_params *params, |
|---|
| 968 | struct snd_soc_dai *dai) |
|---|
| 969 | { |
|---|
| 970 | return -EOPNOTSUPP; |
|---|
| 971 | } |
|---|
| 972 | |
|---|
| 973 | static inline struct device *wcd939x_sdw_device_get(struct device_node *np) |
|---|
| 974 | { |
|---|
| 975 | return NULL; |
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| 976 | } |
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| 977 | |
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| 978 | static inline unsigned int wcd939x_swr_get_current_bank(struct sdw_slave *sdev) |
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| 979 | { |
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| 980 | return 0; |
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| 981 | } |
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| 982 | |
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| 983 | struct regmap *wcd939x_swr_get_regmap(struct wcd939x_sdw_priv *wcd) |
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| 984 | { |
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| 985 | return PTR_ERR(-EINVAL); |
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| 986 | } |
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| 987 | #endif /* CONFIG_SND_SOC_WCD939X_SDW */ |
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| 988 | |
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| 989 | #endif /* __WCD939X_H__ */ |
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| 990 | |
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