| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __LPASS_LPAIF_REG_H__ |
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| 7 | #define __LPASS_LPAIF_REG_H__ |
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| 8 | |
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| 9 | /* LPAIF I2S */ |
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| 10 | |
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| 11 | #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ |
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| 12 | (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port)) |
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| 13 | |
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| 14 | #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) |
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| 15 | |
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| 16 | #define LPAIF_I2SCTL_LOOPBACK_DISABLE 0 |
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| 17 | #define LPAIF_I2SCTL_LOOPBACK_ENABLE 1 |
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| 18 | |
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| 19 | #define LPAIF_I2SCTL_SPKEN_DISABLE 0 |
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| 20 | #define LPAIF_I2SCTL_SPKEN_ENABLE 1 |
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| 21 | |
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| 22 | #define LPAIF_I2SCTL_MODE_NONE 0 |
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| 23 | #define LPAIF_I2SCTL_MODE_SD0 1 |
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| 24 | #define LPAIF_I2SCTL_MODE_SD1 2 |
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| 25 | #define LPAIF_I2SCTL_MODE_SD2 3 |
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| 26 | #define LPAIF_I2SCTL_MODE_SD3 4 |
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| 27 | #define LPAIF_I2SCTL_MODE_QUAD01 5 |
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| 28 | #define LPAIF_I2SCTL_MODE_QUAD23 6 |
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| 29 | #define LPAIF_I2SCTL_MODE_6CH 7 |
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| 30 | #define LPAIF_I2SCTL_MODE_8CH 8 |
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| 31 | #define LPAIF_I2SCTL_MODE_10CH 9 |
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| 32 | #define LPAIF_I2SCTL_MODE_12CH 10 |
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| 33 | #define LPAIF_I2SCTL_MODE_14CH 11 |
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| 34 | #define LPAIF_I2SCTL_MODE_16CH 12 |
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| 35 | #define LPAIF_I2SCTL_MODE_SD4 13 |
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| 36 | #define LPAIF_I2SCTL_MODE_SD5 14 |
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| 37 | #define LPAIF_I2SCTL_MODE_SD6 15 |
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| 38 | #define LPAIF_I2SCTL_MODE_SD7 16 |
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| 39 | #define LPAIF_I2SCTL_MODE_QUAD45 17 |
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| 40 | #define LPAIF_I2SCTL_MODE_QUAD47 18 |
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| 41 | #define LPAIF_I2SCTL_MODE_8CH_2 19 |
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| 42 | |
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| 43 | #define LPAIF_I2SCTL_SPKMODE(mode) mode |
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| 44 | |
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| 45 | #define LPAIF_I2SCTL_SPKMONO_STEREO 0 |
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| 46 | #define LPAIF_I2SCTL_SPKMONO_MONO 1 |
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| 47 | |
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| 48 | #define LPAIF_I2SCTL_MICEN_DISABLE 0 |
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| 49 | #define LPAIF_I2SCTL_MICEN_ENABLE 1 |
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| 50 | |
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| 51 | #define LPAIF_I2SCTL_MICMODE(mode) mode |
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| 52 | |
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| 53 | #define LPAIF_I2SCTL_MICMONO_STEREO 0 |
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| 54 | #define LPAIF_I2SCTL_MICMONO_MONO 1 |
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| 55 | |
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| 56 | #define LPAIF_I2SCTL_WSSRC_INTERNAL 0 |
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| 57 | #define LPAIF_I2SCTL_WSSRC_EXTERNAL 1 |
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| 58 | |
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| 59 | #define LPAIF_I2SCTL_BITWIDTH_16 0 |
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| 60 | #define LPAIF_I2SCTL_BITWIDTH_24 1 |
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| 61 | #define LPAIF_I2SCTL_BITWIDTH_32 2 |
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| 62 | |
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| 63 | #define LPAIF_I2SCTL_RESET_STATE 0x003C0004 |
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| 64 | #define LPAIF_DMACTL_RESET_STATE 0x00200000 |
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| 65 | |
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| 66 | |
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| 67 | /* LPAIF IRQ */ |
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| 68 | #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ |
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| 69 | (v->irq_reg_base + (addr) + v->irq_reg_stride * (port)) |
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| 70 | |
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| 71 | #define LPAIF_IRQ_PORT_HOST 0 |
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| 72 | |
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| 73 | #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) |
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| 74 | #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) |
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| 75 | #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) |
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| 76 | |
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| 77 | /* LPAIF RXTX IRQ */ |
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| 78 | #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \ |
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| 79 | (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port)) |
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| 80 | |
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| 81 | #define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port) |
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| 82 | #define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port) |
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| 83 | #define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port) |
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| 84 | |
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| 85 | /* LPAIF VA IRQ */ |
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| 86 | #define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \ |
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| 87 | (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port)) |
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| 88 | |
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| 89 | #define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port) |
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| 90 | #define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port) |
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| 91 | #define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port) |
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| 92 | |
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| 93 | #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \ |
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| 94 | ((v->hdmi_irq_reg_base) + (addr)) |
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| 95 | |
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| 96 | #define LPASS_HDMITX_APP_IRQEN_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4) |
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| 97 | #define LPASS_HDMITX_APP_IRQSTAT_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8) |
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| 98 | #define LPASS_HDMITX_APP_IRQCLEAR_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC) |
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| 99 | |
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| 100 | #define LPAIF_IRQ_BITSTRIDE 3 |
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| 101 | |
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| 102 | #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) |
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| 103 | #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) |
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| 104 | #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) |
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| 105 | |
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| 106 | #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) |
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| 107 | #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan)) |
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| 108 | #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) (1 << (24 + chan)) |
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| 109 | #define LPAIF_IRQ_HDMI_METADONE BIT(23) |
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| 110 | |
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| 111 | /* LPAIF DMA */ |
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| 112 | #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \ |
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| 113 | (v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan)) |
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| 114 | |
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| 115 | #define LPAIF_HDMI_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT) |
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| 116 | |
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| 117 | #define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan)) |
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| 118 | #define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan)) |
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| 119 | #define LPAIF_HDMI_RDMABUFF_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan)) |
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| 120 | #define LPAIF_HDMI_RDMACURR_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan)) |
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| 121 | #define LPAIF_HDMI_RDMAPER_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan)) |
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| 122 | #define LPAIF_HDMI_RDMAPERCNT_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan)) |
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| 123 | |
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| 124 | #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \ |
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| 125 | (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan)) |
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| 126 | |
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| 127 | #define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT) |
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| 128 | |
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| 129 | #define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan)) |
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| 130 | #define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan)) |
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| 131 | #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan)) |
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| 132 | #define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan)) |
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| 133 | #define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan)) |
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| 134 | #define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan)) |
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| 135 | |
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| 136 | #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \ |
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| 137 | (v->wrdma_reg_base + (addr) + \ |
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| 138 | v->wrdma_reg_stride * (chan - v->wrdma_channel_start)) |
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| 139 | |
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| 140 | #define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan)) |
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| 141 | #define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan)) |
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| 142 | #define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan)) |
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| 143 | #define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan)) |
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| 144 | #define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan)) |
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| 145 | #define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan)) |
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| 146 | |
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| 147 | #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id) \ |
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| 148 | ((dai_id == LPASS_DP_RX) ? \ |
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| 149 | LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \ |
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| 150 | LPAIF_RDMA##reg##_REG(v, chan)) |
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| 151 | |
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| 152 | #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id) \ |
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| 153 | ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \ |
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| 154 | (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \ |
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| 155 | LPAIF_WRDMA##reg##_REG(v, chan)) |
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| 156 | |
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| 157 | #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \ |
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| 158 | (is_cdc_dma_port(dai_id) ? \ |
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| 159 | __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \ |
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| 160 | __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)) |
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| 161 | #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \ |
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| 162 | (is_cdc_dma_port(dai_id) ? \ |
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| 163 | __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \ |
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| 164 | __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)) |
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| 165 | #define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \ |
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| 166 | (is_cdc_dma_port(dai_id) ? \ |
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| 167 | __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \ |
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| 168 | __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)) |
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| 169 | #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \ |
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| 170 | (is_cdc_dma_port(dai_id) ? \ |
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| 171 | __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \ |
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| 172 | __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)) |
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| 173 | #define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \ |
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| 174 | (is_cdc_dma_port(dai_id) ? \ |
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| 175 | __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \ |
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| 176 | __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)) |
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| 177 | #define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \ |
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| 178 | (is_cdc_dma_port(dai_id) ? \ |
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| 179 | __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \ |
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| 180 | __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)) |
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| 181 | |
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| 182 | #define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \ |
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| 183 | (is_rxtx_cdc_dma_port(dai_id) ? \ |
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| 184 | (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \ |
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| 185 | (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan))) |
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| 186 | |
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| 187 | #define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \ |
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| 188 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id) |
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| 189 | #define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \ |
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| 190 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id) |
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| 191 | #define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \ |
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| 192 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id) |
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| 193 | #define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \ |
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| 194 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id) |
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| 195 | #define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \ |
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| 196 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id) |
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| 197 | #define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \ |
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| 198 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id) |
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| 199 | |
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| 200 | #define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id) |
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| 201 | #define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id) |
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| 202 | #define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id) |
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| 203 | #define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id) |
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| 204 | #define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id) |
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| 205 | #define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \ |
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| 206 | LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id) |
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| 207 | |
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| 208 | #define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \ |
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| 209 | (is_rxtx_cdc_dma_port(dai_id) ? \ |
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| 210 | (v->rxtx_wrdma_reg_base + (addr) + \ |
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| 211 | v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \ |
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| 212 | (v->va_wrdma_reg_base + (addr) + \ |
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| 213 | v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start))) |
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| 214 | |
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| 215 | #define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \ |
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| 216 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id) |
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| 217 | #define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \ |
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| 218 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id) |
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| 219 | #define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \ |
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| 220 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id) |
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| 221 | #define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \ |
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| 222 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id) |
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| 223 | #define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \ |
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| 224 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id) |
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| 225 | #define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \ |
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| 226 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id) |
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| 227 | |
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| 228 | #define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \ |
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| 229 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id) |
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| 230 | #define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \ |
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| 231 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id) |
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| 232 | #define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \ |
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| 233 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id) |
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| 234 | #define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \ |
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| 235 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id) |
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| 236 | #define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \ |
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| 237 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id) |
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| 238 | #define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \ |
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| 239 | LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id) |
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| 240 | |
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| 241 | #define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \ |
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| 242 | (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \ |
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| 243 | LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id)) |
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| 244 | |
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| 245 | #define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \ |
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| 246 | (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \ |
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| 247 | LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id)) |
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| 248 | |
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| 249 | #define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \ |
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| 250 | ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \ |
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| 251 | __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \ |
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| 252 | __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id)) |
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| 253 | |
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| 254 | #define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \ |
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| 255 | ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \ |
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| 256 | LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \ |
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| 257 | LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id)) |
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| 258 | |
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| 259 | #define LPAIF_INTF_REG(v, chan, dir, dai_id) \ |
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| 260 | (is_cdc_dma_port(dai_id) ? \ |
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| 261 | LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \ |
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| 262 | LPAIF_DMACTL_REG(v, chan, dir, dai_id)) |
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| 263 | |
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| 264 | #define LPAIF_DMACTL_BURSTEN_SINGLE 0 |
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| 265 | #define LPAIF_DMACTL_BURSTEN_INCR4 1 |
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| 266 | |
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| 267 | #define LPAIF_DMACTL_WPSCNT_ONE 0 |
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| 268 | #define LPAIF_DMACTL_WPSCNT_TWO 1 |
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| 269 | #define LPAIF_DMACTL_WPSCNT_THREE 2 |
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| 270 | #define LPAIF_DMACTL_WPSCNT_FOUR 3 |
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| 271 | #define LPAIF_DMACTL_WPSCNT_SIX 5 |
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| 272 | #define LPAIF_DMACTL_WPSCNT_EIGHT 7 |
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| 273 | #define LPAIF_DMACTL_WPSCNT_TEN 9 |
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| 274 | #define LPAIF_DMACTL_WPSCNT_TWELVE 11 |
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| 275 | #define LPAIF_DMACTL_WPSCNT_FOURTEEN 13 |
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| 276 | #define LPAIF_DMACTL_WPSCNT_SIXTEEN 15 |
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| 277 | |
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| 278 | #define LPAIF_DMACTL_AUDINTF(id) id |
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| 279 | |
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| 280 | #define LPAIF_DMACTL_FIFOWM_1 0 |
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| 281 | #define LPAIF_DMACTL_FIFOWM_2 1 |
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| 282 | #define LPAIF_DMACTL_FIFOWM_3 2 |
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| 283 | #define LPAIF_DMACTL_FIFOWM_4 3 |
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| 284 | #define LPAIF_DMACTL_FIFOWM_5 4 |
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| 285 | #define LPAIF_DMACTL_FIFOWM_6 5 |
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| 286 | #define LPAIF_DMACTL_FIFOWM_7 6 |
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| 287 | #define LPAIF_DMACTL_FIFOWM_8 7 |
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| 288 | #define LPAIF_DMACTL_FIFOWM_9 8 |
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| 289 | #define LPAIF_DMACTL_FIFOWM_10 9 |
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| 290 | #define LPAIF_DMACTL_FIFOWM_11 10 |
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| 291 | #define LPAIF_DMACTL_FIFOWM_12 11 |
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| 292 | #define LPAIF_DMACTL_FIFOWM_13 12 |
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| 293 | #define LPAIF_DMACTL_FIFOWM_14 13 |
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| 294 | #define LPAIF_DMACTL_FIFOWM_15 14 |
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| 295 | #define LPAIF_DMACTL_FIFOWM_16 15 |
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| 296 | #define LPAIF_DMACTL_FIFOWM_17 16 |
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| 297 | #define LPAIF_DMACTL_FIFOWM_18 17 |
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| 298 | #define LPAIF_DMACTL_FIFOWM_19 18 |
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| 299 | #define LPAIF_DMACTL_FIFOWM_20 19 |
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| 300 | #define LPAIF_DMACTL_FIFOWM_21 20 |
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| 301 | #define LPAIF_DMACTL_FIFOWM_22 21 |
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| 302 | #define LPAIF_DMACTL_FIFOWM_23 22 |
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| 303 | #define LPAIF_DMACTL_FIFOWM_24 23 |
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| 304 | #define LPAIF_DMACTL_FIFOWM_25 24 |
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| 305 | #define LPAIF_DMACTL_FIFOWM_26 25 |
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| 306 | #define LPAIF_DMACTL_FIFOWM_27 26 |
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| 307 | #define LPAIF_DMACTL_FIFOWM_28 27 |
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| 308 | #define LPAIF_DMACTL_FIFOWM_29 28 |
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| 309 | #define LPAIF_DMACTL_FIFOWM_30 29 |
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| 310 | #define LPAIF_DMACTL_FIFOWM_31 30 |
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| 311 | #define LPAIF_DMACTL_FIFOWM_32 31 |
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| 312 | |
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| 313 | #define LPAIF_DMACTL_ENABLE_OFF 0 |
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| 314 | #define LPAIF_DMACTL_ENABLE_ON 1 |
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| 315 | |
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| 316 | #define LPAIF_DMACTL_DYNCLK_OFF 0 |
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| 317 | #define LPAIF_DMACTL_DYNCLK_ON 1 |
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| 318 | |
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| 319 | #endif /* __LPASS_LPAIF_REG_H__ */ |
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| 320 | |
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