| 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
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| 2 | /* |
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| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
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| 4 | * redistributing this file, you may do so under either license. |
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| 5 | * |
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| 6 | * Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved. |
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| 7 | * |
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| 8 | * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _ACP_DSP_IP_OFFSET_H |
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| 12 | #define _ACP_DSP_IP_OFFSET_H |
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| 13 | |
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| 14 | /* Registers from ACP_DMA_0 block */ |
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| 15 | #define ACP_DMA_CNTL_0 0x00 |
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| 16 | #define ACP_DMA_DSCR_STRT_IDX_0 0x20 |
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| 17 | #define ACP_DMA_DSCR_CNT_0 0x40 |
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| 18 | #define ACP_DMA_PRIO_0 0x60 |
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| 19 | #define ACP_DMA_CUR_DSCR_0 0x80 |
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| 20 | #define ACP_DMA_ERR_STS_0 0xC0 |
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| 21 | #define ACP_DMA_DESC_BASE_ADDR 0xE0 |
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| 22 | #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4 |
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| 23 | #define ACP_DMA_CH_STS 0xE8 |
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| 24 | #define ACP_DMA_CH_GROUP 0xEC |
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| 25 | #define ACP_DMA_CH_RST_STS 0xF0 |
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| 26 | #define ACP70_DMA_CNTL_0 0x00 |
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| 27 | #define ACP70_DMA_DSCR_STRT_IDX_0 0x28 |
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| 28 | #define ACP70_DMA_DSCR_CNT_0 0x50 |
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| 29 | #define ACP70_DMA_PRIO_0 0x78 |
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| 30 | #define ACP70_DMA_CUR_DSCR_0 0xA0 |
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| 31 | #define ACP70_DMA_ERR_STS_0 0xF0 |
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| 32 | #define ACP70_DMA_DESC_BASE_ADDR 0x118 |
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| 33 | #define ACP70_DMA_DESC_MAX_NUM_DSCR 0x11C |
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| 34 | #define ACP70_DMA_CH_STS 0x120 |
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| 35 | #define ACP70_DMA_CH_GROUP 0x124 |
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| 36 | #define ACP70_DMA_CH_RST_STS 0x128 |
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| 37 | |
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| 38 | /* Registers from ACP_DSP_0 block */ |
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| 39 | #define ACP_DSP0_RUNSTALL 0x414 |
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| 40 | |
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| 41 | /* Registers from ACP_AXI2AXIATU block */ |
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| 42 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC00 |
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| 43 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC04 |
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| 44 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC08 |
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| 45 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C |
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| 46 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0xC10 |
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| 47 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0xC14 |
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| 48 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0xC18 |
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| 49 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0xC1C |
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| 50 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20 |
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| 51 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24 |
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| 52 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0xC28 |
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| 53 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0xC2C |
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| 54 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0xC30 |
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| 55 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0xC34 |
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| 56 | #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0xC38 |
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| 57 | #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0xC3C |
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| 58 | #define ACPAXI2AXI_ATU_CTRL 0xC40 |
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| 59 | #define ACP_SOFT_RESET 0x1000 |
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| 60 | #define ACP_CONTROL 0x1004 |
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| 61 | |
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| 62 | #define ACP3X_I2S_PIN_CONFIG 0x1400 |
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| 63 | #define ACP5X_I2S_PIN_CONFIG 0x1400 |
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| 64 | #define ACP6X_I2S_PIN_CONFIG 0x1440 |
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| 65 | |
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| 66 | /* Registers offsets from ACP_PGFSM block */ |
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| 67 | #define ACP3X_PGFSM_BASE 0x141C |
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| 68 | #define ACP5X_PGFSM_BASE 0x1424 |
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| 69 | #define ACP6X_PGFSM_BASE 0x1024 |
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| 70 | #define ACP70_PGFSM_BASE ACP6X_PGFSM_BASE |
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| 71 | #define PGFSM_CONTROL_OFFSET 0x0 |
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| 72 | #define PGFSM_STATUS_OFFSET 0x4 |
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| 73 | #define ACP3X_CLKMUX_SEL 0x1424 |
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| 74 | #define ACP5X_CLKMUX_SEL 0x142C |
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| 75 | #define ACP6X_CLKMUX_SEL 0x102C |
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| 76 | #define ACP70_CLKMUX_SEL ACP6X_CLKMUX_SEL |
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| 77 | |
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| 78 | /* Registers from ACP_INTR block */ |
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| 79 | #define ACP3X_EXT_INTR_STAT 0x1808 |
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| 80 | #define ACP5X_EXT_INTR_STAT 0x1808 |
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| 81 | #define ACP6X_EXTERNAL_INTR_ENB 0x1A00 |
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| 82 | #define ACP6X_EXTERNAL_INTR_CNTL 0x1A04 |
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| 83 | #define ACP6X_EXT_INTR_STAT 0x1A0C |
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| 84 | #define ACP6X_EXT_INTR_STAT1 0x1A10 |
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| 85 | #define ACP70_EXTERNAL_INTR_ENB ACP6X_EXTERNAL_INTR_ENB |
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| 86 | #define ACP70_EXTERNAL_INTR_CNTL ACP6X_EXTERNAL_INTR_CNTL |
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| 87 | #define ACP70_EXT_INTR_STAT ACP6X_EXT_INTR_STAT |
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| 88 | #define ACP70_EXT_INTR_STAT1 ACP6X_EXT_INTR_STAT1 |
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| 89 | |
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| 90 | #define ACP3X_DSP_SW_INTR_BASE 0x1814 |
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| 91 | #define ACP5X_DSP_SW_INTR_BASE 0x1814 |
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| 92 | #define ACP6X_DSP_SW_INTR_BASE 0x1808 |
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| 93 | #define ACP70_DSP_SW_INTR_BASE ACP6X_DSP_SW_INTR_BASE |
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| 94 | #define DSP_SW_INTR_CNTL_OFFSET 0x0 |
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| 95 | #define DSP_SW_INTR_STAT_OFFSET 0x4 |
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| 96 | #define DSP_SW_INTR_TRIG_OFFSET 0x8 |
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| 97 | #define ACP3X_ERROR_STATUS 0x18C4 |
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| 98 | #define ACP6X_ERROR_STATUS 0x1A4C |
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| 99 | #define ACP70_ERROR_STATUS ACP6X_ERROR_STATUS |
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| 100 | #define ACP3X_AXI2DAGB_SEM_0 0x1880 |
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| 101 | #define ACP5X_AXI2DAGB_SEM_0 0x1884 |
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| 102 | #define ACP6X_AXI2DAGB_SEM_0 0x1874 |
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| 103 | #define ACP70_AXI2DAGB_SEM_0 ACP6X_AXI2DAGB_SEM_0 |
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| 104 | |
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| 105 | /* ACP common registers to report errors related to I2S & SoundWire interfaces */ |
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| 106 | #define ACP3X_SW_I2S_ERROR_REASON 0x18C8 |
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| 107 | #define ACP6X_SW0_I2S_ERROR_REASON 0x18B4 |
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| 108 | #define ACP7X_SW0_I2S_ERROR_REASON ACP6X_SW0_I2S_ERROR_REASON |
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| 109 | #define ACP_SW1_I2S_ERROR_REASON 0x1A50 |
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| 110 | |
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| 111 | /* Registers from ACP_SHA block */ |
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| 112 | #define ACP_SHA_DSP_FW_QUALIFIER 0x1C70 |
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| 113 | #define ACP_SHA_DMA_CMD 0x1CB0 |
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| 114 | #define ACP_SHA_MSG_LENGTH 0x1CB4 |
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| 115 | #define ACP_SHA_DMA_STRT_ADDR 0x1CB8 |
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| 116 | #define ACP_SHA_DMA_DESTINATION_ADDR 0x1CBC |
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| 117 | #define ACP_SHA_DMA_CMD_STS 0x1CC0 |
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| 118 | #define ACP_SHA_DMA_ERR_STATUS 0x1CC4 |
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| 119 | #define ACP_SHA_TRANSFER_BYTE_CNT 0x1CC8 |
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| 120 | #define ACP_SHA_DMA_INCLUDE_HDR 0x1CCC |
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| 121 | #define ACP_SHA_PSP_ACK 0x1C74 |
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| 122 | |
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| 123 | #define ACP_SCRATCH_REG_0 0x10000 |
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| 124 | #define ACP6X_DSP_FUSION_RUNSTALL 0x0644 |
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| 125 | #define ACP70_DSP_FUSION_RUNSTALL ACP6X_DSP_FUSION_RUNSTALL |
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| 126 | |
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| 127 | /* Cache window registers */ |
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| 128 | #define ACP_DSP0_CACHE_OFFSET0 0x0420 |
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| 129 | #define ACP_DSP0_CACHE_SIZE0 0x0424 |
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| 130 | |
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| 131 | #define ACP_SW0_EN 0x3000 |
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| 132 | #define ACP_SW1_EN 0x3C00 |
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| 133 | #define ACP70_PME_EN 0x1400 |
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| 134 | #define ACP70_EXTERNAL_INTR_CNTL1 0x1A08 |
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| 135 | #define ACP70_SW0_WAKE_EN 0x1458 |
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| 136 | #define ACP70_SW1_WAKE_EN 0x1460 |
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| 137 | #define ACP70_SDW_HOST_WAKE_MASK 0x0C00000 |
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| 138 | #define ACP70_SDW0_HOST_WAKE_STAT BIT(24) |
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| 139 | #define ACP70_SDW1_HOST_WAKE_STAT BIT(25) |
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| 140 | #define ACP70_SDW0_PME_STAT BIT(26) |
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| 141 | #define ACP70_SDW1_PME_STAT BIT(27) |
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| 142 | |
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| 143 | #endif |
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| 144 | |
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