1 | //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// |
---|---|
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file declares PPC TargetInfo objects. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H |
14 | #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H |
15 | |
16 | #include "OSTargets.h" |
17 | #include "clang/Basic/TargetInfo.h" |
18 | #include "clang/Basic/TargetOptions.h" |
19 | #include "llvm/ADT/StringSwitch.h" |
20 | #include "llvm/Support/Compiler.h" |
21 | #include "llvm/TargetParser/Triple.h" |
22 | |
23 | namespace clang { |
24 | namespace targets { |
25 | |
26 | // PPC abstract base class |
27 | class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { |
28 | |
29 | /// Flags for architecture specific defines. |
30 | typedef enum { |
31 | ArchDefineNone = 0, |
32 | ArchDefineName = 1 << 0, // <name> is substituted for arch name. |
33 | ArchDefinePpcgr = 1 << 1, |
34 | ArchDefinePpcsq = 1 << 2, |
35 | ArchDefine440 = 1 << 3, |
36 | ArchDefine603 = 1 << 4, |
37 | ArchDefine604 = 1 << 5, |
38 | ArchDefinePwr4 = 1 << 6, |
39 | ArchDefinePwr5 = 1 << 7, |
40 | ArchDefinePwr5x = 1 << 8, |
41 | ArchDefinePwr6 = 1 << 9, |
42 | ArchDefinePwr6x = 1 << 10, |
43 | ArchDefinePwr7 = 1 << 11, |
44 | ArchDefinePwr8 = 1 << 12, |
45 | ArchDefinePwr9 = 1 << 13, |
46 | ArchDefinePwr10 = 1 << 14, |
47 | ArchDefinePwr11 = 1 << 15, |
48 | ArchDefineFuture = 1 << 16, |
49 | ArchDefineA2 = 1 << 17, |
50 | ArchDefineE500 = 1 << 18 |
51 | } ArchDefineTypes; |
52 | |
53 | ArchDefineTypes ArchDefs = ArchDefineNone; |
54 | static const char *const GCCRegNames[]; |
55 | static const TargetInfo::GCCRegAlias GCCRegAliases[]; |
56 | std::string CPU; |
57 | enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; |
58 | |
59 | // Target cpu features. |
60 | bool HasAltivec = false; |
61 | bool HasMMA = false; |
62 | bool HasROPProtect = false; |
63 | bool HasVSX = false; |
64 | bool HasP8Vector = false; |
65 | bool HasP8Crypto = false; |
66 | bool HasHTM = false; |
67 | bool HasP9Vector = false; |
68 | bool HasSPE = false; |
69 | bool HasFrsqrte = false; |
70 | bool HasFrsqrtes = false; |
71 | bool HasP10Vector = false; |
72 | bool HasPCRelativeMemops = false; |
73 | bool HasQuadwordAtomics = false; |
74 | bool UseLongCalls = false; |
75 | |
76 | protected: |
77 | std::string ABI; |
78 | |
79 | public: |
80 | PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) |
81 | : TargetInfo(Triple) { |
82 | SuitableAlign = 128; |
83 | LongDoubleWidth = LongDoubleAlign = 128; |
84 | LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); |
85 | HasStrictFP = true; |
86 | HasIbm128 = true; |
87 | HasUnalignedAccess = true; |
88 | } |
89 | |
90 | // Set the language option for altivec based on our value. |
91 | void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override; |
92 | |
93 | // Note: GCC recognizes the following additional cpus: |
94 | // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, |
95 | // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. |
96 | bool isValidCPUName(StringRef Name) const override; |
97 | void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; |
98 | |
99 | bool setCPU(const std::string &Name) override { |
100 | bool CPUKnown = isValidCPUName(Name); |
101 | if (CPUKnown) { |
102 | CPU = Name; |
103 | |
104 | // CPU identification. |
105 | ArchDefs = |
106 | (ArchDefineTypes)llvm::StringSwitch<int>(CPU) |
107 | .Case(S: "440", Value: ArchDefineName) |
108 | .Case(S: "450", Value: ArchDefineName | ArchDefine440) |
109 | .Case(S: "601", Value: ArchDefineName) |
110 | .Case(S: "602", Value: ArchDefineName | ArchDefinePpcgr) |
111 | .Case(S: "603", Value: ArchDefineName | ArchDefinePpcgr) |
112 | .Case(S: "603e", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr) |
113 | .Case(S: "603ev", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr) |
114 | .Case(S: "604", Value: ArchDefineName | ArchDefinePpcgr) |
115 | .Case(S: "604e", Value: ArchDefineName | ArchDefine604 | ArchDefinePpcgr) |
116 | .Case(S: "620", Value: ArchDefineName | ArchDefinePpcgr) |
117 | .Case(S: "630", Value: ArchDefineName | ArchDefinePpcgr) |
118 | .Case(S: "7400", Value: ArchDefineName | ArchDefinePpcgr) |
119 | .Case(S: "7450", Value: ArchDefineName | ArchDefinePpcgr) |
120 | .Case(S: "750", Value: ArchDefineName | ArchDefinePpcgr) |
121 | .Case(S: "970", Value: ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | |
122 | ArchDefinePpcsq) |
123 | .Case(S: "a2", Value: ArchDefineA2) |
124 | .Cases(S0: "power3", S1: "pwr3", Value: ArchDefinePpcgr) |
125 | .Cases(S0: "power4", S1: "pwr4", |
126 | Value: ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) |
127 | .Cases(S0: "power5", S1: "pwr5", |
128 | Value: ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | |
129 | ArchDefinePpcsq) |
130 | .Cases(S0: "power5x", S1: "pwr5x", |
131 | Value: ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | |
132 | ArchDefinePpcgr | ArchDefinePpcsq) |
133 | .Cases(S0: "power6", S1: "pwr6", |
134 | Value: ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | |
135 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) |
136 | .Cases(S0: "power6x", S1: "pwr6x", |
137 | Value: ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | |
138 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | |
139 | ArchDefinePpcsq) |
140 | .Cases(S0: "power7", S1: "pwr7", |
141 | Value: ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | |
142 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | |
143 | ArchDefinePpcsq) |
144 | // powerpc64le automatically defaults to at least power8. |
145 | .Cases(S0: "power8", S1: "pwr8", S2: "ppc64le", |
146 | Value: ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | |
147 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | |
148 | ArchDefinePpcgr | ArchDefinePpcsq) |
149 | .Cases(S0: "power9", S1: "pwr9", |
150 | Value: ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | |
151 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | |
152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) |
153 | .Cases(S0: "power10", S1: "pwr10", |
154 | Value: ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | |
155 | ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | |
156 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | |
157 | ArchDefinePpcsq) |
158 | .Cases(S0: "power11", S1: "pwr11", |
159 | Value: ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 | |
160 | ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | |
161 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | |
162 | ArchDefinePpcgr | ArchDefinePpcsq) |
163 | .Case(S: "future", |
164 | Value: ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 | |
165 | ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | |
166 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | |
167 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) |
168 | .Cases(S0: "8548", S1: "e500", Value: ArchDefineE500) |
169 | .Default(Value: ArchDefineNone); |
170 | } |
171 | return CPUKnown; |
172 | } |
173 | |
174 | StringRef getABI() const override { return ABI; } |
175 | |
176 | llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override; |
177 | |
178 | bool isCLZForZeroUndef() const override { return false; } |
179 | |
180 | void getTargetDefines(const LangOptions &Opts, |
181 | MacroBuilder &Builder) const override; |
182 | |
183 | bool |
184 | initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, |
185 | StringRef CPU, |
186 | const std::vector<std::string> &FeaturesVec) const override; |
187 | |
188 | void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; |
189 | void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const; |
190 | void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; |
191 | |
192 | bool handleTargetFeatures(std::vector<std::string> &Features, |
193 | DiagnosticsEngine &Diags) override; |
194 | |
195 | bool hasFeature(StringRef Feature) const override; |
196 | |
197 | void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, |
198 | bool Enabled) const override; |
199 | |
200 | bool supportsTargetAttributeTune() const override { return true; } |
201 | |
202 | ArrayRef<const char *> getGCCRegNames() const override; |
203 | |
204 | ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; |
205 | |
206 | ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; |
207 | |
208 | bool validateAsmConstraint(const char *&Name, |
209 | TargetInfo::ConstraintInfo &Info) const override { |
210 | switch (*Name) { |
211 | default: |
212 | return false; |
213 | case 'O': // Zero |
214 | break; |
215 | case 'f': // Floating point register |
216 | // Don't use floating point registers on soft float ABI. |
217 | if (FloatABI == SoftFloat) |
218 | return false; |
219 | [[fallthrough]]; |
220 | case 'b': // Base register |
221 | Info.setAllowsRegister(); |
222 | break; |
223 | // FIXME: The following are added to allow parsing. |
224 | // I just took a guess at what the actions should be. |
225 | // Also, is more specific checking needed? I.e. specific registers? |
226 | case 'd': // Floating point register (containing 64-bit value) |
227 | case 'v': // Altivec vector register |
228 | // Don't use floating point and altivec vector registers |
229 | // on soft float ABI |
230 | if (FloatABI == SoftFloat) |
231 | return false; |
232 | Info.setAllowsRegister(); |
233 | break; |
234 | case 'w': |
235 | switch (Name[1]) { |
236 | case 'd': // VSX vector register to hold vector double data |
237 | case 'f': // VSX vector register to hold vector float data |
238 | case 's': // VSX vector register to hold scalar double data |
239 | case 'w': // VSX vector register to hold scalar double data |
240 | case 'a': // Any VSX register |
241 | case 'c': // An individual CR bit |
242 | case 'i': // FP or VSX register to hold 64-bit integers data |
243 | break; |
244 | default: |
245 | return false; |
246 | } |
247 | Info.setAllowsRegister(); |
248 | Name++; // Skip over 'w'. |
249 | break; |
250 | case 'h': // `MQ', `CTR', or `LINK' register |
251 | case 'q': // `MQ' register |
252 | case 'c': // `CTR' register |
253 | case 'l': // `LINK' register |
254 | case 'x': // `CR' register (condition register) number 0 |
255 | case 'y': // `CR' register (condition register) |
256 | case 'z': // `XER[CA]' carry bit (part of the XER register) |
257 | Info.setAllowsRegister(); |
258 | break; |
259 | case 'I': // Signed 16-bit constant |
260 | case 'J': // Unsigned 16-bit constant shifted left 16 bits |
261 | // (use `L' instead for SImode constants) |
262 | case 'K': // Unsigned 16-bit constant |
263 | case 'L': // Signed 16-bit constant shifted left 16 bits |
264 | case 'M': // Constant larger than 31 |
265 | case 'N': // Exact power of 2 |
266 | case 'P': // Constant whose negation is a signed 16-bit constant |
267 | case 'G': // Floating point constant that can be loaded into a |
268 | // register with one instruction per word |
269 | case 'H': // Integer/Floating point constant that can be loaded |
270 | // into a register using three instructions |
271 | break; |
272 | case 'm': // Memory operand. Note that on PowerPC targets, m can |
273 | // include addresses that update the base register. It |
274 | // is therefore only safe to use `m' in an asm statement |
275 | // if that asm statement accesses the operand exactly once. |
276 | // The asm statement must also use `%U<opno>' as a |
277 | // placeholder for the "update" flag in the corresponding |
278 | // load or store instruction. For example: |
279 | // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); |
280 | // is correct but: |
281 | // asm ("st %1,%0" : "=m" (mem) : "r" (val)); |
282 | // is not. Use es rather than m if you don't want the base |
283 | // register to be updated. |
284 | case 'e': |
285 | if (Name[1] != 's') |
286 | return false; |
287 | // es: A "stable" memory operand; that is, one which does not |
288 | // include any automodification of the base register. Unlike |
289 | // `m', this constraint can be used in asm statements that |
290 | // might access the operand several times, or that might not |
291 | // access it at all. |
292 | Info.setAllowsMemory(); |
293 | Name++; // Skip over 'e'. |
294 | break; |
295 | case 'Q': // Memory operand that is an offset from a register (it is |
296 | // usually better to use `m' or `es' in asm statements) |
297 | Info.setAllowsRegister(); |
298 | [[fallthrough]]; |
299 | case 'Z': // Memory operand that is an indexed or indirect from a |
300 | // register (it is usually better to use `m' or `es' in |
301 | // asm statements) |
302 | Info.setAllowsMemory(); |
303 | break; |
304 | case 'a': // Address operand that is an indexed or indirect from a |
305 | // register (`p' is preferable for asm statements) |
306 | // TODO: Add full support for this constraint |
307 | return false; |
308 | case 'R': // AIX TOC entry |
309 | case 'S': // Constant suitable as a 64-bit mask operand |
310 | case 'T': // Constant suitable as a 32-bit mask operand |
311 | case 'U': // System V Release 4 small data area reference |
312 | case 't': // AND masks that can be performed by two rldic{l, r} |
313 | // instructions |
314 | case 'W': // Vector constant that does not require memory |
315 | case 'j': // Vector constant that is all zeros. |
316 | break; |
317 | // End FIXME. |
318 | } |
319 | return true; |
320 | } |
321 | |
322 | std::string convertConstraint(const char *&Constraint) const override { |
323 | std::string R; |
324 | switch (*Constraint) { |
325 | case 'e': |
326 | case 'w': |
327 | // Two-character constraint; add "^" hint for later parsing. |
328 | R = std::string("^") + std::string(Constraint, 2); |
329 | Constraint++; |
330 | break; |
331 | default: |
332 | return TargetInfo::convertConstraint(Constraint); |
333 | } |
334 | return R; |
335 | } |
336 | |
337 | std::string_view getClobbers() const override { return ""; } |
338 | int getEHDataRegisterNumber(unsigned RegNo) const override { |
339 | if (RegNo == 0) |
340 | return 3; |
341 | if (RegNo == 1) |
342 | return 4; |
343 | return -1; |
344 | } |
345 | |
346 | bool hasSjLjLowering() const override { return true; } |
347 | |
348 | const char *getLongDoubleMangling() const override { |
349 | if (LongDoubleWidth == 64) |
350 | return "e"; |
351 | return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() |
352 | ? "g" |
353 | : "u9__ieee128"; |
354 | } |
355 | const char *getFloat128Mangling() const override { return "u9__ieee128"; } |
356 | const char *getIbm128Mangling() const override { return "g"; } |
357 | |
358 | bool hasBitIntType() const override { return true; } |
359 | |
360 | bool isSPRegName(StringRef RegName) const override { |
361 | return RegName == "r1"|| RegName == "x1"; |
362 | } |
363 | |
364 | // We support __builtin_cpu_supports/__builtin_cpu_is on targets that |
365 | // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv. |
366 | static constexpr int MINIMUM_AIX_OS_MAJOR = 7; |
367 | static constexpr int MINIMUM_AIX_OS_MINOR = 2; |
368 | bool supportsCpuSupports() const override { |
369 | llvm::Triple Triple = getTriple(); |
370 | // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports(). |
371 | return Triple.isOSGlibc() || |
372 | (Triple.isOSAIX() && |
373 | !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR)); |
374 | } |
375 | |
376 | bool supportsCpuIs() const override { |
377 | llvm::Triple Triple = getTriple(); |
378 | // AIX 7.2 is the minimum requirement to support __builtin_cpu_is(). |
379 | return Triple.isOSGlibc() || |
380 | (Triple.isOSAIX() && |
381 | !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR)); |
382 | } |
383 | bool validateCpuSupports(StringRef Feature) const override; |
384 | bool validateCpuIs(StringRef Name) const override; |
385 | }; |
386 | |
387 | class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { |
388 | public: |
389 | PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) |
390 | : PPCTargetInfo(Triple, Opts) { |
391 | if (Triple.isOSAIX()) |
392 | resetDataLayout(DL: "E-m:a-p:32:32-Fi32-i64:64-n32"); |
393 | else if (Triple.getArch() == llvm::Triple::ppcle) |
394 | resetDataLayout(DL: "e-m:e-p:32:32-Fn32-i64:64-n32"); |
395 | else |
396 | resetDataLayout(DL: "E-m:e-p:32:32-Fn32-i64:64-n32"); |
397 | |
398 | switch (getTriple().getOS()) { |
399 | case llvm::Triple::Linux: |
400 | case llvm::Triple::FreeBSD: |
401 | case llvm::Triple::NetBSD: |
402 | SizeType = UnsignedInt; |
403 | PtrDiffType = SignedInt; |
404 | IntPtrType = SignedInt; |
405 | break; |
406 | case llvm::Triple::AIX: |
407 | SizeType = UnsignedLong; |
408 | PtrDiffType = SignedLong; |
409 | IntPtrType = SignedLong; |
410 | LongDoubleWidth = 64; |
411 | LongDoubleAlign = DoubleAlign = 32; |
412 | LongDoubleFormat = &llvm::APFloat::IEEEdouble(); |
413 | break; |
414 | default: |
415 | break; |
416 | } |
417 | |
418 | if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || |
419 | Triple.isMusl()) { |
420 | LongDoubleWidth = LongDoubleAlign = 64; |
421 | LongDoubleFormat = &llvm::APFloat::IEEEdouble(); |
422 | } |
423 | |
424 | // PPC32 supports atomics up to 4 bytes. |
425 | MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; |
426 | } |
427 | |
428 | BuiltinVaListKind getBuiltinVaListKind() const override { |
429 | // This is the ELF definition |
430 | return TargetInfo::PowerABIBuiltinVaList; |
431 | } |
432 | |
433 | std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { |
434 | return std::make_pair(x: 32, y: 32); |
435 | } |
436 | }; |
437 | |
438 | // Note: ABI differences may eventually require us to have a separate |
439 | // TargetInfo for little endian. |
440 | class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { |
441 | public: |
442 | PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) |
443 | : PPCTargetInfo(Triple, Opts) { |
444 | LongWidth = LongAlign = PointerWidth = PointerAlign = 64; |
445 | IntMaxType = SignedLong; |
446 | Int64Type = SignedLong; |
447 | std::string DataLayout; |
448 | |
449 | if (Triple.isOSAIX()) { |
450 | // TODO: Set appropriate ABI for AIX platform. |
451 | DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64"; |
452 | LongDoubleWidth = 64; |
453 | LongDoubleAlign = DoubleAlign = 32; |
454 | LongDoubleFormat = &llvm::APFloat::IEEEdouble(); |
455 | } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { |
456 | DataLayout = "e-m:e-Fn32-i64:64-i128:128-n32:64"; |
457 | ABI = "elfv2"; |
458 | } else { |
459 | DataLayout = "E-m:e"; |
460 | if (Triple.isPPC64ELFv2ABI()) { |
461 | ABI = "elfv2"; |
462 | DataLayout += "-Fn32"; |
463 | } else { |
464 | ABI = "elfv1"; |
465 | DataLayout += "-Fi64"; |
466 | } |
467 | DataLayout += "-i64:64-i128:128-n32:64"; |
468 | } |
469 | |
470 | if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { |
471 | LongDoubleWidth = LongDoubleAlign = 64; |
472 | LongDoubleFormat = &llvm::APFloat::IEEEdouble(); |
473 | } |
474 | |
475 | if (Triple.isOSAIX() || Triple.isOSLinux()) |
476 | DataLayout += "-S128-v256:256:256-v512:512:512"; |
477 | resetDataLayout(DL: DataLayout); |
478 | |
479 | // Newer PPC64 instruction sets support atomics up to 16 bytes. |
480 | MaxAtomicPromoteWidth = 128; |
481 | // Baseline PPC64 supports inlining atomics up to 8 bytes. |
482 | MaxAtomicInlineWidth = 64; |
483 | } |
484 | |
485 | void setMaxAtomicWidth() override { |
486 | // For power8 and up, backend is able to inline 16-byte atomic lock free |
487 | // code. |
488 | // TODO: We should allow AIX to inline quadword atomics in the future. |
489 | if (!getTriple().isOSAIX() && hasFeature(Feature: "quadword-atomics")) |
490 | MaxAtomicInlineWidth = 128; |
491 | } |
492 | |
493 | BuiltinVaListKind getBuiltinVaListKind() const override { |
494 | return TargetInfo::CharPtrBuiltinVaList; |
495 | } |
496 | |
497 | // PPC64 Linux-specific ABI options. |
498 | bool setABI(const std::string &Name) override { |
499 | if (Name == "elfv1"|| Name == "elfv2") { |
500 | ABI = Name; |
501 | return true; |
502 | } |
503 | return false; |
504 | } |
505 | |
506 | CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { |
507 | switch (CC) { |
508 | case CC_Swift: |
509 | return CCCR_OK; |
510 | case CC_SwiftAsync: |
511 | return CCCR_Error; |
512 | default: |
513 | return CCCR_Warning; |
514 | } |
515 | } |
516 | |
517 | std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { |
518 | return std::make_pair(x: 128, y: 128); |
519 | } |
520 | }; |
521 | |
522 | class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : |
523 | public AIXTargetInfo<PPC32TargetInfo> { |
524 | public: |
525 | using AIXTargetInfo::AIXTargetInfo; |
526 | BuiltinVaListKind getBuiltinVaListKind() const override { |
527 | return TargetInfo::CharPtrBuiltinVaList; |
528 | } |
529 | }; |
530 | |
531 | class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : |
532 | public AIXTargetInfo<PPC64TargetInfo> { |
533 | public: |
534 | using AIXTargetInfo::AIXTargetInfo; |
535 | }; |
536 | |
537 | } // namespace targets |
538 | } // namespace clang |
539 | #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H |
540 |
Definitions
- PPCTargetInfo
- PPCFloatABI
- PPCTargetInfo
- setCPU
- getABI
- isCLZForZeroUndef
- supportsTargetAttributeTune
- validateAsmConstraint
- convertConstraint
- getClobbers
- getEHDataRegisterNumber
- hasSjLjLowering
- getLongDoubleMangling
- getFloat128Mangling
- getIbm128Mangling
- hasBitIntType
- isSPRegName
- MINIMUM_AIX_OS_MAJOR
- MINIMUM_AIX_OS_MINOR
- supportsCpuSupports
- supportsCpuIs
- PPC32TargetInfo
- PPC32TargetInfo
- getBuiltinVaListKind
- hardwareInterferenceSizes
- PPC64TargetInfo
- PPC64TargetInfo
- setMaxAtomicWidth
- getBuiltinVaListKind
- setABI
- checkCallingConvention
- hardwareInterferenceSizes
- AIXPPC32TargetInfo
- getBuiltinVaListKind
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