1//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares PPC TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16#include "OSTargets.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/Triple.h"
22
23namespace clang {
24namespace targets {
25
26// PPC abstract base class
27class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29 /// Flags for architecture specific defines.
30 typedef enum {
31 ArchDefineNone = 0,
32 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefineFuture = 1 << 15,
48 ArchDefineA2 = 1 << 16,
49 ArchDefineE500 = 1 << 18
50 } ArchDefineTypes;
51
52 ArchDefineTypes ArchDefs = ArchDefineNone;
53 static const char *const GCCRegNames[];
54 static const TargetInfo::GCCRegAlias GCCRegAliases[];
55 std::string CPU;
56 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
57
58 // Target cpu features.
59 bool HasAltivec = false;
60 bool HasMMA = false;
61 bool HasROPProtect = false;
62 bool HasPrivileged = false;
63 bool HasAIXSmallLocalExecTLS = false;
64 bool HasAIXSmallLocalDynamicTLS = false;
65 bool HasVSX = false;
66 bool UseCRBits = false;
67 bool HasP8Vector = false;
68 bool HasP8Crypto = false;
69 bool HasDirectMove = false;
70 bool HasHTM = false;
71 bool HasBPERMD = false;
72 bool HasExtDiv = false;
73 bool HasP9Vector = false;
74 bool HasSPE = false;
75 bool PairedVectorMemops = false;
76 bool HasP10Vector = false;
77 bool HasPCRelativeMemops = false;
78 bool HasPrefixInstrs = false;
79 bool IsISA2_06 = false;
80 bool IsISA2_07 = false;
81 bool IsISA3_0 = false;
82 bool IsISA3_1 = false;
83 bool HasQuadwordAtomics = false;
84
85protected:
86 std::string ABI;
87
88public:
89 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
90 : TargetInfo(Triple) {
91 SuitableAlign = 128;
92 LongDoubleWidth = LongDoubleAlign = 128;
93 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
94 HasStrictFP = true;
95 HasIbm128 = true;
96 HasUnalignedAccess = true;
97 }
98
99 // Set the language option for altivec based on our value.
100 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
101
102 // Note: GCC recognizes the following additional cpus:
103 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
104 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
105 bool isValidCPUName(StringRef Name) const override;
106 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
107
108 bool setCPU(const std::string &Name) override {
109 bool CPUKnown = isValidCPUName(Name);
110 if (CPUKnown) {
111 CPU = Name;
112
113 // CPU identification.
114 ArchDefs =
115 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
116 .Case(S: "440", Value: ArchDefineName)
117 .Case(S: "450", Value: ArchDefineName | ArchDefine440)
118 .Case(S: "601", Value: ArchDefineName)
119 .Case(S: "602", Value: ArchDefineName | ArchDefinePpcgr)
120 .Case(S: "603", Value: ArchDefineName | ArchDefinePpcgr)
121 .Case(S: "603e", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
122 .Case(S: "603ev", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
123 .Case(S: "604", Value: ArchDefineName | ArchDefinePpcgr)
124 .Case(S: "604e", Value: ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
125 .Case(S: "620", Value: ArchDefineName | ArchDefinePpcgr)
126 .Case(S: "630", Value: ArchDefineName | ArchDefinePpcgr)
127 .Case(S: "7400", Value: ArchDefineName | ArchDefinePpcgr)
128 .Case(S: "7450", Value: ArchDefineName | ArchDefinePpcgr)
129 .Case(S: "750", Value: ArchDefineName | ArchDefinePpcgr)
130 .Case(S: "970", Value: ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
131 ArchDefinePpcsq)
132 .Case(S: "a2", Value: ArchDefineA2)
133 .Cases(S0: "power3", S1: "pwr3", Value: ArchDefinePpcgr)
134 .Cases(S0: "power4", S1: "pwr4",
135 Value: ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
136 .Cases(S0: "power5", S1: "pwr5",
137 Value: ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
138 ArchDefinePpcsq)
139 .Cases(S0: "power5x", S1: "pwr5x",
140 Value: ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
141 ArchDefinePpcgr | ArchDefinePpcsq)
142 .Cases(S0: "power6", S1: "pwr6",
143 Value: ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
144 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
145 .Cases(S0: "power6x", S1: "pwr6x",
146 Value: ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
147 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
148 ArchDefinePpcsq)
149 .Cases(S0: "power7", S1: "pwr7",
150 Value: ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
151 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
152 ArchDefinePpcsq)
153 // powerpc64le automatically defaults to at least power8.
154 .Cases(S0: "power8", S1: "pwr8", S2: "ppc64le",
155 Value: ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
156 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
157 ArchDefinePpcgr | ArchDefinePpcsq)
158 .Cases(S0: "power9", S1: "pwr9",
159 Value: ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
160 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
161 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
162 .Cases(S0: "power10", S1: "pwr10",
163 Value: ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
164 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
165 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
166 ArchDefinePpcsq)
167 .Case(S: "future",
168 Value: ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
169 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
170 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
171 ArchDefinePpcgr | ArchDefinePpcsq)
172 .Cases(S0: "8548", S1: "e500", Value: ArchDefineE500)
173 .Default(Value: ArchDefineNone);
174 }
175 return CPUKnown;
176 }
177
178 StringRef getABI() const override { return ABI; }
179
180 ArrayRef<Builtin::Info> getTargetBuiltins() const override;
181
182 bool isCLZForZeroUndef() const override { return false; }
183
184 void getTargetDefines(const LangOptions &Opts,
185 MacroBuilder &Builder) const override;
186
187 bool
188 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
189 StringRef CPU,
190 const std::vector<std::string> &FeaturesVec) const override;
191
192 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
193 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
194
195 bool handleTargetFeatures(std::vector<std::string> &Features,
196 DiagnosticsEngine &Diags) override;
197
198 bool hasFeature(StringRef Feature) const override;
199
200 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
201 bool Enabled) const override;
202
203 bool supportsTargetAttributeTune() const override { return true; }
204
205 ArrayRef<const char *> getGCCRegNames() const override;
206
207 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
208
209 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
210
211 bool validateAsmConstraint(const char *&Name,
212 TargetInfo::ConstraintInfo &Info) const override {
213 switch (*Name) {
214 default:
215 return false;
216 case 'O': // Zero
217 break;
218 case 'f': // Floating point register
219 // Don't use floating point registers on soft float ABI.
220 if (FloatABI == SoftFloat)
221 return false;
222 [[fallthrough]];
223 case 'b': // Base register
224 Info.setAllowsRegister();
225 break;
226 // FIXME: The following are added to allow parsing.
227 // I just took a guess at what the actions should be.
228 // Also, is more specific checking needed? I.e. specific registers?
229 case 'd': // Floating point register (containing 64-bit value)
230 case 'v': // Altivec vector register
231 // Don't use floating point and altivec vector registers
232 // on soft float ABI
233 if (FloatABI == SoftFloat)
234 return false;
235 Info.setAllowsRegister();
236 break;
237 case 'w':
238 switch (Name[1]) {
239 case 'd': // VSX vector register to hold vector double data
240 case 'f': // VSX vector register to hold vector float data
241 case 's': // VSX vector register to hold scalar double data
242 case 'w': // VSX vector register to hold scalar double data
243 case 'a': // Any VSX register
244 case 'c': // An individual CR bit
245 case 'i': // FP or VSX register to hold 64-bit integers data
246 break;
247 default:
248 return false;
249 }
250 Info.setAllowsRegister();
251 Name++; // Skip over 'w'.
252 break;
253 case 'h': // `MQ', `CTR', or `LINK' register
254 case 'q': // `MQ' register
255 case 'c': // `CTR' register
256 case 'l': // `LINK' register
257 case 'x': // `CR' register (condition register) number 0
258 case 'y': // `CR' register (condition register)
259 case 'z': // `XER[CA]' carry bit (part of the XER register)
260 Info.setAllowsRegister();
261 break;
262 case 'I': // Signed 16-bit constant
263 case 'J': // Unsigned 16-bit constant shifted left 16 bits
264 // (use `L' instead for SImode constants)
265 case 'K': // Unsigned 16-bit constant
266 case 'L': // Signed 16-bit constant shifted left 16 bits
267 case 'M': // Constant larger than 31
268 case 'N': // Exact power of 2
269 case 'P': // Constant whose negation is a signed 16-bit constant
270 case 'G': // Floating point constant that can be loaded into a
271 // register with one instruction per word
272 case 'H': // Integer/Floating point constant that can be loaded
273 // into a register using three instructions
274 break;
275 case 'm': // Memory operand. Note that on PowerPC targets, m can
276 // include addresses that update the base register. It
277 // is therefore only safe to use `m' in an asm statement
278 // if that asm statement accesses the operand exactly once.
279 // The asm statement must also use `%U<opno>' as a
280 // placeholder for the "update" flag in the corresponding
281 // load or store instruction. For example:
282 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
283 // is correct but:
284 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
285 // is not. Use es rather than m if you don't want the base
286 // register to be updated.
287 case 'e':
288 if (Name[1] != 's')
289 return false;
290 // es: A "stable" memory operand; that is, one which does not
291 // include any automodification of the base register. Unlike
292 // `m', this constraint can be used in asm statements that
293 // might access the operand several times, or that might not
294 // access it at all.
295 Info.setAllowsMemory();
296 Name++; // Skip over 'e'.
297 break;
298 case 'Q': // Memory operand that is an offset from a register (it is
299 // usually better to use `m' or `es' in asm statements)
300 Info.setAllowsRegister();
301 [[fallthrough]];
302 case 'Z': // Memory operand that is an indexed or indirect from a
303 // register (it is usually better to use `m' or `es' in
304 // asm statements)
305 Info.setAllowsMemory();
306 break;
307 case 'R': // AIX TOC entry
308 case 'a': // Address operand that is an indexed or indirect from a
309 // register (`p' is preferable for asm statements)
310 case 'S': // Constant suitable as a 64-bit mask operand
311 case 'T': // Constant suitable as a 32-bit mask operand
312 case 'U': // System V Release 4 small data area reference
313 case 't': // AND masks that can be performed by two rldic{l, r}
314 // instructions
315 case 'W': // Vector constant that does not require memory
316 case 'j': // Vector constant that is all zeros.
317 break;
318 // End FIXME.
319 }
320 return true;
321 }
322
323 std::string convertConstraint(const char *&Constraint) const override {
324 std::string R;
325 switch (*Constraint) {
326 case 'e':
327 case 'w':
328 // Two-character constraint; add "^" hint for later parsing.
329 R = std::string("^") + std::string(Constraint, 2);
330 Constraint++;
331 break;
332 default:
333 return TargetInfo::convertConstraint(Constraint);
334 }
335 return R;
336 }
337
338 std::string_view getClobbers() const override { return ""; }
339 int getEHDataRegisterNumber(unsigned RegNo) const override {
340 if (RegNo == 0)
341 return 3;
342 if (RegNo == 1)
343 return 4;
344 return -1;
345 }
346
347 bool hasSjLjLowering() const override { return true; }
348
349 const char *getLongDoubleMangling() const override {
350 if (LongDoubleWidth == 64)
351 return "e";
352 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
353 ? "g"
354 : "u9__ieee128";
355 }
356 const char *getFloat128Mangling() const override { return "u9__ieee128"; }
357 const char *getIbm128Mangling() const override { return "g"; }
358
359 bool hasBitIntType() const override { return true; }
360
361 bool isSPRegName(StringRef RegName) const override {
362 return RegName.equals(RHS: "r1") || RegName.equals(RHS: "x1");
363 }
364
365 // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
366 // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
367 static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
368 static constexpr int MINIMUM_AIX_OS_MINOR = 2;
369 bool supportsCpuSupports() const override { return getTriple().isOSGlibc(); }
370 bool supportsCpuIs() const override {
371 llvm::Triple Triple = getTriple();
372 // AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
373 return Triple.isOSGlibc() ||
374 (Triple.isOSAIX() &&
375 !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR));
376 }
377 bool validateCpuSupports(StringRef Feature) const override;
378 bool validateCpuIs(StringRef Name) const override;
379};
380
381class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
382public:
383 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
384 : PPCTargetInfo(Triple, Opts) {
385 if (Triple.isOSAIX())
386 resetDataLayout(DL: "E-m:a-p:32:32-Fi32-i64:64-n32");
387 else if (Triple.getArch() == llvm::Triple::ppcle)
388 resetDataLayout(DL: "e-m:e-p:32:32-Fn32-i64:64-n32");
389 else
390 resetDataLayout(DL: "E-m:e-p:32:32-Fn32-i64:64-n32");
391
392 switch (getTriple().getOS()) {
393 case llvm::Triple::Linux:
394 case llvm::Triple::FreeBSD:
395 case llvm::Triple::NetBSD:
396 SizeType = UnsignedInt;
397 PtrDiffType = SignedInt;
398 IntPtrType = SignedInt;
399 break;
400 case llvm::Triple::AIX:
401 SizeType = UnsignedLong;
402 PtrDiffType = SignedLong;
403 IntPtrType = SignedLong;
404 LongDoubleWidth = 64;
405 LongDoubleAlign = DoubleAlign = 32;
406 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
407 break;
408 default:
409 break;
410 }
411
412 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
413 Triple.isMusl()) {
414 LongDoubleWidth = LongDoubleAlign = 64;
415 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
416 }
417
418 // PPC32 supports atomics up to 4 bytes.
419 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
420 }
421
422 BuiltinVaListKind getBuiltinVaListKind() const override {
423 // This is the ELF definition
424 return TargetInfo::PowerABIBuiltinVaList;
425 }
426};
427
428// Note: ABI differences may eventually require us to have a separate
429// TargetInfo for little endian.
430class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
431public:
432 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
433 : PPCTargetInfo(Triple, Opts) {
434 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
435 IntMaxType = SignedLong;
436 Int64Type = SignedLong;
437 std::string DataLayout;
438
439 if (Triple.isOSAIX()) {
440 // TODO: Set appropriate ABI for AIX platform.
441 DataLayout = "E-m:a-Fi64-i64:64-n32:64";
442 LongDoubleWidth = 64;
443 LongDoubleAlign = DoubleAlign = 32;
444 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
445 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
446 DataLayout = "e-m:e-Fn32-i64:64-n32:64";
447 ABI = "elfv2";
448 } else {
449 DataLayout = "E-m:e";
450 if (Triple.isPPC64ELFv2ABI()) {
451 ABI = "elfv2";
452 DataLayout += "-Fn32";
453 } else {
454 ABI = "elfv1";
455 DataLayout += "-Fi64";
456 }
457 DataLayout += "-i64:64-n32:64";
458 }
459
460 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
461 LongDoubleWidth = LongDoubleAlign = 64;
462 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
463 }
464
465 if (Triple.isOSAIX() || Triple.isOSLinux())
466 DataLayout += "-S128-v256:256:256-v512:512:512";
467 resetDataLayout(DL: DataLayout);
468
469 // Newer PPC64 instruction sets support atomics up to 16 bytes.
470 MaxAtomicPromoteWidth = 128;
471 // Baseline PPC64 supports inlining atomics up to 8 bytes.
472 MaxAtomicInlineWidth = 64;
473 }
474
475 void setMaxAtomicWidth() override {
476 // For power8 and up, backend is able to inline 16-byte atomic lock free
477 // code.
478 // TODO: We should allow AIX to inline quadword atomics in the future.
479 if (!getTriple().isOSAIX() && hasFeature(Feature: "quadword-atomics"))
480 MaxAtomicInlineWidth = 128;
481 }
482
483 BuiltinVaListKind getBuiltinVaListKind() const override {
484 return TargetInfo::CharPtrBuiltinVaList;
485 }
486
487 // PPC64 Linux-specific ABI options.
488 bool setABI(const std::string &Name) override {
489 if (Name == "elfv1" || Name == "elfv2") {
490 ABI = Name;
491 return true;
492 }
493 return false;
494 }
495
496 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
497 switch (CC) {
498 case CC_Swift:
499 return CCCR_OK;
500 case CC_SwiftAsync:
501 return CCCR_Error;
502 default:
503 return CCCR_Warning;
504 }
505 }
506};
507
508class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
509 public AIXTargetInfo<PPC32TargetInfo> {
510public:
511 using AIXTargetInfo::AIXTargetInfo;
512 BuiltinVaListKind getBuiltinVaListKind() const override {
513 return TargetInfo::CharPtrBuiltinVaList;
514 }
515};
516
517class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
518 public AIXTargetInfo<PPC64TargetInfo> {
519public:
520 using AIXTargetInfo::AIXTargetInfo;
521};
522
523} // namespace targets
524} // namespace clang
525#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
526

source code of clang/lib/Basic/Targets/PPC.h