1//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares PPC TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15
16#include "OSTargets.h"
17#include "clang/Basic/TargetInfo.h"
18#include "clang/Basic/TargetOptions.h"
19#include "llvm/ADT/StringSwitch.h"
20#include "llvm/Support/Compiler.h"
21#include "llvm/TargetParser/Triple.h"
22
23namespace clang {
24namespace targets {
25
26// PPC abstract base class
27class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28
29 /// Flags for architecture specific defines.
30 typedef enum {
31 ArchDefineNone = 0,
32 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33 ArchDefinePpcgr = 1 << 1,
34 ArchDefinePpcsq = 1 << 2,
35 ArchDefine440 = 1 << 3,
36 ArchDefine603 = 1 << 4,
37 ArchDefine604 = 1 << 5,
38 ArchDefinePwr4 = 1 << 6,
39 ArchDefinePwr5 = 1 << 7,
40 ArchDefinePwr5x = 1 << 8,
41 ArchDefinePwr6 = 1 << 9,
42 ArchDefinePwr6x = 1 << 10,
43 ArchDefinePwr7 = 1 << 11,
44 ArchDefinePwr8 = 1 << 12,
45 ArchDefinePwr9 = 1 << 13,
46 ArchDefinePwr10 = 1 << 14,
47 ArchDefinePwr11 = 1 << 15,
48 ArchDefineFuture = 1 << 16,
49 ArchDefineA2 = 1 << 17,
50 ArchDefineE500 = 1 << 18
51 } ArchDefineTypes;
52
53 ArchDefineTypes ArchDefs = ArchDefineNone;
54 static const char *const GCCRegNames[];
55 static const TargetInfo::GCCRegAlias GCCRegAliases[];
56 std::string CPU;
57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
58
59 // Target cpu features.
60 bool HasAltivec = false;
61 bool HasMMA = false;
62 bool HasROPProtect = false;
63 bool HasVSX = false;
64 bool HasP8Vector = false;
65 bool HasP8Crypto = false;
66 bool HasHTM = false;
67 bool HasP9Vector = false;
68 bool HasSPE = false;
69 bool HasFrsqrte = false;
70 bool HasFrsqrtes = false;
71 bool HasP10Vector = false;
72 bool HasPCRelativeMemops = false;
73 bool HasQuadwordAtomics = false;
74 bool UseLongCalls = false;
75
76protected:
77 std::string ABI;
78
79public:
80 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
81 : TargetInfo(Triple) {
82 SuitableAlign = 128;
83 LongDoubleWidth = LongDoubleAlign = 128;
84 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
85 HasStrictFP = true;
86 HasIbm128 = true;
87 HasUnalignedAccess = true;
88 }
89
90 // Set the language option for altivec based on our value.
91 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,
92 const TargetInfo *Aux) override;
93
94 // Note: GCC recognizes the following additional cpus:
95 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
96 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
97 bool isValidCPUName(StringRef Name) const override;
98 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
99
100 bool setCPU(const std::string &Name) override {
101 bool CPUKnown = isValidCPUName(Name);
102 if (CPUKnown) {
103 CPU = Name;
104
105 // CPU identification.
106 ArchDefs =
107 (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
108 .Case(S: "440", Value: ArchDefineName)
109 .Case(S: "450", Value: ArchDefineName | ArchDefine440)
110 .Case(S: "601", Value: ArchDefineName)
111 .Case(S: "602", Value: ArchDefineName | ArchDefinePpcgr)
112 .Case(S: "603", Value: ArchDefineName | ArchDefinePpcgr)
113 .Case(S: "603e", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
114 .Case(S: "603ev", Value: ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
115 .Case(S: "604", Value: ArchDefineName | ArchDefinePpcgr)
116 .Case(S: "604e", Value: ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
117 .Case(S: "620", Value: ArchDefineName | ArchDefinePpcgr)
118 .Case(S: "630", Value: ArchDefineName | ArchDefinePpcgr)
119 .Case(S: "7400", Value: ArchDefineName | ArchDefinePpcgr)
120 .Case(S: "7450", Value: ArchDefineName | ArchDefinePpcgr)
121 .Case(S: "750", Value: ArchDefineName | ArchDefinePpcgr)
122 .Case(S: "970", Value: ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
123 ArchDefinePpcsq)
124 .Case(S: "a2", Value: ArchDefineA2)
125 .Cases(S0: "power3", S1: "pwr3", Value: ArchDefinePpcgr)
126 .Cases(S0: "power4", S1: "pwr4",
127 Value: ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
128 .Cases(S0: "power5", S1: "pwr5",
129 Value: ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
130 ArchDefinePpcsq)
131 .Cases(S0: "power5x", S1: "pwr5x",
132 Value: ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
133 ArchDefinePpcgr | ArchDefinePpcsq)
134 .Cases(S0: "power6", S1: "pwr6",
135 Value: ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
136 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
137 .Cases(S0: "power6x", S1: "pwr6x",
138 Value: ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
139 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
140 ArchDefinePpcsq)
141 .Cases(S0: "power7", S1: "pwr7",
142 Value: ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
143 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
144 ArchDefinePpcsq)
145 // powerpc64le automatically defaults to at least power8.
146 .Cases(S0: "power8", S1: "pwr8", S2: "ppc64le",
147 Value: ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
148 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
149 ArchDefinePpcgr | ArchDefinePpcsq)
150 .Cases(S0: "power9", S1: "pwr9",
151 Value: ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
152 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
153 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
154 .Cases(S0: "power10", S1: "pwr10",
155 Value: ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
156 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
157 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
158 ArchDefinePpcsq)
159 .Cases(S0: "power11", S1: "pwr11",
160 Value: ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 |
161 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
162 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
163 ArchDefinePpcgr | ArchDefinePpcsq)
164 .Case(S: "future",
165 Value: ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 |
166 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
167 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
168 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
169 .Cases(S0: "8548", S1: "e500", Value: ArchDefineE500)
170 .Default(Value: ArchDefineNone);
171 }
172 return CPUKnown;
173 }
174
175 StringRef getABI() const override { return ABI; }
176
177 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
178
179 bool isCLZForZeroUndef() const override { return false; }
180
181 void getTargetDefines(const LangOptions &Opts,
182 MacroBuilder &Builder) const override;
183
184 bool
185 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
186 StringRef CPU,
187 const std::vector<std::string> &FeaturesVec) const override;
188
189 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
190 void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const;
191 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
192
193 bool handleTargetFeatures(std::vector<std::string> &Features,
194 DiagnosticsEngine &Diags) override;
195
196 bool hasFeature(StringRef Feature) const override;
197
198 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
199 bool Enabled) const override;
200
201 bool supportsTargetAttributeTune() const override { return true; }
202
203 ArrayRef<const char *> getGCCRegNames() const override;
204
205 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
206
207 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
208
209 bool validateAsmConstraint(const char *&Name,
210 TargetInfo::ConstraintInfo &Info) const override {
211 switch (*Name) {
212 default:
213 return false;
214 case 'O': // Zero
215 break;
216 case 'f': // Floating point register
217 // Don't use floating point registers on soft float ABI.
218 if (FloatABI == SoftFloat)
219 return false;
220 [[fallthrough]];
221 case 'b': // Base register
222 Info.setAllowsRegister();
223 break;
224 // FIXME: The following are added to allow parsing.
225 // I just took a guess at what the actions should be.
226 // Also, is more specific checking needed? I.e. specific registers?
227 case 'd': // Floating point register (containing 64-bit value)
228 case 'v': // Altivec vector register
229 // Don't use floating point and altivec vector registers
230 // on soft float ABI
231 if (FloatABI == SoftFloat)
232 return false;
233 Info.setAllowsRegister();
234 break;
235 case 'w':
236 switch (Name[1]) {
237 case 'd': // VSX vector register to hold vector double data
238 case 'f': // VSX vector register to hold vector float data
239 case 's': // VSX vector register to hold scalar double data
240 case 'w': // VSX vector register to hold scalar double data
241 case 'a': // Any VSX register
242 case 'c': // An individual CR bit
243 case 'i': // FP or VSX register to hold 64-bit integers data
244 break;
245 default:
246 return false;
247 }
248 Info.setAllowsRegister();
249 Name++; // Skip over 'w'.
250 break;
251 case 'h': // `MQ', `CTR', or `LINK' register
252 case 'q': // `MQ' register
253 case 'c': // `CTR' register
254 case 'l': // `LINK' register
255 case 'x': // `CR' register (condition register) number 0
256 case 'y': // `CR' register (condition register)
257 case 'z': // `XER[CA]' carry bit (part of the XER register)
258 Info.setAllowsRegister();
259 break;
260 case 'I': // Signed 16-bit constant
261 case 'J': // Unsigned 16-bit constant shifted left 16 bits
262 // (use `L' instead for SImode constants)
263 case 'K': // Unsigned 16-bit constant
264 case 'L': // Signed 16-bit constant shifted left 16 bits
265 case 'M': // Constant larger than 31
266 case 'N': // Exact power of 2
267 case 'P': // Constant whose negation is a signed 16-bit constant
268 case 'G': // Floating point constant that can be loaded into a
269 // register with one instruction per word
270 case 'H': // Integer/Floating point constant that can be loaded
271 // into a register using three instructions
272 break;
273 case 'm': // Memory operand. Note that on PowerPC targets, m can
274 // include addresses that update the base register. It
275 // is therefore only safe to use `m' in an asm statement
276 // if that asm statement accesses the operand exactly once.
277 // The asm statement must also use `%U<opno>' as a
278 // placeholder for the "update" flag in the corresponding
279 // load or store instruction. For example:
280 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
281 // is correct but:
282 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
283 // is not. Use es rather than m if you don't want the base
284 // register to be updated.
285 case 'e':
286 if (Name[1] != 's')
287 return false;
288 // es: A "stable" memory operand; that is, one which does not
289 // include any automodification of the base register. Unlike
290 // `m', this constraint can be used in asm statements that
291 // might access the operand several times, or that might not
292 // access it at all.
293 Info.setAllowsMemory();
294 Name++; // Skip over 'e'.
295 break;
296 case 'Q': // Memory operand that is an offset from a register (it is
297 // usually better to use `m' or `es' in asm statements)
298 Info.setAllowsRegister();
299 [[fallthrough]];
300 case 'Z': // Memory operand that is an indexed or indirect from a
301 // register (it is usually better to use `m' or `es' in
302 // asm statements)
303 Info.setAllowsMemory();
304 break;
305 case 'a': // Address operand that is an indexed or indirect from a
306 // register (`p' is preferable for asm statements)
307 // TODO: Add full support for this constraint
308 return false;
309 case 'R': // AIX TOC entry
310 case 'S': // Constant suitable as a 64-bit mask operand
311 case 'T': // Constant suitable as a 32-bit mask operand
312 case 'U': // System V Release 4 small data area reference
313 case 't': // AND masks that can be performed by two rldic{l, r}
314 // instructions
315 case 'W': // Vector constant that does not require memory
316 case 'j': // Vector constant that is all zeros.
317 break;
318 // End FIXME.
319 }
320 return true;
321 }
322
323 std::string convertConstraint(const char *&Constraint) const override {
324 std::string R;
325 switch (*Constraint) {
326 case 'e':
327 case 'w':
328 // Two-character constraint; add "^" hint for later parsing.
329 R = std::string("^") + std::string(Constraint, 2);
330 Constraint++;
331 break;
332 default:
333 return TargetInfo::convertConstraint(Constraint);
334 }
335 return R;
336 }
337
338 std::string_view getClobbers() const override { return ""; }
339 int getEHDataRegisterNumber(unsigned RegNo) const override {
340 if (RegNo == 0)
341 return 3;
342 if (RegNo == 1)
343 return 4;
344 return -1;
345 }
346
347 bool hasSjLjLowering() const override { return true; }
348
349 const char *getLongDoubleMangling() const override {
350 if (LongDoubleWidth == 64)
351 return "e";
352 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
353 ? "g"
354 : "u9__ieee128";
355 }
356 const char *getFloat128Mangling() const override { return "u9__ieee128"; }
357 const char *getIbm128Mangling() const override { return "g"; }
358
359 bool hasBitIntType() const override { return true; }
360
361 bool isSPRegName(StringRef RegName) const override {
362 return RegName == "r1" || RegName == "x1";
363 }
364
365 // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
366 // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
367 static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
368 static constexpr int MINIMUM_AIX_OS_MINOR = 2;
369 bool supportsCpuSupports() const override {
370 llvm::Triple Triple = getTriple();
371 // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports().
372 return Triple.isOSGlibc() ||
373 (Triple.isOSAIX() &&
374 !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR));
375 }
376
377 bool supportsCpuIs() const override {
378 llvm::Triple Triple = getTriple();
379 // AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
380 return Triple.isOSGlibc() ||
381 (Triple.isOSAIX() &&
382 !Triple.isOSVersionLT(Major: MINIMUM_AIX_OS_MAJOR, Minor: MINIMUM_AIX_OS_MINOR));
383 }
384 bool validateCpuSupports(StringRef Feature) const override;
385 bool validateCpuIs(StringRef Name) const override;
386};
387
388class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
389public:
390 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
391 : PPCTargetInfo(Triple, Opts) {
392 if (Triple.isOSAIX())
393 resetDataLayout(DL: "E-m:a-p:32:32-Fi32-i64:64-n32");
394 else if (Triple.getArch() == llvm::Triple::ppcle)
395 resetDataLayout(DL: "e-m:e-p:32:32-Fn32-i64:64-n32");
396 else
397 resetDataLayout(DL: "E-m:e-p:32:32-Fn32-i64:64-n32");
398
399 switch (getTriple().getOS()) {
400 case llvm::Triple::Linux:
401 case llvm::Triple::FreeBSD:
402 case llvm::Triple::NetBSD:
403 SizeType = UnsignedInt;
404 PtrDiffType = SignedInt;
405 IntPtrType = SignedInt;
406 break;
407 case llvm::Triple::AIX:
408 SizeType = UnsignedLong;
409 PtrDiffType = SignedLong;
410 IntPtrType = SignedLong;
411 LongDoubleWidth = 64;
412 LongDoubleAlign = DoubleAlign = 32;
413 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
414 break;
415 default:
416 break;
417 }
418
419 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
420 Triple.isMusl()) {
421 LongDoubleWidth = LongDoubleAlign = 64;
422 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
423 }
424
425 // PPC32 supports atomics up to 4 bytes.
426 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
427 }
428
429 BuiltinVaListKind getBuiltinVaListKind() const override {
430 // This is the ELF definition
431 return TargetInfo::PowerABIBuiltinVaList;
432 }
433
434 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
435 return std::make_pair(x: 32, y: 32);
436 }
437};
438
439// Note: ABI differences may eventually require us to have a separate
440// TargetInfo for little endian.
441class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
442public:
443 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
444 : PPCTargetInfo(Triple, Opts) {
445 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
446 IntMaxType = SignedLong;
447 Int64Type = SignedLong;
448 std::string DataLayout;
449
450 if (Triple.isOSAIX()) {
451 // TODO: Set appropriate ABI for AIX platform.
452 DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64";
453 LongDoubleWidth = 64;
454 LongDoubleAlign = DoubleAlign = 32;
455 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
456 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
457 DataLayout = "e-m:e-Fn32-i64:64-i128:128-n32:64";
458 ABI = "elfv2";
459 } else {
460 DataLayout = "E-m:e";
461 if (Triple.isPPC64ELFv2ABI()) {
462 ABI = "elfv2";
463 DataLayout += "-Fn32";
464 } else {
465 ABI = "elfv1";
466 DataLayout += "-Fi64";
467 }
468 DataLayout += "-i64:64-i128:128-n32:64";
469 }
470
471 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
472 LongDoubleWidth = LongDoubleAlign = 64;
473 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
474 }
475
476 if (Triple.isOSAIX() || Triple.isOSLinux())
477 DataLayout += "-S128-v256:256:256-v512:512:512";
478 resetDataLayout(DL: DataLayout);
479
480 // Newer PPC64 instruction sets support atomics up to 16 bytes.
481 MaxAtomicPromoteWidth = 128;
482 // Baseline PPC64 supports inlining atomics up to 8 bytes.
483 MaxAtomicInlineWidth = 64;
484 }
485
486 void setMaxAtomicWidth() override {
487 // For power8 and up, backend is able to inline 16-byte atomic lock free
488 // code.
489 // TODO: We should allow AIX to inline quadword atomics in the future.
490 if (!getTriple().isOSAIX() && hasFeature(Feature: "quadword-atomics"))
491 MaxAtomicInlineWidth = 128;
492 }
493
494 BuiltinVaListKind getBuiltinVaListKind() const override {
495 return TargetInfo::CharPtrBuiltinVaList;
496 }
497
498 // PPC64 Linux-specific ABI options.
499 bool setABI(const std::string &Name) override {
500 if (Name == "elfv1" || Name == "elfv2") {
501 ABI = Name;
502 return true;
503 }
504 return false;
505 }
506
507 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
508 switch (CC) {
509 case CC_Swift:
510 return CCCR_OK;
511 case CC_SwiftAsync:
512 return CCCR_Error;
513 default:
514 return CCCR_Warning;
515 }
516 }
517
518 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
519 return std::make_pair(x: 128, y: 128);
520 }
521};
522
523class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
524 public AIXTargetInfo<PPC32TargetInfo> {
525public:
526 using AIXTargetInfo::AIXTargetInfo;
527 BuiltinVaListKind getBuiltinVaListKind() const override {
528 return TargetInfo::CharPtrBuiltinVaList;
529 }
530};
531
532class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
533 public AIXTargetInfo<PPC64TargetInfo> {
534public:
535 using AIXTargetInfo::AIXTargetInfo;
536};
537
538} // namespace targets
539} // namespace clang
540#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
541

source code of clang/lib/Basic/Targets/PPC.h