| 1 | //===------ SemaHexagon.cpp ------ Hexagon target-specific routines -------===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file implements semantic analysis functions specific to Hexagon. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #include "clang/Sema/SemaHexagon.h" |
| 14 | #include "clang/Basic/TargetBuiltins.h" |
| 15 | #include "clang/Sema/Sema.h" |
| 16 | #include "llvm/ADT/STLExtras.h" |
| 17 | #include <cstdint> |
| 18 | #include <iterator> |
| 19 | |
| 20 | namespace clang { |
| 21 | |
| 22 | SemaHexagon::SemaHexagon(Sema &S) : SemaBase(S) {} |
| 23 | |
| 24 | bool SemaHexagon::CheckHexagonBuiltinArgument(unsigned BuiltinID, |
| 25 | CallExpr *TheCall) { |
| 26 | struct ArgInfo { |
| 27 | uint8_t OpNum; |
| 28 | bool IsSigned; |
| 29 | uint8_t BitWidth; |
| 30 | uint8_t Align; |
| 31 | }; |
| 32 | struct BuiltinInfo { |
| 33 | unsigned BuiltinID; |
| 34 | ArgInfo Infos[2]; |
| 35 | }; |
| 36 | |
| 37 | static BuiltinInfo Infos[] = { |
| 38 | { Hexagon::BI__builtin_circ_ldd, {{ 3, true, 4, 3 }} }, |
| 39 | { Hexagon::BI__builtin_circ_ldw, {{ 3, true, 4, 2 }} }, |
| 40 | { Hexagon::BI__builtin_circ_ldh, {{ 3, true, 4, 1 }} }, |
| 41 | { Hexagon::BI__builtin_circ_lduh, {{ 3, true, 4, 1 }} }, |
| 42 | { Hexagon::BI__builtin_circ_ldb, {{ 3, true, 4, 0 }} }, |
| 43 | { Hexagon::BI__builtin_circ_ldub, {{ 3, true, 4, 0 }} }, |
| 44 | { Hexagon::BI__builtin_circ_std, {{ 3, true, 4, 3 }} }, |
| 45 | { Hexagon::BI__builtin_circ_stw, {{ 3, true, 4, 2 }} }, |
| 46 | { Hexagon::BI__builtin_circ_sth, {{ 3, true, 4, 1 }} }, |
| 47 | { Hexagon::BI__builtin_circ_sthhi, {{ 3, true, 4, 1 }} }, |
| 48 | { Hexagon::BI__builtin_circ_stb, {{ 3, true, 4, 0 }} }, |
| 49 | |
| 50 | { Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci, {{ 1, true, 4, 0 }} }, |
| 51 | { Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci, {{ 1, true, 4, 0 }} }, |
| 52 | { Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci, {{ 1, true, 4, 1 }} }, |
| 53 | { Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci, {{ 1, true, 4, 1 }} }, |
| 54 | { Hexagon::BI__builtin_HEXAGON_L2_loadri_pci, {{ 1, true, 4, 2 }} }, |
| 55 | { Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci, {{ 1, true, 4, 3 }} }, |
| 56 | { Hexagon::BI__builtin_HEXAGON_S2_storerb_pci, {{ 1, true, 4, 0 }} }, |
| 57 | { Hexagon::BI__builtin_HEXAGON_S2_storerh_pci, {{ 1, true, 4, 1 }} }, |
| 58 | { Hexagon::BI__builtin_HEXAGON_S2_storerf_pci, {{ 1, true, 4, 1 }} }, |
| 59 | { Hexagon::BI__builtin_HEXAGON_S2_storeri_pci, {{ 1, true, 4, 2 }} }, |
| 60 | { Hexagon::BI__builtin_HEXAGON_S2_storerd_pci, {{ 1, true, 4, 3 }} }, |
| 61 | |
| 62 | { Hexagon::BI__builtin_HEXAGON_A2_combineii, {{ 1, true, 8, 0 }} }, |
| 63 | { Hexagon::BI__builtin_HEXAGON_A2_tfrih, {{ 1, false, 16, 0 }} }, |
| 64 | { Hexagon::BI__builtin_HEXAGON_A2_tfril, {{ 1, false, 16, 0 }} }, |
| 65 | { Hexagon::BI__builtin_HEXAGON_A2_tfrpi, {{ 0, true, 8, 0 }} }, |
| 66 | { Hexagon::BI__builtin_HEXAGON_A4_bitspliti, {{ 1, false, 5, 0 }} }, |
| 67 | { Hexagon::BI__builtin_HEXAGON_A4_cmpbeqi, {{ 1, false, 8, 0 }} }, |
| 68 | { Hexagon::BI__builtin_HEXAGON_A4_cmpbgti, {{ 1, true, 8, 0 }} }, |
| 69 | { Hexagon::BI__builtin_HEXAGON_A4_cround_ri, {{ 1, false, 5, 0 }} }, |
| 70 | { Hexagon::BI__builtin_HEXAGON_A4_round_ri, {{ 1, false, 5, 0 }} }, |
| 71 | { Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat, {{ 1, false, 5, 0 }} }, |
| 72 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpbeqi, {{ 1, false, 8, 0 }} }, |
| 73 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgti, {{ 1, true, 8, 0 }} }, |
| 74 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpbgtui, {{ 1, false, 7, 0 }} }, |
| 75 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpheqi, {{ 1, true, 8, 0 }} }, |
| 76 | { Hexagon::BI__builtin_HEXAGON_A4_vcmphgti, {{ 1, true, 8, 0 }} }, |
| 77 | { Hexagon::BI__builtin_HEXAGON_A4_vcmphgtui, {{ 1, false, 7, 0 }} }, |
| 78 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpweqi, {{ 1, true, 8, 0 }} }, |
| 79 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgti, {{ 1, true, 8, 0 }} }, |
| 80 | { Hexagon::BI__builtin_HEXAGON_A4_vcmpwgtui, {{ 1, false, 7, 0 }} }, |
| 81 | { Hexagon::BI__builtin_HEXAGON_C2_bitsclri, {{ 1, false, 6, 0 }} }, |
| 82 | { Hexagon::BI__builtin_HEXAGON_C2_muxii, {{ 2, true, 8, 0 }} }, |
| 83 | { Hexagon::BI__builtin_HEXAGON_C4_nbitsclri, {{ 1, false, 6, 0 }} }, |
| 84 | { Hexagon::BI__builtin_HEXAGON_F2_dfclass, {{ 1, false, 5, 0 }} }, |
| 85 | { Hexagon::BI__builtin_HEXAGON_F2_dfimm_n, {{ 0, false, 10, 0 }} }, |
| 86 | { Hexagon::BI__builtin_HEXAGON_F2_dfimm_p, {{ 0, false, 10, 0 }} }, |
| 87 | { Hexagon::BI__builtin_HEXAGON_F2_sfclass, {{ 1, false, 5, 0 }} }, |
| 88 | { Hexagon::BI__builtin_HEXAGON_F2_sfimm_n, {{ 0, false, 10, 0 }} }, |
| 89 | { Hexagon::BI__builtin_HEXAGON_F2_sfimm_p, {{ 0, false, 10, 0 }} }, |
| 90 | { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addi, {{ 2, false, 6, 0 }} }, |
| 91 | { Hexagon::BI__builtin_HEXAGON_M4_mpyri_addr_u2, {{ 1, false, 6, 2 }} }, |
| 92 | { Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri, {{ 2, false, 3, 0 }} }, |
| 93 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc, {{ 2, false, 6, 0 }} }, |
| 94 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and, {{ 2, false, 6, 0 }} }, |
| 95 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p, {{ 1, false, 6, 0 }} }, |
| 96 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac, {{ 2, false, 6, 0 }} }, |
| 97 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or, {{ 2, false, 6, 0 }} }, |
| 98 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc, {{ 2, false, 6, 0 }} }, |
| 99 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc, {{ 2, false, 5, 0 }} }, |
| 100 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and, {{ 2, false, 5, 0 }} }, |
| 101 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r, {{ 1, false, 5, 0 }} }, |
| 102 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac, {{ 2, false, 5, 0 }} }, |
| 103 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or, {{ 2, false, 5, 0 }} }, |
| 104 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat, {{ 1, false, 5, 0 }} }, |
| 105 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc, {{ 2, false, 5, 0 }} }, |
| 106 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh, {{ 1, false, 4, 0 }} }, |
| 107 | { Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw, {{ 1, false, 5, 0 }} }, |
| 108 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc, {{ 2, false, 6, 0 }} }, |
| 109 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and, {{ 2, false, 6, 0 }} }, |
| 110 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p, {{ 1, false, 6, 0 }} }, |
| 111 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac, {{ 2, false, 6, 0 }} }, |
| 112 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or, {{ 2, false, 6, 0 }} }, |
| 113 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax, |
| 114 | {{ 1, false, 6, 0 }} }, |
| 115 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_rnd, {{ 1, false, 6, 0 }} }, |
| 116 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc, {{ 2, false, 5, 0 }} }, |
| 117 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and, {{ 2, false, 5, 0 }} }, |
| 118 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r, {{ 1, false, 5, 0 }} }, |
| 119 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac, {{ 2, false, 5, 0 }} }, |
| 120 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or, {{ 2, false, 5, 0 }} }, |
| 121 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax, |
| 122 | {{ 1, false, 5, 0 }} }, |
| 123 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd, {{ 1, false, 5, 0 }} }, |
| 124 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun, {{ 1, false, 5, 0 }} }, |
| 125 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh, {{ 1, false, 4, 0 }} }, |
| 126 | { Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw, {{ 1, false, 5, 0 }} }, |
| 127 | { Hexagon::BI__builtin_HEXAGON_S2_clrbit_i, {{ 1, false, 5, 0 }} }, |
| 128 | { Hexagon::BI__builtin_HEXAGON_S2_extractu, {{ 1, false, 5, 0 }, |
| 129 | { 2, false, 5, 0 }} }, |
| 130 | { Hexagon::BI__builtin_HEXAGON_S2_extractup, {{ 1, false, 6, 0 }, |
| 131 | { 2, false, 6, 0 }} }, |
| 132 | { Hexagon::BI__builtin_HEXAGON_S2_insert, {{ 2, false, 5, 0 }, |
| 133 | { 3, false, 5, 0 }} }, |
| 134 | { Hexagon::BI__builtin_HEXAGON_S2_insertp, {{ 2, false, 6, 0 }, |
| 135 | { 3, false, 6, 0 }} }, |
| 136 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc, {{ 2, false, 6, 0 }} }, |
| 137 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and, {{ 2, false, 6, 0 }} }, |
| 138 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p, {{ 1, false, 6, 0 }} }, |
| 139 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac, {{ 2, false, 6, 0 }} }, |
| 140 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or, {{ 2, false, 6, 0 }} }, |
| 141 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc, {{ 2, false, 6, 0 }} }, |
| 142 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc, {{ 2, false, 5, 0 }} }, |
| 143 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and, {{ 2, false, 5, 0 }} }, |
| 144 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r, {{ 1, false, 5, 0 }} }, |
| 145 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac, {{ 2, false, 5, 0 }} }, |
| 146 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or, {{ 2, false, 5, 0 }} }, |
| 147 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc, {{ 2, false, 5, 0 }} }, |
| 148 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh, {{ 1, false, 4, 0 }} }, |
| 149 | { Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw, {{ 1, false, 5, 0 }} }, |
| 150 | { Hexagon::BI__builtin_HEXAGON_S2_setbit_i, {{ 1, false, 5, 0 }} }, |
| 151 | { Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax, |
| 152 | {{ 2, false, 4, 0 }, |
| 153 | { 3, false, 5, 0 }} }, |
| 154 | { Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax, |
| 155 | {{ 2, false, 4, 0 }, |
| 156 | { 3, false, 5, 0 }} }, |
| 157 | { Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax, |
| 158 | {{ 2, false, 4, 0 }, |
| 159 | { 3, false, 5, 0 }} }, |
| 160 | { Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax, |
| 161 | {{ 2, false, 4, 0 }, |
| 162 | { 3, false, 5, 0 }} }, |
| 163 | { Hexagon::BI__builtin_HEXAGON_S2_togglebit_i, {{ 1, false, 5, 0 }} }, |
| 164 | { Hexagon::BI__builtin_HEXAGON_S2_tstbit_i, {{ 1, false, 5, 0 }} }, |
| 165 | { Hexagon::BI__builtin_HEXAGON_S2_valignib, {{ 2, false, 3, 0 }} }, |
| 166 | { Hexagon::BI__builtin_HEXAGON_S2_vspliceib, {{ 2, false, 3, 0 }} }, |
| 167 | { Hexagon::BI__builtin_HEXAGON_S4_addi_asl_ri, {{ 2, false, 5, 0 }} }, |
| 168 | { Hexagon::BI__builtin_HEXAGON_S4_addi_lsr_ri, {{ 2, false, 5, 0 }} }, |
| 169 | { Hexagon::BI__builtin_HEXAGON_S4_andi_asl_ri, {{ 2, false, 5, 0 }} }, |
| 170 | { Hexagon::BI__builtin_HEXAGON_S4_andi_lsr_ri, {{ 2, false, 5, 0 }} }, |
| 171 | { Hexagon::BI__builtin_HEXAGON_S4_clbaddi, {{ 1, true , 6, 0 }} }, |
| 172 | { Hexagon::BI__builtin_HEXAGON_S4_clbpaddi, {{ 1, true, 6, 0 }} }, |
| 173 | { Hexagon::BI__builtin_HEXAGON_S4_extract, {{ 1, false, 5, 0 }, |
| 174 | { 2, false, 5, 0 }} }, |
| 175 | { Hexagon::BI__builtin_HEXAGON_S4_extractp, {{ 1, false, 6, 0 }, |
| 176 | { 2, false, 6, 0 }} }, |
| 177 | { Hexagon::BI__builtin_HEXAGON_S4_lsli, {{ 0, true, 6, 0 }} }, |
| 178 | { Hexagon::BI__builtin_HEXAGON_S4_ntstbit_i, {{ 1, false, 5, 0 }} }, |
| 179 | { Hexagon::BI__builtin_HEXAGON_S4_ori_asl_ri, {{ 2, false, 5, 0 }} }, |
| 180 | { Hexagon::BI__builtin_HEXAGON_S4_ori_lsr_ri, {{ 2, false, 5, 0 }} }, |
| 181 | { Hexagon::BI__builtin_HEXAGON_S4_subi_asl_ri, {{ 2, false, 5, 0 }} }, |
| 182 | { Hexagon::BI__builtin_HEXAGON_S4_subi_lsr_ri, {{ 2, false, 5, 0 }} }, |
| 183 | { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate_acc, {{ 3, false, 2, 0 }} }, |
| 184 | { Hexagon::BI__builtin_HEXAGON_S4_vrcrotate, {{ 2, false, 2, 0 }} }, |
| 185 | { Hexagon::BI__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax, |
| 186 | {{ 1, false, 4, 0 }} }, |
| 187 | { Hexagon::BI__builtin_HEXAGON_S5_asrhub_sat, {{ 1, false, 4, 0 }} }, |
| 188 | { Hexagon::BI__builtin_HEXAGON_S5_vasrhrnd_goodsyntax, |
| 189 | {{ 1, false, 4, 0 }} }, |
| 190 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p, {{ 1, false, 6, 0 }} }, |
| 191 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_acc, {{ 2, false, 6, 0 }} }, |
| 192 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_and, {{ 2, false, 6, 0 }} }, |
| 193 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_nac, {{ 2, false, 6, 0 }} }, |
| 194 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_or, {{ 2, false, 6, 0 }} }, |
| 195 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_p_xacc, {{ 2, false, 6, 0 }} }, |
| 196 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r, {{ 1, false, 5, 0 }} }, |
| 197 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_acc, {{ 2, false, 5, 0 }} }, |
| 198 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_and, {{ 2, false, 5, 0 }} }, |
| 199 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_nac, {{ 2, false, 5, 0 }} }, |
| 200 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_or, {{ 2, false, 5, 0 }} }, |
| 201 | { Hexagon::BI__builtin_HEXAGON_S6_rol_i_r_xacc, {{ 2, false, 5, 0 }} }, |
| 202 | { Hexagon::BI__builtin_HEXAGON_V6_valignbi, {{ 2, false, 3, 0 }} }, |
| 203 | { Hexagon::BI__builtin_HEXAGON_V6_valignbi_128B, {{ 2, false, 3, 0 }} }, |
| 204 | { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi, {{ 2, false, 3, 0 }} }, |
| 205 | { Hexagon::BI__builtin_HEXAGON_V6_vlalignbi_128B, {{ 2, false, 3, 0 }} }, |
| 206 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi, {{ 2, false, 1, 0 }} }, |
| 207 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_128B, {{ 2, false, 1, 0 }} }, |
| 208 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc, {{ 3, false, 1, 0 }} }, |
| 209 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpybusi_acc_128B, |
| 210 | {{ 3, false, 1, 0 }} }, |
| 211 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi, {{ 2, false, 1, 0 }} }, |
| 212 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_128B, {{ 2, false, 1, 0 }} }, |
| 213 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc, {{ 3, false, 1, 0 }} }, |
| 214 | { Hexagon::BI__builtin_HEXAGON_V6_vrmpyubi_acc_128B, |
| 215 | {{ 3, false, 1, 0 }} }, |
| 216 | { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi, {{ 2, false, 1, 0 }} }, |
| 217 | { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_128B, {{ 2, false, 1, 0 }} }, |
| 218 | { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc, {{ 3, false, 1, 0 }} }, |
| 219 | { Hexagon::BI__builtin_HEXAGON_V6_vrsadubi_acc_128B, |
| 220 | {{ 3, false, 1, 0 }} }, |
| 221 | |
| 222 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10, {{ 2, false, 2, 0 }} }, |
| 223 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_128B, |
| 224 | {{ 2, false, 2, 0 }} }, |
| 225 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx, |
| 226 | {{ 3, false, 2, 0 }} }, |
| 227 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyhubs10_vxx_128B, |
| 228 | {{ 3, false, 2, 0 }} }, |
| 229 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10, {{ 2, false, 2, 0 }} }, |
| 230 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_128B, |
| 231 | {{ 2, false, 2, 0 }} }, |
| 232 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx, |
| 233 | {{ 3, false, 2, 0 }} }, |
| 234 | { Hexagon::BI__builtin_HEXAGON_V6_v6mpyvubs10_vxx_128B, |
| 235 | {{ 3, false, 2, 0 }} }, |
| 236 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi, {{ 2, false, 3, 0 }} }, |
| 237 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvvbi_128B, {{ 2, false, 3, 0 }} }, |
| 238 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci, {{ 3, false, 3, 0 }} }, |
| 239 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvvb_oracci_128B, |
| 240 | {{ 3, false, 3, 0 }} }, |
| 241 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi, {{ 2, false, 3, 0 }} }, |
| 242 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvwhi_128B, {{ 2, false, 3, 0 }} }, |
| 243 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci, {{ 3, false, 3, 0 }} }, |
| 244 | { Hexagon::BI__builtin_HEXAGON_V6_vlutvwh_oracci_128B, |
| 245 | {{ 3, false, 3, 0 }} }, |
| 246 | }; |
| 247 | |
| 248 | // Use a dynamically initialized static to sort the table exactly once on |
| 249 | // first run. |
| 250 | static const bool SortOnce = |
| 251 | (llvm::sort(C&: Infos, |
| 252 | Comp: [](const BuiltinInfo &LHS, const BuiltinInfo &RHS) { |
| 253 | return LHS.BuiltinID < RHS.BuiltinID; |
| 254 | }), |
| 255 | true); |
| 256 | (void)SortOnce; |
| 257 | |
| 258 | const BuiltinInfo *F = llvm::partition_point( |
| 259 | Infos, [=](const BuiltinInfo &BI) { return BI.BuiltinID < BuiltinID; }); |
| 260 | if (F == std::end(Infos) || F->BuiltinID != BuiltinID) |
| 261 | return false; |
| 262 | |
| 263 | bool Error = false; |
| 264 | |
| 265 | for (const ArgInfo &A : F->Infos) { |
| 266 | // Ignore empty ArgInfo elements. |
| 267 | if (A.BitWidth == 0) |
| 268 | continue; |
| 269 | |
| 270 | int32_t Min = A.IsSigned ? -(1 << (A.BitWidth - 1)) : 0; |
| 271 | int32_t Max = (1 << (A.IsSigned ? A.BitWidth - 1 : A.BitWidth)) - 1; |
| 272 | if (!A.Align) { |
| 273 | Error |= SemaRef.BuiltinConstantArgRange(TheCall, A.OpNum, Min, Max); |
| 274 | } else { |
| 275 | unsigned M = 1 << A.Align; |
| 276 | Min *= M; |
| 277 | Max *= M; |
| 278 | Error |= SemaRef.BuiltinConstantArgRange(TheCall, A.OpNum, Min, Max); |
| 279 | Error |= SemaRef.BuiltinConstantArgMultiple(TheCall, A.OpNum, M); |
| 280 | } |
| 281 | } |
| 282 | return Error; |
| 283 | } |
| 284 | |
| 285 | bool SemaHexagon::CheckHexagonBuiltinFunctionCall(unsigned BuiltinID, |
| 286 | CallExpr *TheCall) { |
| 287 | return CheckHexagonBuiltinArgument(BuiltinID, TheCall); |
| 288 | } |
| 289 | |
| 290 | } // namespace clang |
| 291 | |