1//===-- TestMCDisasmInstanceRISCV.cpp -------------------------------------===//
2
3//
4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5// See https://llvm.org/LICENSE.txt for license information.
6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/Support/TargetSelect.h"
11#include "gtest/gtest.h"
12
13#include "lldb/Core/Address.h"
14#include "lldb/Core/Disassembler.h"
15#include "lldb/Target/ExecutionContext.h"
16#include "lldb/Utility/ArchSpec.h"
17#include "lldb/Utility/StreamString.h"
18
19#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
20
21using namespace lldb;
22using namespace lldb_private;
23
24namespace {
25class TestMCDisasmInstanceRISCV : public testing::Test {
26public:
27 static void SetUpTestCase();
28 static void TearDownTestCase();
29
30protected:
31};
32
33void TestMCDisasmInstanceRISCV::SetUpTestCase() {
34 llvm::InitializeAllTargets();
35 llvm::InitializeAllAsmPrinters();
36 llvm::InitializeAllTargetMCs();
37 llvm::InitializeAllDisassemblers();
38 DisassemblerLLVMC::Initialize();
39}
40
41void TestMCDisasmInstanceRISCV::TearDownTestCase() {
42 DisassemblerLLVMC::Terminate();
43}
44} // namespace
45
46TEST_F(TestMCDisasmInstanceRISCV, TestRISCV32Instruction) {
47 ArchSpec arch("riscv32-*-linux");
48
49 const unsigned num_of_instructions = 5;
50 uint8_t data[] = {
51 0xef, 0x00, 0x00, 0x00, // call -- jal x1, 0
52 0xe7, 0x00, 0x00, 0x00, // call -- jalr x1, x0, 0
53 0x6f, 0x00, 0x00, 0x00, // jump -- jal x0, 0
54 0x67, 0x00, 0x00, 0x00, // jump -- jalr x0, x0, 0
55 0x67, 0x80, 0x00, 0x00 // ret -- jalr x0, x1, 0
56 };
57
58 DisassemblerSP disass_sp;
59 Address start_addr(0x100);
60 disass_sp = Disassembler::DisassembleBytes(
61 arch, plugin_name: nullptr, flavor: nullptr, cpu: nullptr, features: nullptr, start: start_addr, bytes: &data, length: sizeof(data),
62 max_num_instructions: num_of_instructions, data_from_file: false);
63
64 const InstructionList inst_list(disass_sp->GetInstructionList());
65 EXPECT_EQ(num_of_instructions, inst_list.GetSize());
66
67 InstructionSP inst_sp;
68 inst_sp = inst_list.GetInstructionAtIndex(idx: 0);
69 EXPECT_TRUE(inst_sp->IsCall());
70 EXPECT_TRUE(inst_sp->DoesBranch());
71
72 inst_sp = inst_list.GetInstructionAtIndex(idx: 1);
73 EXPECT_TRUE(inst_sp->IsCall());
74 EXPECT_TRUE(inst_sp->DoesBranch());
75
76 inst_sp = inst_list.GetInstructionAtIndex(idx: 2);
77 EXPECT_FALSE(inst_sp->IsCall());
78 EXPECT_TRUE(inst_sp->DoesBranch());
79
80 inst_sp = inst_list.GetInstructionAtIndex(idx: 3);
81 EXPECT_FALSE(inst_sp->IsCall());
82 EXPECT_TRUE(inst_sp->DoesBranch());
83
84 inst_sp = inst_list.GetInstructionAtIndex(idx: 4);
85 EXPECT_FALSE(inst_sp->IsCall());
86 EXPECT_TRUE(inst_sp->DoesBranch());
87}
88
89TEST_F(TestMCDisasmInstanceRISCV, TestOpcodeBytePrinter) {
90 ArchSpec arch("riscv32-*-linux");
91
92 const unsigned num_of_instructions = 7;
93 // clang-format off
94 uint8_t data[] = {
95 0x41, 0x11, // addi sp, sp, -0x10
96 0x06, 0xc6, // sw ra, 0xc(sp)
97 0x23, 0x2a, 0xa4, 0xfe, // sw a0, -0xc(s0)
98 0x23, 0x28, 0xa4, 0xfe, // sw a0, -0x10(s0)
99 0x22, 0x44, // lw s0, 0x8(sp)
100
101 0x3f, 0x00, 0x40, 0x09, // Fake 64-bit instruction
102 0x20, 0x00, 0x20, 0x00,
103
104 0x1f, 0x02, // 48 bit xqci.e.li rd=8 imm=0x1000
105 0x00, 0x00,
106 0x00, 0x10,
107 };
108 // clang-format on
109
110 // clang-format off
111 const char *expected_outputs[] = {
112 "1141",
113 "c606",
114 "fea42a23",
115 "fea42823",
116 "4422",
117 "0940003f 00200020",
118 "021f 0000 1000"
119 };
120 // clang-format on
121 const unsigned num_of_expected_outputs =
122 sizeof(expected_outputs) / sizeof(char *);
123
124 EXPECT_EQ(num_of_instructions, num_of_expected_outputs);
125
126 DisassemblerSP disass_sp;
127 Address start_addr(0x100);
128 disass_sp = Disassembler::DisassembleBytes(
129 arch, plugin_name: nullptr, flavor: nullptr, cpu: nullptr, features: nullptr, start: start_addr, bytes: &data, length: sizeof(data),
130 max_num_instructions: num_of_instructions, data_from_file: false);
131
132 const InstructionList inst_list(disass_sp->GetInstructionList());
133 EXPECT_EQ(num_of_instructions, inst_list.GetSize());
134
135 for (size_t i = 0; i < num_of_instructions; i++) {
136 InstructionSP inst_sp;
137 StreamString s;
138 inst_sp = inst_list.GetInstructionAtIndex(idx: i);
139 inst_sp->GetOpcode().Dump(s: &s, min_byte_width: 1);
140 ASSERT_STREQ(s.GetString().str().c_str(), expected_outputs[i]);
141 }
142}
143

source code of lldb/unittests/Disassembler/RISCV/TestMCDisasmInstanceRISCV.cpp