| 1 | //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This file provides AArch64 specific target descriptions. |
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| 10 | // |
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| 11 | //===----------------------------------------------------------------------===// |
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| 12 | |
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| 13 | #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H |
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| 14 | #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H |
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| 15 | |
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| 16 | #include "llvm/MC/MCInstrDesc.h" |
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| 17 | #include "llvm/Support/DataTypes.h" |
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| 18 | |
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| 19 | #include <memory> |
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| 20 | |
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| 21 | namespace llvm { |
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| 22 | class formatted_raw_ostream; |
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| 23 | class MCAsmBackend; |
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| 24 | class MCCodeEmitter; |
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| 25 | class MCContext; |
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| 26 | class MCInst; |
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| 27 | class MCInstrInfo; |
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| 28 | class MCInstPrinter; |
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| 29 | class MCRegisterInfo; |
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| 30 | class MCObjectTargetWriter; |
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| 31 | class MCStreamer; |
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| 32 | class MCSubtargetInfo; |
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| 33 | class MCTargetOptions; |
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| 34 | class MCTargetStreamer; |
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| 35 | class Target; |
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| 36 | class Triple; |
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| 37 | |
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| 38 | MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, |
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| 39 | MCContext &Ctx); |
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| 40 | MCAsmBackend *createAArch64leAsmBackend(const Target &T, |
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| 41 | const MCSubtargetInfo &STI, |
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| 42 | const MCRegisterInfo &MRI, |
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| 43 | const MCTargetOptions &Options); |
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| 44 | MCAsmBackend *createAArch64beAsmBackend(const Target &T, |
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| 45 | const MCSubtargetInfo &STI, |
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| 46 | const MCRegisterInfo &MRI, |
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| 47 | const MCTargetOptions &Options); |
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| 48 | |
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| 49 | std::unique_ptr<MCObjectTargetWriter> |
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| 50 | createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32); |
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| 51 | |
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| 52 | std::unique_ptr<MCObjectTargetWriter> |
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| 53 | createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, |
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| 54 | bool IsILP32); |
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| 55 | |
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| 56 | std::unique_ptr<MCObjectTargetWriter> |
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| 57 | createAArch64WinCOFFObjectWriter(const Triple &TheTriple); |
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| 58 | |
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| 59 | MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S, |
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| 60 | formatted_raw_ostream &OS, |
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| 61 | MCInstPrinter *InstPrint, |
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| 62 | bool isVerboseAsm); |
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| 63 | |
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| 64 | namespace AArch64_MC { |
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| 65 | void initLLVMToCVRegMapping(MCRegisterInfo *MRI); |
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| 66 | bool isHForm(const MCInst &MI, const MCInstrInfo *MCII); |
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| 67 | bool isQForm(const MCInst &MI, const MCInstrInfo *MCII); |
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| 68 | bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); |
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| 69 | } |
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| 70 | |
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| 71 | namespace AArch64 { |
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| 72 | enum OperandType { |
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| 73 | OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET, |
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| 74 | }; |
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| 75 | } // namespace AArch64 |
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| 76 | |
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| 77 | } // End llvm namespace |
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| 78 | |
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| 79 | // Defines symbolic names for AArch64 registers. This defines a mapping from |
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| 80 | // register name to register number. |
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| 81 | // |
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| 82 | #define GET_REGINFO_ENUM |
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| 83 | #include "AArch64GenRegisterInfo.inc" |
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| 84 | |
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| 85 | // Defines symbolic names for the AArch64 instructions. |
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| 86 | // |
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| 87 | #define GET_INSTRINFO_ENUM |
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| 88 | #define GET_INSTRINFO_MC_HELPER_DECLS |
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| 89 | #include "AArch64GenInstrInfo.inc" |
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| 90 | |
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| 91 | #define GET_SUBTARGETINFO_ENUM |
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| 92 | #include "AArch64GenSubtargetInfo.inc" |
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| 93 | |
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| 94 | #endif |
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| 95 | |
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