1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AMDGPUArgumentUsageInfo.h"
10#include "AMDGPU.h"
11#include "AMDGPUTargetMachine.h"
12#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13#include "SIRegisterInfo.h"
14#include "llvm/CodeGen/TargetRegisterInfo.h"
15#include "llvm/IR/Function.h"
16#include "llvm/Support/NativeFormatting.h"
17#include "llvm/Support/raw_ostream.h"
18
19using namespace llvm;
20
21#define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
22
23INITIALIZE_PASS(AMDGPUArgumentUsageInfo, DEBUG_TYPE,
24 "Argument Register Usage Information Storage", false, true)
25
26void ArgDescriptor::print(raw_ostream &OS,
27 const TargetRegisterInfo *TRI) const {
28 if (!isSet()) {
29 OS << "<not set>\n";
30 return;
31 }
32
33 if (isRegister())
34 OS << "Reg " << printReg(Reg: getRegister(), TRI);
35 else
36 OS << "Stack offset " << getStackOffset();
37
38 if (isMasked()) {
39 OS << " & ";
40 llvm::write_hex(S&: OS, N: Mask, Style: llvm::HexPrintStyle::PrefixLower);
41 }
42
43 OS << '\n';
44}
45
46char AMDGPUArgumentUsageInfo::ID = 0;
47
48const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
49
50// Hardcoded registers from fixed function ABI
51const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
52 = AMDGPUFunctionArgInfo::fixedABILayout();
53
54bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) {
55 return false;
56}
57
58bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) {
59 ArgInfoMap.clear();
60 return false;
61}
62
63// TODO: Print preload kernargs?
64void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
65 for (const auto &FI : ArgInfoMap) {
66 OS << "Arguments for " << FI.first->getName() << '\n'
67 << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
68 << " DispatchPtr: " << FI.second.DispatchPtr
69 << " QueuePtr: " << FI.second.QueuePtr
70 << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
71 << " DispatchID: " << FI.second.DispatchID
72 << " FlatScratchInit: " << FI.second.FlatScratchInit
73 << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
74 << " WorkGroupIDX: " << FI.second.WorkGroupIDX
75 << " WorkGroupIDY: " << FI.second.WorkGroupIDY
76 << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
77 << " WorkGroupInfo: " << FI.second.WorkGroupInfo
78 << " LDSKernelId: " << FI.second.LDSKernelId
79 << " PrivateSegmentWaveByteOffset: "
80 << FI.second.PrivateSegmentWaveByteOffset
81 << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
82 << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
83 << " WorkItemIDX " << FI.second.WorkItemIDX
84 << " WorkItemIDY " << FI.second.WorkItemIDY
85 << " WorkItemIDZ " << FI.second.WorkItemIDZ
86 << '\n';
87 }
88}
89
90std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
91AMDGPUFunctionArgInfo::getPreloadedValue(
92 AMDGPUFunctionArgInfo::PreloadedValue Value) const {
93 switch (Value) {
94 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
95 return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
96 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32));
97 }
98 case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
99 return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
100 &AMDGPU::SGPR_64RegClass,
101 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
102 case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
103 return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
104 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
105 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
106 return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
107 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
108 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
109 return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
110 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
111 case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
112 return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
113 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
114 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
115 return std::tuple(
116 PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
117 &AMDGPU::SGPR_32RegClass, LLT::scalar(SizeInBits: 32));
118 case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
119 return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
120 &AMDGPU::SGPR_64RegClass,
121 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
122 case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
123 return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
124 &AMDGPU::SGPR_64RegClass,
125 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
126 case AMDGPUFunctionArgInfo::DISPATCH_ID:
127 return std::tuple(DispatchID ? &DispatchID : nullptr,
128 &AMDGPU::SGPR_64RegClass, LLT::scalar(SizeInBits: 64));
129 case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
130 return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
131 &AMDGPU::SGPR_64RegClass, LLT::scalar(SizeInBits: 64));
132 case AMDGPUFunctionArgInfo::DISPATCH_PTR:
133 return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
134 &AMDGPU::SGPR_64RegClass,
135 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
136 case AMDGPUFunctionArgInfo::QUEUE_PTR:
137 return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
138 LLT::pointer(AddressSpace: AMDGPUAS::CONSTANT_ADDRESS, SizeInBits: 64));
139 case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
140 return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
141 &AMDGPU::VGPR_32RegClass, LLT::scalar(SizeInBits: 32));
142 case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
143 return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
144 &AMDGPU::VGPR_32RegClass, LLT::scalar(SizeInBits: 32));
145 case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
146 return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
147 &AMDGPU::VGPR_32RegClass, LLT::scalar(SizeInBits: 32));
148 }
149 llvm_unreachable("unexpected preloaded value type");
150}
151
152AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
153 AMDGPUFunctionArgInfo AI;
154 AI.PrivateSegmentBuffer
155 = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR0_SGPR1_SGPR2_SGPR3);
156 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR4_SGPR5);
157 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR6_SGPR7);
158
159 // Do not pass kernarg segment pointer, only pass increment version in its
160 // place.
161 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR8_SGPR9);
162 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR10_SGPR11);
163
164 // Skip FlatScratchInit/PrivateSegmentSize
165 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR12);
166 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR13);
167 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR14);
168 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::Reg: SGPR15);
169
170 const unsigned Mask = 0x3ff;
171 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::Reg: VGPR31, Mask);
172 AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::Reg: VGPR31, Mask: Mask << 10);
173 AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::Reg: VGPR31, Mask: Mask << 20);
174 return AI;
175}
176
177const AMDGPUFunctionArgInfo &
178AMDGPUArgumentUsageInfo::lookupFuncArgInfo(const Function &F) const {
179 auto I = ArgInfoMap.find(Val: &F);
180 if (I == ArgInfoMap.end())
181 return FixedABIFunctionInfo;
182 return I->second;
183}
184

source code of llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp