1// Copyright (C) 2022 Intel Corporation.
2// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
3// This is a generated file. DO NOT EDIT.
4// Please see util/x86simdgen/README.md
5
6#include "qsimd_x86_p.h"
7
8static const char features_string[] =
9 " sse2\0"
10 " sse3\0"
11 " ssse3\0"
12 " fma\0"
13 " sse4.1\0"
14 " sse4.2\0"
15 " movbe\0"
16 " popcnt\0"
17 " aes\0"
18 " avx\0"
19 " f16c\0"
20 " rdrnd\0"
21 " bmi\0"
22 " avx2\0"
23 " bmi2\0"
24 " avx512f\0"
25 " avx512dq\0"
26 " rdseed\0"
27 " avx512ifma\0"
28 " avx512cd\0"
29 " sha\0"
30 " avx512bw\0"
31 " avx512vl\0"
32 " avx512vbmi\0"
33 " waitpkg\0"
34 " avx512vbmi2\0"
35 " shstk\0"
36 " gfni\0"
37 " vaes\0"
38 " avx512bitalg\0"
39 " avx512vpopcntdq\0"
40 " hybrid\0"
41 " ibt\0"
42 " avx512fp16\0"
43 " raoint\0"
44 " cmpccxadd\0"
45 " avxifma\0"
46 " lam\0"
47 "\0";
48
49static const uint16_t features_indices[] = {
50 0, 6, 12, 19, 24, 32, 40, 47,
51 55, 60, 65, 71, 78, 83, 89, 95,
52 104, 114, 122, 134, 144, 149, 159, 169,
53 181, 190, 203, 210, 216, 222, 236, 253,
54 261, 266, 278, 286, 297, 306,
55};
56
57enum X86CpuidLeaves {
58 Leaf01EDX,
59 Leaf01ECX,
60 Leaf07_00EBX,
61 Leaf07_00ECX,
62 Leaf07_00EDX,
63 Leaf07_01EAX,
64 Leaf07_01EDX,
65 Leaf13_01EAX,
66 Leaf80000001hECX,
67 Leaf80000008hEBX,
68 X86CpuidMaxLeaf
69};
70
71static const uint16_t x86_locators[] = {
72 Leaf01EDX*32 + 26, // sse2
73 Leaf01ECX*32 + 0, // sse3
74 Leaf01ECX*32 + 9, // ssse3
75 Leaf01ECX*32 + 12, // fma
76 Leaf01ECX*32 + 19, // sse4.1
77 Leaf01ECX*32 + 20, // sse4.2
78 Leaf01ECX*32 + 22, // movbe
79 Leaf01ECX*32 + 23, // popcnt
80 Leaf01ECX*32 + 25, // aes
81 Leaf01ECX*32 + 28, // avx
82 Leaf01ECX*32 + 29, // f16c
83 Leaf01ECX*32 + 30, // rdrnd
84 Leaf07_00EBX*32 + 3, // bmi
85 Leaf07_00EBX*32 + 5, // avx2
86 Leaf07_00EBX*32 + 8, // bmi2
87 Leaf07_00EBX*32 + 16, // avx512f
88 Leaf07_00EBX*32 + 17, // avx512dq
89 Leaf07_00EBX*32 + 18, // rdseed
90 Leaf07_00EBX*32 + 21, // avx512ifma
91 Leaf07_00EBX*32 + 28, // avx512cd
92 Leaf07_00EBX*32 + 29, // sha
93 Leaf07_00EBX*32 + 30, // avx512bw
94 Leaf07_00EBX*32 + 31, // avx512vl
95 Leaf07_00ECX*32 + 1, // avx512vbmi
96 Leaf07_00ECX*32 + 5, // waitpkg
97 Leaf07_00ECX*32 + 6, // avx512vbmi2
98 Leaf07_00ECX*32 + 7, // shstk
99 Leaf07_00ECX*32 + 8, // gfni
100 Leaf07_00ECX*32 + 9, // vaes
101 Leaf07_00ECX*32 + 12, // avx512bitalg
102 Leaf07_00ECX*32 + 14, // avx512vpopcntdq
103 Leaf07_00EDX*32 + 15, // hybrid
104 Leaf07_00EDX*32 + 20, // ibt
105 Leaf07_00EDX*32 + 23, // avx512fp16
106 Leaf07_01EAX*32 + 3, // raoint
107 Leaf07_01EAX*32 + 6, // cmpccxadd
108 Leaf07_01EAX*32 + 23, // avxifma
109 Leaf07_01EAX*32 + 26, // lam
110};
111
112struct X86Architecture
113{
114 uint64_t features;
115 char name[17 + 1];
116};
117
118static const struct X86Architecture x86_architectures[] = {
119 { cpu_core2, .name: "Core2" },
120 { cpu_westmere, .name: "Westmere" },
121 { cpu_sandybridge, .name: "Sandy Bridge" },
122 { cpu_silvermont, .name: "Silvermont" },
123 { cpu_ivybridge, .name: "Ivy Bridge" },
124 { cpu_goldmont, .name: "Goldmont" },
125 { cpu_haswell, .name: "Haswell" },
126 { cpu_broadwell, .name: "Broadwell" },
127 { cpu_tremont, .name: "Tremont" },
128 { cpu_skylake, .name: "Skylake" },
129 { cpu_skylake_avx512, .name: "Skylake (Avx512)" },
130 { cpu_cascadelake, .name: "Cascade Lake" },
131 { cpu_cooperlake, .name: "Cooper Lake" },
132 { cpu_cannonlake, .name: "Cannon Lake" },
133 { cpu_gracemont, .name: "Gracemont" },
134 { cpu_icelake_client, .name: "Ice Lake (Client)" },
135 { cpu_icelake_server, .name: "Ice Lake (Server)" },
136 { cpu_crestmont, .name: "Crestmont" },
137 { cpu_tigerlake, .name: "Tiger Lake" },
138 { cpu_clearwaterforest, .name: "Clearwater Forest" },
139 { cpu_grandridge, .name: "Grand Ridge" },
140 { cpu_raptorcove, .name: "Raptor Cove" },
141 { cpu_redwoodcove, .name: "Redwood Cove" },
142 { cpu_emeraldrapids, .name: "Emerald Rapids" },
143 { cpu_graniterapids, .name: "Granite Rapids" },
144};
145
146enum XSaveBits {
147 XSave_X87 = 0x0001, // X87 and MMX state
148 XSave_SseState = 0x0002, // SSE: 128 bits of XMM registers
149 XSave_Ymm_Hi128 = 0x0004, // AVX: high 128 bits in YMM registers
150 XSave_Bndregs = 0x0008, // Memory Protection Extensions
151 XSave_Bndcsr = 0x0010, // Memory Protection Extensions
152 XSave_OpMask = 0x0020, // AVX512: k0 through k7
153 XSave_Zmm_Hi256 = 0x0040, // AVX512: high 256 bits of ZMM0-15
154 XSave_Hi16_Zmm = 0x0080, // AVX512: all 512 bits of ZMM16-31
155 XSave_PTState = 0x0100, // Processor Trace
156 XSave_PKRUState = 0x0200, // Protection Key
157 XSave_CetUState = 0x0800, // CET: user mode
158 XSave_CetSState = 0x1000, // CET: supervisor mode
159 XSave_HdcState = 0x2000, // Hardware Duty Cycle
160 XSave_UintrState = 0x4000, // User Interrupts
161 XSave_HwpState = 0x10000, // Hardware P-State
162 XSave_Xtilecfg = 0x20000, // AMX: XTILECFG register
163 XSave_Xtiledata = 0x40000, // AMX: data in the tiles
164 XSave_AvxState = XSave_SseState | XSave_Ymm_Hi128,
165 XSave_MPXState = XSave_Bndregs | XSave_Bndcsr,
166 XSave_Avx512State = XSave_AvxState | XSave_OpMask | XSave_Zmm_Hi256 | XSave_Hi16_Zmm,
167 XSave_CetState = XSave_CetUState | XSave_CetSState,
168 XSave_AmxState = XSave_Xtilecfg | XSave_Xtiledata,
169};
170
171// List of features requiring XSave_AvxState
172static const uint64_t XSaveReq_AvxState = 0
173 | cpu_feature_fma
174 | cpu_feature_avx
175 | cpu_feature_f16c
176 | cpu_feature_avx2
177 | cpu_feature_avx512f
178 | cpu_feature_avx512dq
179 | cpu_feature_avx512ifma
180 | cpu_feature_avx512cd
181 | cpu_feature_avx512bw
182 | cpu_feature_avx512vl
183 | cpu_feature_avx512vbmi
184 | cpu_feature_avx512vbmi2
185 | cpu_feature_vaes
186 | cpu_feature_avx512bitalg
187 | cpu_feature_avx512vpopcntdq
188 | cpu_feature_avx512fp16
189 | cpu_feature_avxifma;
190
191// List of features requiring XSave_Avx512State
192static const uint64_t XSaveReq_Avx512State = 0
193 | cpu_feature_avx512f
194 | cpu_feature_avx512dq
195 | cpu_feature_avx512ifma
196 | cpu_feature_avx512cd
197 | cpu_feature_avx512bw
198 | cpu_feature_avx512vl
199 | cpu_feature_avx512vbmi
200 | cpu_feature_avx512vbmi2
201 | cpu_feature_avx512bitalg
202 | cpu_feature_avx512vpopcntdq
203 | cpu_feature_avx512fp16;
204
205// List of features requiring XSave_CetState
206static const uint64_t XSaveReq_CetState = 0
207 | cpu_feature_shstk;
208
209struct XSaveRequirementMapping
210{
211 uint64_t cpu_features;
212 uint64_t xsave_state;
213};
214
215static const struct XSaveRequirementMapping xsave_requirements[] = {
216 { .cpu_features: XSaveReq_AvxState, .xsave_state: XSave_AvxState },
217 { .cpu_features: XSaveReq_Avx512State, .xsave_state: XSave_Avx512State },
218 { .cpu_features: XSaveReq_CetState, .xsave_state: XSave_CetState },
219};
220
221

source code of qtbase/src/corelib/global/qsimd_x86.cpp