1use crate::core_arch::{simd::*, x86::*};
2use crate::intrinsics::simd::*;
3
4#[cfg(test)]
5use stdarch_test::assert_instr;
6
7/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
8///
9/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmw_epi32&expand=553)
10#[inline]
11#[target_feature(enable = "avx512cd")]
12#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
13#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
14pub unsafe fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i {
15 _mm512_set1_epi32(k as i32)
16}
17
18/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
19///
20/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmw_epi32&expand=552)
21#[inline]
22#[target_feature(enable = "avx512cd,avx512vl")]
23#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
24#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
25pub unsafe fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i {
26 _mm256_set1_epi32(k as i32)
27}
28
29/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
30///
31/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmw_epi32&expand=551)
32#[inline]
33#[target_feature(enable = "avx512cd,avx512vl")]
34#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
35#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
36pub unsafe fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i {
37 _mm_set1_epi32(k as i32)
38}
39
40/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
41///
42/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmb_epi64&expand=550)
43#[inline]
44#[target_feature(enable = "avx512cd")]
45#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
46#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
47pub unsafe fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i {
48 _mm512_set1_epi64(k as i64)
49}
50
51/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
52///
53/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmb_epi64&expand=549)
54#[inline]
55#[target_feature(enable = "avx512cd,avx512vl")]
56#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
57#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
58pub unsafe fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i {
59 _mm256_set1_epi64x(k as i64)
60}
61
62/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
63///
64/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmb_epi64&expand=548)
65#[inline]
66#[target_feature(enable = "avx512cd,avx512vl")]
67#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
68#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
69pub unsafe fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i {
70 _mm_set1_epi64x(k as i64)
71}
72
73/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
74///
75/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi32&expand=1248)
76#[inline]
77#[target_feature(enable = "avx512cd")]
78#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
79#[cfg_attr(test, assert_instr(vpconflictd))]
80pub unsafe fn _mm512_conflict_epi32(a: __m512i) -> __m512i {
81 transmute(src:vpconflictd(a.as_i32x16()))
82}
83
84/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
85///
86/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi32&expand=1249)
87#[inline]
88#[target_feature(enable = "avx512cd")]
89#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
90#[cfg_attr(test, assert_instr(vpconflictd))]
91pub unsafe fn _mm512_mask_conflict_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
92 let conflict: i32x16 = _mm512_conflict_epi32(a).as_i32x16();
93 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:src.as_i32x16()))
94}
95
96/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
97///
98/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi32&expand=1250)
99#[inline]
100#[target_feature(enable = "avx512cd")]
101#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
102#[cfg_attr(test, assert_instr(vpconflictd))]
103pub unsafe fn _mm512_maskz_conflict_epi32(k: __mmask16, a: __m512i) -> __m512i {
104 let conflict: i32x16 = _mm512_conflict_epi32(a).as_i32x16();
105 let zero: i32x16 = _mm512_setzero_si512().as_i32x16();
106 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:zero))
107}
108
109/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
110///
111/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi32&expand=1245)
112#[inline]
113#[target_feature(enable = "avx512cd,avx512vl")]
114#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
115#[cfg_attr(test, assert_instr(vpconflictd))]
116pub unsafe fn _mm256_conflict_epi32(a: __m256i) -> __m256i {
117 transmute(src:vpconflictd256(a.as_i32x8()))
118}
119
120/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
121///
122/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi32&expand=1246)
123#[inline]
124#[target_feature(enable = "avx512cd,avx512vl")]
125#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
126#[cfg_attr(test, assert_instr(vpconflictd))]
127pub unsafe fn _mm256_mask_conflict_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
128 let conflict: i32x8 = _mm256_conflict_epi32(a).as_i32x8();
129 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:src.as_i32x8()))
130}
131
132/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
133///
134/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi32&expand=1247)
135#[inline]
136#[target_feature(enable = "avx512cd,avx512vl")]
137#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
138#[cfg_attr(test, assert_instr(vpconflictd))]
139pub unsafe fn _mm256_maskz_conflict_epi32(k: __mmask8, a: __m256i) -> __m256i {
140 let conflict: i32x8 = _mm256_conflict_epi32(a).as_i32x8();
141 let zero: i32x8 = _mm256_setzero_si256().as_i32x8();
142 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:zero))
143}
144
145/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
146///
147/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi32&expand=1242)
148#[inline]
149#[target_feature(enable = "avx512cd,avx512vl")]
150#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
151#[cfg_attr(test, assert_instr(vpconflictd))]
152pub unsafe fn _mm_conflict_epi32(a: __m128i) -> __m128i {
153 transmute(src:vpconflictd128(a.as_i32x4()))
154}
155
156/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
157///
158/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi32&expand=1243)
159#[inline]
160#[target_feature(enable = "avx512cd,avx512vl")]
161#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
162#[cfg_attr(test, assert_instr(vpconflictd))]
163pub unsafe fn _mm_mask_conflict_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
164 let conflict: i32x4 = _mm_conflict_epi32(a).as_i32x4();
165 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:src.as_i32x4()))
166}
167
168/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
169///
170/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi32&expand=1244)
171#[inline]
172#[target_feature(enable = "avx512cd,avx512vl")]
173#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
174#[cfg_attr(test, assert_instr(vpconflictd))]
175pub unsafe fn _mm_maskz_conflict_epi32(k: __mmask8, a: __m128i) -> __m128i {
176 let conflict: i32x4 = _mm_conflict_epi32(a).as_i32x4();
177 let zero: i32x4 = _mm_setzero_si128().as_i32x4();
178 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:zero))
179}
180
181/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
182///
183/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi64&expand=1257)
184#[inline]
185#[target_feature(enable = "avx512cd")]
186#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
187#[cfg_attr(test, assert_instr(vpconflictq))]
188pub unsafe fn _mm512_conflict_epi64(a: __m512i) -> __m512i {
189 transmute(src:vpconflictq(a.as_i64x8()))
190}
191
192/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
193///
194/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi64&expand=1258)
195#[inline]
196#[target_feature(enable = "avx512cd")]
197#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
198#[cfg_attr(test, assert_instr(vpconflictq))]
199pub unsafe fn _mm512_mask_conflict_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
200 let conflict: i64x8 = _mm512_conflict_epi64(a).as_i64x8();
201 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:src.as_i64x8()))
202}
203
204/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
205///
206/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi64&expand=1259)
207#[inline]
208#[target_feature(enable = "avx512cd")]
209#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
210#[cfg_attr(test, assert_instr(vpconflictq))]
211pub unsafe fn _mm512_maskz_conflict_epi64(k: __mmask8, a: __m512i) -> __m512i {
212 let conflict: i64x8 = _mm512_conflict_epi64(a).as_i64x8();
213 let zero: i64x8 = _mm512_setzero_si512().as_i64x8();
214 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:zero))
215}
216
217/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
218///
219/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi64&expand=1254)
220#[inline]
221#[target_feature(enable = "avx512cd,avx512vl")]
222#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
223#[cfg_attr(test, assert_instr(vpconflictq))]
224pub unsafe fn _mm256_conflict_epi64(a: __m256i) -> __m256i {
225 transmute(src:vpconflictq256(a.as_i64x4()))
226}
227
228/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
229///
230/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi64&expand=1255)
231#[inline]
232#[target_feature(enable = "avx512cd,avx512vl")]
233#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
234#[cfg_attr(test, assert_instr(vpconflictq))]
235pub unsafe fn _mm256_mask_conflict_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
236 let conflict: i64x4 = _mm256_conflict_epi64(a).as_i64x4();
237 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:src.as_i64x4()))
238}
239
240/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
241///
242/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi64&expand=1256)
243#[inline]
244#[target_feature(enable = "avx512cd,avx512vl")]
245#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
246#[cfg_attr(test, assert_instr(vpconflictq))]
247pub unsafe fn _mm256_maskz_conflict_epi64(k: __mmask8, a: __m256i) -> __m256i {
248 let conflict: i64x4 = _mm256_conflict_epi64(a).as_i64x4();
249 let zero: i64x4 = _mm256_setzero_si256().as_i64x4();
250 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:zero))
251}
252
253/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
254///
255/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi64&expand=1251)
256#[inline]
257#[target_feature(enable = "avx512cd,avx512vl")]
258#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
259#[cfg_attr(test, assert_instr(vpconflictq))]
260pub unsafe fn _mm_conflict_epi64(a: __m128i) -> __m128i {
261 transmute(src:vpconflictq128(a.as_i64x2()))
262}
263
264/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
265///
266/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi64&expand=1252)
267#[inline]
268#[target_feature(enable = "avx512cd,avx512vl")]
269#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
270#[cfg_attr(test, assert_instr(vpconflictq))]
271pub unsafe fn _mm_mask_conflict_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
272 let conflict: i64x2 = _mm_conflict_epi64(a).as_i64x2();
273 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:src.as_i64x2()))
274}
275
276/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
277///
278/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi64&expand=1253)
279#[inline]
280#[target_feature(enable = "avx512cd,avx512vl")]
281#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
282#[cfg_attr(test, assert_instr(vpconflictq))]
283pub unsafe fn _mm_maskz_conflict_epi64(k: __mmask8, a: __m128i) -> __m128i {
284 let conflict: i64x2 = _mm_conflict_epi64(a).as_i64x2();
285 let zero: i64x2 = _mm_setzero_si128().as_i64x2();
286 transmute(src:simd_select_bitmask(m:k, yes:conflict, no:zero))
287}
288
289/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
290///
291/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi32&expand=3491)
292#[inline]
293#[target_feature(enable = "avx512cd")]
294#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
295#[cfg_attr(test, assert_instr(vplzcntd))]
296pub unsafe fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i {
297 transmute(src:vplzcntd(a:a.as_i32x16(), nonzero:false))
298}
299
300/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
301///
302/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi32&expand=3492)
303#[inline]
304#[target_feature(enable = "avx512cd")]
305#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
306#[cfg_attr(test, assert_instr(vplzcntd))]
307pub unsafe fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
308 let zerocount: i32x16 = _mm512_lzcnt_epi32(a).as_i32x16();
309 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:src.as_i32x16()))
310}
311
312/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
313///
314/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi32&expand=3493)
315#[inline]
316#[target_feature(enable = "avx512cd")]
317#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
318#[cfg_attr(test, assert_instr(vplzcntd))]
319pub unsafe fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
320 let zerocount: i32x16 = _mm512_lzcnt_epi32(a).as_i32x16();
321 let zero: i32x16 = _mm512_setzero_si512().as_i32x16();
322 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:zero))
323}
324
325/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
326///
327/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi32&expand=3488)
328#[inline]
329#[target_feature(enable = "avx512cd,avx512vl")]
330#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
331#[cfg_attr(test, assert_instr(vplzcntd))]
332pub unsafe fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i {
333 transmute(src:vplzcntd256(a:a.as_i32x8(), nonzero:false))
334}
335
336/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
337///
338/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi32&expand=3489)
339#[inline]
340#[target_feature(enable = "avx512cd,avx512vl")]
341#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
342#[cfg_attr(test, assert_instr(vplzcntd))]
343pub unsafe fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
344 let zerocount: i32x8 = _mm256_lzcnt_epi32(a).as_i32x8();
345 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:src.as_i32x8()))
346}
347
348/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
349///
350/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi32&expand=3490)
351#[inline]
352#[target_feature(enable = "avx512cd,avx512vl")]
353#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
354#[cfg_attr(test, assert_instr(vplzcntd))]
355pub unsafe fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
356 let zerocount: i32x8 = _mm256_lzcnt_epi32(a).as_i32x8();
357 let zero: i32x8 = _mm256_setzero_si256().as_i32x8();
358 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:zero))
359}
360
361/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
362///
363/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi32&expand=3485)
364#[inline]
365#[target_feature(enable = "avx512cd,avx512vl")]
366#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
367#[cfg_attr(test, assert_instr(vplzcntd))]
368pub unsafe fn _mm_lzcnt_epi32(a: __m128i) -> __m128i {
369 transmute(src:vplzcntd128(a:a.as_i32x4(), nonzero:false))
370}
371
372/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
373///
374/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi32&expand=3486)
375#[inline]
376#[target_feature(enable = "avx512cd,avx512vl")]
377#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
378#[cfg_attr(test, assert_instr(vplzcntd))]
379pub unsafe fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
380 let zerocount: i32x4 = _mm_lzcnt_epi32(a).as_i32x4();
381 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:src.as_i32x4()))
382}
383
384/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
385///
386/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi32&expand=3487)
387#[inline]
388#[target_feature(enable = "avx512cd,avx512vl")]
389#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
390#[cfg_attr(test, assert_instr(vplzcntd))]
391pub unsafe fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
392 let zerocount: i32x4 = _mm_lzcnt_epi32(a).as_i32x4();
393 let zero: i32x4 = _mm_setzero_si128().as_i32x4();
394 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:zero))
395}
396
397/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
398///
399/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi64&expand=3500)
400#[inline]
401#[target_feature(enable = "avx512cd")]
402#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
403#[cfg_attr(test, assert_instr(vplzcntq))]
404pub unsafe fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i {
405 transmute(src:vplzcntq(a:a.as_i64x8(), nonzero:false))
406}
407
408/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
409///
410/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi64&expand=3501)
411#[inline]
412#[target_feature(enable = "avx512cd")]
413#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
414#[cfg_attr(test, assert_instr(vplzcntq))]
415pub unsafe fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
416 let zerocount: i64x8 = _mm512_lzcnt_epi64(a).as_i64x8();
417 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:src.as_i64x8()))
418}
419
420/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
421///
422/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi64&expand=3502)
423#[inline]
424#[target_feature(enable = "avx512cd")]
425#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
426#[cfg_attr(test, assert_instr(vplzcntq))]
427pub unsafe fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
428 let zerocount: i64x8 = _mm512_lzcnt_epi64(a).as_i64x8();
429 let zero: i64x8 = _mm512_setzero_si512().as_i64x8();
430 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:zero))
431}
432
433/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
434///
435/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi64&expand=3497)
436#[inline]
437#[target_feature(enable = "avx512cd,avx512vl")]
438#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
439#[cfg_attr(test, assert_instr(vplzcntq))]
440pub unsafe fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i {
441 transmute(src:vplzcntq256(a:a.as_i64x4(), nonzero:false))
442}
443
444/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
445///
446/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi64&expand=3498)
447#[inline]
448#[target_feature(enable = "avx512cd,avx512vl")]
449#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
450#[cfg_attr(test, assert_instr(vplzcntq))]
451pub unsafe fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
452 let zerocount: i64x4 = _mm256_lzcnt_epi64(a).as_i64x4();
453 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:src.as_i64x4()))
454}
455
456/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
457///
458/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi64&expand=3499)
459#[inline]
460#[target_feature(enable = "avx512cd,avx512vl")]
461#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
462#[cfg_attr(test, assert_instr(vplzcntq))]
463pub unsafe fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
464 let zerocount: i64x4 = _mm256_lzcnt_epi64(a).as_i64x4();
465 let zero: i64x4 = _mm256_setzero_si256().as_i64x4();
466 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:zero))
467}
468
469/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
470///
471/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi64&expand=3494)
472#[inline]
473#[target_feature(enable = "avx512cd,avx512vl")]
474#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
475#[cfg_attr(test, assert_instr(vplzcntq))]
476pub unsafe fn _mm_lzcnt_epi64(a: __m128i) -> __m128i {
477 transmute(src:vplzcntq128(a:a.as_i64x2(), nonzero:false))
478}
479
480/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
481///
482/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi64&expand=3495)
483#[inline]
484#[target_feature(enable = "avx512cd,avx512vl")]
485#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
486#[cfg_attr(test, assert_instr(vplzcntq))]
487pub unsafe fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
488 let zerocount: i64x2 = _mm_lzcnt_epi64(a).as_i64x2();
489 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:src.as_i64x2()))
490}
491
492/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
493///
494/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi64&expand=3496)
495#[inline]
496#[target_feature(enable = "avx512cd,avx512vl")]
497#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
498#[cfg_attr(test, assert_instr(vplzcntq))]
499pub unsafe fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
500 let zerocount: i64x2 = _mm_lzcnt_epi64(a).as_i64x2();
501 let zero: i64x2 = _mm_setzero_si128().as_i64x2();
502 transmute(src:simd_select_bitmask(m:k, yes:zerocount, no:zero))
503}
504
505#[allow(improper_ctypes)]
506extern "C" {
507 #[link_name = "llvm.x86.avx512.conflict.d.512"]
508 fn vpconflictd(a: i32x16) -> i32x16;
509 #[link_name = "llvm.x86.avx512.conflict.d.256"]
510 fn vpconflictd256(a: i32x8) -> i32x8;
511 #[link_name = "llvm.x86.avx512.conflict.d.128"]
512 fn vpconflictd128(a: i32x4) -> i32x4;
513
514 #[link_name = "llvm.x86.avx512.conflict.q.512"]
515 fn vpconflictq(a: i64x8) -> i64x8;
516 #[link_name = "llvm.x86.avx512.conflict.q.256"]
517 fn vpconflictq256(a: i64x4) -> i64x4;
518 #[link_name = "llvm.x86.avx512.conflict.q.128"]
519 fn vpconflictq128(a: i64x2) -> i64x2;
520
521 #[link_name = "llvm.ctlz.v16i32"]
522 fn vplzcntd(a: i32x16, nonzero: bool) -> i32x16;
523 #[link_name = "llvm.ctlz.v8i32"]
524 fn vplzcntd256(a: i32x8, nonzero: bool) -> i32x8;
525 #[link_name = "llvm.ctlz.v4i32"]
526 fn vplzcntd128(a: i32x4, nonzero: bool) -> i32x4;
527
528 #[link_name = "llvm.ctlz.v8i64"]
529 fn vplzcntq(a: i64x8, nonzero: bool) -> i64x8;
530 #[link_name = "llvm.ctlz.v4i64"]
531 fn vplzcntq256(a: i64x4, nonzero: bool) -> i64x4;
532 #[link_name = "llvm.ctlz.v2i64"]
533 fn vplzcntq128(a: i64x2, nonzero: bool) -> i64x2;
534}
535
536#[cfg(test)]
537mod tests {
538
539 use crate::core_arch::x86::*;
540 use stdarch_test::simd_test;
541
542 #[simd_test(enable = "avx512cd")]
543 unsafe fn test_mm512_broadcastmw_epi32() {
544 let a: __mmask16 = 2;
545 let r = _mm512_broadcastmw_epi32(a);
546 let e = _mm512_set1_epi32(2);
547 assert_eq_m512i(r, e);
548 }
549
550 #[simd_test(enable = "avx512cd,avx512vl")]
551 unsafe fn test_mm256_broadcastmw_epi32() {
552 let a: __mmask16 = 2;
553 let r = _mm256_broadcastmw_epi32(a);
554 let e = _mm256_set1_epi32(2);
555 assert_eq_m256i(r, e);
556 }
557
558 #[simd_test(enable = "avx512cd,avx512vl")]
559 unsafe fn test_mm_broadcastmw_epi32() {
560 let a: __mmask16 = 2;
561 let r = _mm_broadcastmw_epi32(a);
562 let e = _mm_set1_epi32(2);
563 assert_eq_m128i(r, e);
564 }
565
566 #[simd_test(enable = "avx512cd")]
567 unsafe fn test_mm512_broadcastmb_epi64() {
568 let a: __mmask8 = 2;
569 let r = _mm512_broadcastmb_epi64(a);
570 let e = _mm512_set1_epi64(2);
571 assert_eq_m512i(r, e);
572 }
573
574 #[simd_test(enable = "avx512cd,avx512vl")]
575 unsafe fn test_mm256_broadcastmb_epi64() {
576 let a: __mmask8 = 2;
577 let r = _mm256_broadcastmb_epi64(a);
578 let e = _mm256_set1_epi64x(2);
579 assert_eq_m256i(r, e);
580 }
581
582 #[simd_test(enable = "avx512cd,avx512vl")]
583 unsafe fn test_mm_broadcastmb_epi64() {
584 let a: __mmask8 = 2;
585 let r = _mm_broadcastmb_epi64(a);
586 let e = _mm_set1_epi64x(2);
587 assert_eq_m128i(r, e);
588 }
589
590 #[simd_test(enable = "avx512cd")]
591 unsafe fn test_mm512_conflict_epi32() {
592 let a = _mm512_set1_epi32(1);
593 let r = _mm512_conflict_epi32(a);
594 let e = _mm512_set_epi32(
595 1 << 14
596 | 1 << 13
597 | 1 << 12
598 | 1 << 11
599 | 1 << 10
600 | 1 << 9
601 | 1 << 8
602 | 1 << 7
603 | 1 << 6
604 | 1 << 5
605 | 1 << 4
606 | 1 << 3
607 | 1 << 2
608 | 1 << 1
609 | 1 << 0,
610 1 << 13
611 | 1 << 12
612 | 1 << 11
613 | 1 << 10
614 | 1 << 9
615 | 1 << 8
616 | 1 << 7
617 | 1 << 6
618 | 1 << 5
619 | 1 << 4
620 | 1 << 3
621 | 1 << 2
622 | 1 << 1
623 | 1 << 0,
624 1 << 12
625 | 1 << 11
626 | 1 << 10
627 | 1 << 9
628 | 1 << 8
629 | 1 << 7
630 | 1 << 6
631 | 1 << 5
632 | 1 << 4
633 | 1 << 3
634 | 1 << 2
635 | 1 << 1
636 | 1 << 0,
637 1 << 11
638 | 1 << 10
639 | 1 << 9
640 | 1 << 8
641 | 1 << 7
642 | 1 << 6
643 | 1 << 5
644 | 1 << 4
645 | 1 << 3
646 | 1 << 2
647 | 1 << 1
648 | 1 << 0,
649 1 << 10
650 | 1 << 9
651 | 1 << 8
652 | 1 << 7
653 | 1 << 6
654 | 1 << 5
655 | 1 << 4
656 | 1 << 3
657 | 1 << 2
658 | 1 << 1
659 | 1 << 0,
660 1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
661 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
662 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
663 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
664 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
665 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
666 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
667 1 << 2 | 1 << 1 | 1 << 0,
668 1 << 1 | 1 << 0,
669 1 << 0,
670 0,
671 );
672 assert_eq_m512i(r, e);
673 }
674
675 #[simd_test(enable = "avx512cd")]
676 unsafe fn test_mm512_mask_conflict_epi32() {
677 let a = _mm512_set1_epi32(1);
678 let r = _mm512_mask_conflict_epi32(a, 0, a);
679 assert_eq_m512i(r, a);
680 let r = _mm512_mask_conflict_epi32(a, 0b11111111_11111111, a);
681 let e = _mm512_set_epi32(
682 1 << 14
683 | 1 << 13
684 | 1 << 12
685 | 1 << 11
686 | 1 << 10
687 | 1 << 9
688 | 1 << 8
689 | 1 << 7
690 | 1 << 6
691 | 1 << 5
692 | 1 << 4
693 | 1 << 3
694 | 1 << 2
695 | 1 << 1
696 | 1 << 0,
697 1 << 13
698 | 1 << 12
699 | 1 << 11
700 | 1 << 10
701 | 1 << 9
702 | 1 << 8
703 | 1 << 7
704 | 1 << 6
705 | 1 << 5
706 | 1 << 4
707 | 1 << 3
708 | 1 << 2
709 | 1 << 1
710 | 1 << 0,
711 1 << 12
712 | 1 << 11
713 | 1 << 10
714 | 1 << 9
715 | 1 << 8
716 | 1 << 7
717 | 1 << 6
718 | 1 << 5
719 | 1 << 4
720 | 1 << 3
721 | 1 << 2
722 | 1 << 1
723 | 1 << 0,
724 1 << 11
725 | 1 << 10
726 | 1 << 9
727 | 1 << 8
728 | 1 << 7
729 | 1 << 6
730 | 1 << 5
731 | 1 << 4
732 | 1 << 3
733 | 1 << 2
734 | 1 << 1
735 | 1 << 0,
736 1 << 10
737 | 1 << 9
738 | 1 << 8
739 | 1 << 7
740 | 1 << 6
741 | 1 << 5
742 | 1 << 4
743 | 1 << 3
744 | 1 << 2
745 | 1 << 1
746 | 1 << 0,
747 1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
748 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
749 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
750 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
751 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
752 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
753 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
754 1 << 2 | 1 << 1 | 1 << 0,
755 1 << 1 | 1 << 0,
756 1 << 0,
757 0,
758 );
759 assert_eq_m512i(r, e);
760 }
761
762 #[simd_test(enable = "avx512cd")]
763 unsafe fn test_mm512_maskz_conflict_epi32() {
764 let a = _mm512_set1_epi32(1);
765 let r = _mm512_maskz_conflict_epi32(0, a);
766 assert_eq_m512i(r, _mm512_setzero_si512());
767 let r = _mm512_maskz_conflict_epi32(0b11111111_11111111, a);
768 let e = _mm512_set_epi32(
769 1 << 14
770 | 1 << 13
771 | 1 << 12
772 | 1 << 11
773 | 1 << 10
774 | 1 << 9
775 | 1 << 8
776 | 1 << 7
777 | 1 << 6
778 | 1 << 5
779 | 1 << 4
780 | 1 << 3
781 | 1 << 2
782 | 1 << 1
783 | 1 << 0,
784 1 << 13
785 | 1 << 12
786 | 1 << 11
787 | 1 << 10
788 | 1 << 9
789 | 1 << 8
790 | 1 << 7
791 | 1 << 6
792 | 1 << 5
793 | 1 << 4
794 | 1 << 3
795 | 1 << 2
796 | 1 << 1
797 | 1 << 0,
798 1 << 12
799 | 1 << 11
800 | 1 << 10
801 | 1 << 9
802 | 1 << 8
803 | 1 << 7
804 | 1 << 6
805 | 1 << 5
806 | 1 << 4
807 | 1 << 3
808 | 1 << 2
809 | 1 << 1
810 | 1 << 0,
811 1 << 11
812 | 1 << 10
813 | 1 << 9
814 | 1 << 8
815 | 1 << 7
816 | 1 << 6
817 | 1 << 5
818 | 1 << 4
819 | 1 << 3
820 | 1 << 2
821 | 1 << 1
822 | 1 << 0,
823 1 << 10
824 | 1 << 9
825 | 1 << 8
826 | 1 << 7
827 | 1 << 6
828 | 1 << 5
829 | 1 << 4
830 | 1 << 3
831 | 1 << 2
832 | 1 << 1
833 | 1 << 0,
834 1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
835 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
836 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
837 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
838 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
839 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
840 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
841 1 << 2 | 1 << 1 | 1 << 0,
842 1 << 1 | 1 << 0,
843 1 << 0,
844 0,
845 );
846 assert_eq_m512i(r, e);
847 }
848
849 #[simd_test(enable = "avx512cd,avx512vl")]
850 unsafe fn test_mm256_conflict_epi32() {
851 let a = _mm256_set1_epi32(1);
852 let r = _mm256_conflict_epi32(a);
853 let e = _mm256_set_epi32(
854 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
855 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
856 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
857 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
858 1 << 2 | 1 << 1 | 1 << 0,
859 1 << 1 | 1 << 0,
860 1 << 0,
861 0,
862 );
863 assert_eq_m256i(r, e);
864 }
865
866 #[simd_test(enable = "avx512cd,avx512vl")]
867 unsafe fn test_mm256_mask_conflict_epi32() {
868 let a = _mm256_set1_epi32(1);
869 let r = _mm256_mask_conflict_epi32(a, 0, a);
870 assert_eq_m256i(r, a);
871 let r = _mm256_mask_conflict_epi32(a, 0b11111111, a);
872 let e = _mm256_set_epi32(
873 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
874 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
875 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
876 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
877 1 << 2 | 1 << 1 | 1 << 0,
878 1 << 1 | 1 << 0,
879 1 << 0,
880 0,
881 );
882 assert_eq_m256i(r, e);
883 }
884
885 #[simd_test(enable = "avx512cd,avx512vl")]
886 unsafe fn test_mm256_maskz_conflict_epi32() {
887 let a = _mm256_set1_epi32(1);
888 let r = _mm256_maskz_conflict_epi32(0, a);
889 assert_eq_m256i(r, _mm256_setzero_si256());
890 let r = _mm256_maskz_conflict_epi32(0b11111111, a);
891 let e = _mm256_set_epi32(
892 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
893 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
894 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
895 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
896 1 << 2 | 1 << 1 | 1 << 0,
897 1 << 1 | 1 << 0,
898 1 << 0,
899 0,
900 );
901 assert_eq_m256i(r, e);
902 }
903
904 #[simd_test(enable = "avx512cd,avx512vl")]
905 unsafe fn test_mm_conflict_epi32() {
906 let a = _mm_set1_epi32(1);
907 let r = _mm_conflict_epi32(a);
908 let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
909 assert_eq_m128i(r, e);
910 }
911
912 #[simd_test(enable = "avx512cd,avx512vl")]
913 unsafe fn test_mm_mask_conflict_epi32() {
914 let a = _mm_set1_epi32(1);
915 let r = _mm_mask_conflict_epi32(a, 0, a);
916 assert_eq_m128i(r, a);
917 let r = _mm_mask_conflict_epi32(a, 0b00001111, a);
918 let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
919 assert_eq_m128i(r, e);
920 }
921
922 #[simd_test(enable = "avx512cd,avx512vl")]
923 unsafe fn test_mm_maskz_conflict_epi32() {
924 let a = _mm_set1_epi32(1);
925 let r = _mm_maskz_conflict_epi32(0, a);
926 assert_eq_m128i(r, _mm_setzero_si128());
927 let r = _mm_maskz_conflict_epi32(0b00001111, a);
928 let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
929 assert_eq_m128i(r, e);
930 }
931
932 #[simd_test(enable = "avx512cd")]
933 unsafe fn test_mm512_conflict_epi64() {
934 let a = _mm512_set1_epi64(1);
935 let r = _mm512_conflict_epi64(a);
936 let e = _mm512_set_epi64(
937 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
938 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
939 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
940 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
941 1 << 2 | 1 << 1 | 1 << 0,
942 1 << 1 | 1 << 0,
943 1 << 0,
944 0,
945 );
946 assert_eq_m512i(r, e);
947 }
948
949 #[simd_test(enable = "avx512cd")]
950 unsafe fn test_mm512_mask_conflict_epi64() {
951 let a = _mm512_set1_epi64(1);
952 let r = _mm512_mask_conflict_epi64(a, 0, a);
953 assert_eq_m512i(r, a);
954 let r = _mm512_mask_conflict_epi64(a, 0b11111111, a);
955 let e = _mm512_set_epi64(
956 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
957 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
958 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
959 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
960 1 << 2 | 1 << 1 | 1 << 0,
961 1 << 1 | 1 << 0,
962 1 << 0,
963 0,
964 );
965 assert_eq_m512i(r, e);
966 }
967
968 #[simd_test(enable = "avx512cd")]
969 unsafe fn test_mm512_maskz_conflict_epi64() {
970 let a = _mm512_set1_epi64(1);
971 let r = _mm512_maskz_conflict_epi64(0, a);
972 assert_eq_m512i(r, _mm512_setzero_si512());
973 let r = _mm512_maskz_conflict_epi64(0b11111111, a);
974 let e = _mm512_set_epi64(
975 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
976 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
977 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
978 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
979 1 << 2 | 1 << 1 | 1 << 0,
980 1 << 1 | 1 << 0,
981 1 << 0,
982 0,
983 );
984 assert_eq_m512i(r, e);
985 }
986
987 #[simd_test(enable = "avx512cd,avx512vl")]
988 unsafe fn test_mm256_conflict_epi64() {
989 let a = _mm256_set1_epi64x(1);
990 let r = _mm256_conflict_epi64(a);
991 let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
992 assert_eq_m256i(r, e);
993 }
994
995 #[simd_test(enable = "avx512cd,avx512vl")]
996 unsafe fn test_mm256_mask_conflict_epi64() {
997 let a = _mm256_set1_epi64x(1);
998 let r = _mm256_mask_conflict_epi64(a, 0, a);
999 assert_eq_m256i(r, a);
1000 let r = _mm256_mask_conflict_epi64(a, 0b00001111, a);
1001 let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
1002 assert_eq_m256i(r, e);
1003 }
1004
1005 #[simd_test(enable = "avx512cd,avx512vl")]
1006 unsafe fn test_mm256_maskz_conflict_epi64() {
1007 let a = _mm256_set1_epi64x(1);
1008 let r = _mm256_maskz_conflict_epi64(0, a);
1009 assert_eq_m256i(r, _mm256_setzero_si256());
1010 let r = _mm256_maskz_conflict_epi64(0b00001111, a);
1011 let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
1012 assert_eq_m256i(r, e);
1013 }
1014
1015 #[simd_test(enable = "avx512cd,avx512vl")]
1016 unsafe fn test_mm_conflict_epi64() {
1017 let a = _mm_set1_epi64x(1);
1018 let r = _mm_conflict_epi64(a);
1019 let e = _mm_set_epi64x(1 << 0, 0);
1020 assert_eq_m128i(r, e);
1021 }
1022
1023 #[simd_test(enable = "avx512cd,avx512vl")]
1024 unsafe fn test_mm_mask_conflict_epi64() {
1025 let a = _mm_set1_epi64x(1);
1026 let r = _mm_mask_conflict_epi64(a, 0, a);
1027 assert_eq_m128i(r, a);
1028 let r = _mm_mask_conflict_epi64(a, 0b00000011, a);
1029 let e = _mm_set_epi64x(1 << 0, 0);
1030 assert_eq_m128i(r, e);
1031 }
1032
1033 #[simd_test(enable = "avx512cd,avx512vl")]
1034 unsafe fn test_mm_maskz_conflict_epi64() {
1035 let a = _mm_set1_epi64x(1);
1036 let r = _mm_maskz_conflict_epi64(0, a);
1037 assert_eq_m128i(r, _mm_setzero_si128());
1038 let r = _mm_maskz_conflict_epi64(0b00000011, a);
1039 let e = _mm_set_epi64x(1 << 0, 0);
1040 assert_eq_m128i(r, e);
1041 }
1042
1043 #[simd_test(enable = "avx512cd")]
1044 unsafe fn test_mm512_lzcnt_epi32() {
1045 let a = _mm512_set1_epi32(1);
1046 let r = _mm512_lzcnt_epi32(a);
1047 let e = _mm512_set1_epi32(31);
1048 assert_eq_m512i(r, e);
1049 }
1050
1051 #[simd_test(enable = "avx512cd")]
1052 unsafe fn test_mm512_mask_lzcnt_epi32() {
1053 let a = _mm512_set1_epi32(1);
1054 let r = _mm512_mask_lzcnt_epi32(a, 0, a);
1055 assert_eq_m512i(r, a);
1056 let r = _mm512_mask_lzcnt_epi32(a, 0b11111111_11111111, a);
1057 let e = _mm512_set1_epi32(31);
1058 assert_eq_m512i(r, e);
1059 }
1060
1061 #[simd_test(enable = "avx512cd")]
1062 unsafe fn test_mm512_maskz_lzcnt_epi32() {
1063 let a = _mm512_set1_epi32(2);
1064 let r = _mm512_maskz_lzcnt_epi32(0, a);
1065 assert_eq_m512i(r, _mm512_setzero_si512());
1066 let r = _mm512_maskz_lzcnt_epi32(0b11111111_11111111, a);
1067 let e = _mm512_set1_epi32(30);
1068 assert_eq_m512i(r, e);
1069 }
1070
1071 #[simd_test(enable = "avx512cd,avx512vl")]
1072 unsafe fn test_mm256_lzcnt_epi32() {
1073 let a = _mm256_set1_epi32(1);
1074 let r = _mm256_lzcnt_epi32(a);
1075 let e = _mm256_set1_epi32(31);
1076 assert_eq_m256i(r, e);
1077 }
1078
1079 #[simd_test(enable = "avx512cd,avx512vl")]
1080 unsafe fn test_mm256_mask_lzcnt_epi32() {
1081 let a = _mm256_set1_epi32(1);
1082 let r = _mm256_mask_lzcnt_epi32(a, 0, a);
1083 assert_eq_m256i(r, a);
1084 let r = _mm256_mask_lzcnt_epi32(a, 0b11111111, a);
1085 let e = _mm256_set1_epi32(31);
1086 assert_eq_m256i(r, e);
1087 }
1088
1089 #[simd_test(enable = "avx512cd,avx512vl")]
1090 unsafe fn test_mm256_maskz_lzcnt_epi32() {
1091 let a = _mm256_set1_epi32(1);
1092 let r = _mm256_maskz_lzcnt_epi32(0, a);
1093 assert_eq_m256i(r, _mm256_setzero_si256());
1094 let r = _mm256_maskz_lzcnt_epi32(0b11111111, a);
1095 let e = _mm256_set1_epi32(31);
1096 assert_eq_m256i(r, e);
1097 }
1098
1099 #[simd_test(enable = "avx512cd,avx512vl")]
1100 unsafe fn test_mm_lzcnt_epi32() {
1101 let a = _mm_set1_epi32(1);
1102 let r = _mm_lzcnt_epi32(a);
1103 let e = _mm_set1_epi32(31);
1104 assert_eq_m128i(r, e);
1105 }
1106
1107 #[simd_test(enable = "avx512cd,avx512vl")]
1108 unsafe fn test_mm_mask_lzcnt_epi32() {
1109 let a = _mm_set1_epi32(1);
1110 let r = _mm_mask_lzcnt_epi32(a, 0, a);
1111 assert_eq_m128i(r, a);
1112 let r = _mm_mask_lzcnt_epi32(a, 0b00001111, a);
1113 let e = _mm_set1_epi32(31);
1114 assert_eq_m128i(r, e);
1115 }
1116
1117 #[simd_test(enable = "avx512cd,avx512vl")]
1118 unsafe fn test_mm_maskz_lzcnt_epi32() {
1119 let a = _mm_set1_epi32(1);
1120 let r = _mm_maskz_lzcnt_epi32(0, a);
1121 assert_eq_m128i(r, _mm_setzero_si128());
1122 let r = _mm_maskz_lzcnt_epi32(0b00001111, a);
1123 let e = _mm_set1_epi32(31);
1124 assert_eq_m128i(r, e);
1125 }
1126
1127 #[simd_test(enable = "avx512cd")]
1128 unsafe fn test_mm512_lzcnt_epi64() {
1129 let a = _mm512_set1_epi64(1);
1130 let r = _mm512_lzcnt_epi64(a);
1131 let e = _mm512_set1_epi64(63);
1132 assert_eq_m512i(r, e);
1133 }
1134
1135 #[simd_test(enable = "avx512cd")]
1136 unsafe fn test_mm512_mask_lzcnt_epi64() {
1137 let a = _mm512_set1_epi64(1);
1138 let r = _mm512_mask_lzcnt_epi64(a, 0, a);
1139 assert_eq_m512i(r, a);
1140 let r = _mm512_mask_lzcnt_epi64(a, 0b11111111, a);
1141 let e = _mm512_set1_epi64(63);
1142 assert_eq_m512i(r, e);
1143 }
1144
1145 #[simd_test(enable = "avx512cd")]
1146 unsafe fn test_mm512_maskz_lzcnt_epi64() {
1147 let a = _mm512_set1_epi64(2);
1148 let r = _mm512_maskz_lzcnt_epi64(0, a);
1149 assert_eq_m512i(r, _mm512_setzero_si512());
1150 let r = _mm512_maskz_lzcnt_epi64(0b11111111, a);
1151 let e = _mm512_set1_epi64(62);
1152 assert_eq_m512i(r, e);
1153 }
1154
1155 #[simd_test(enable = "avx512cd,avx512vl")]
1156 unsafe fn test_mm256_lzcnt_epi64() {
1157 let a = _mm256_set1_epi64x(1);
1158 let r = _mm256_lzcnt_epi64(a);
1159 let e = _mm256_set1_epi64x(63);
1160 assert_eq_m256i(r, e);
1161 }
1162
1163 #[simd_test(enable = "avx512cd,avx512vl")]
1164 unsafe fn test_mm256_mask_lzcnt_epi64() {
1165 let a = _mm256_set1_epi64x(1);
1166 let r = _mm256_mask_lzcnt_epi64(a, 0, a);
1167 assert_eq_m256i(r, a);
1168 let r = _mm256_mask_lzcnt_epi64(a, 0b00001111, a);
1169 let e = _mm256_set1_epi64x(63);
1170 assert_eq_m256i(r, e);
1171 }
1172
1173 #[simd_test(enable = "avx512cd,avx512vl")]
1174 unsafe fn test_mm256_maskz_lzcnt_epi64() {
1175 let a = _mm256_set1_epi64x(1);
1176 let r = _mm256_maskz_lzcnt_epi64(0, a);
1177 assert_eq_m256i(r, _mm256_setzero_si256());
1178 let r = _mm256_maskz_lzcnt_epi64(0b00001111, a);
1179 let e = _mm256_set1_epi64x(63);
1180 assert_eq_m256i(r, e);
1181 }
1182
1183 #[simd_test(enable = "avx512cd,avx512vl")]
1184 unsafe fn test_mm_lzcnt_epi64() {
1185 let a = _mm_set1_epi64x(1);
1186 let r = _mm_lzcnt_epi64(a);
1187 let e = _mm_set1_epi64x(63);
1188 assert_eq_m128i(r, e);
1189 }
1190
1191 #[simd_test(enable = "avx512cd,avx512vl")]
1192 unsafe fn test_mm_mask_lzcnt_epi64() {
1193 let a = _mm_set1_epi64x(1);
1194 let r = _mm_mask_lzcnt_epi64(a, 0, a);
1195 assert_eq_m128i(r, a);
1196 let r = _mm_mask_lzcnt_epi64(a, 0b00001111, a);
1197 let e = _mm_set1_epi64x(63);
1198 assert_eq_m128i(r, e);
1199 }
1200
1201 #[simd_test(enable = "avx512cd,avx512vl")]
1202 unsafe fn test_mm_maskz_lzcnt_epi64() {
1203 let a = _mm_set1_epi64x(1);
1204 let r = _mm_maskz_lzcnt_epi64(0, a);
1205 assert_eq_m128i(r, _mm_setzero_si128());
1206 let r = _mm_maskz_lzcnt_epi64(0b00001111, a);
1207 let e = _mm_set1_epi64x(63);
1208 assert_eq_m128i(r, e);
1209 }
1210}
1211