1 | //! Bit Manipulation Instruction (BMI) Set 1.0. |
2 | //! |
3 | //! The reference is [Intel 64 and IA-32 Architectures Software Developer's |
4 | //! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref]. |
5 | //! |
6 | //! [Wikipedia][wikipedia_bmi] provides a quick overview of the instructions |
7 | //! available. |
8 | //! |
9 | //! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf |
10 | //! [wikipedia_bmi]: https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_.28Advanced_Bit_Manipulation.29 |
11 | |
12 | #[cfg (test)] |
13 | use stdarch_test::assert_instr; |
14 | |
15 | /// Extracts bits in range [`start`, `start` + `length`) from `a` into |
16 | /// the least significant bits of the result. |
17 | /// |
18 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_bextr_u64) |
19 | #[inline ] |
20 | #[target_feature (enable = "bmi1" )] |
21 | #[cfg_attr (test, assert_instr(bextr))] |
22 | #[cfg (not(target_arch = "x86" ))] |
23 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
24 | pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 { |
25 | _bextr2_u64(a, ((start & 0xff) | ((len & 0xff) << 8)) as u64) |
26 | } |
27 | |
28 | /// Extracts bits of `a` specified by `control` into |
29 | /// the least significant bits of the result. |
30 | /// |
31 | /// Bits `[7,0]` of `control` specify the index to the first bit in the range |
32 | /// to be extracted, and bits `[15,8]` specify the length of the range. |
33 | /// |
34 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_bextr2_u64) |
35 | #[inline ] |
36 | #[target_feature (enable = "bmi1" )] |
37 | #[cfg_attr (test, assert_instr(bextr))] |
38 | #[cfg (not(target_arch = "x86" ))] |
39 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
40 | pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 { |
41 | x86_bmi_bextr_64(x:a, y:control) |
42 | } |
43 | |
44 | /// Bitwise logical `AND` of inverted `a` with `b`. |
45 | /// |
46 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_andn_u64) |
47 | #[inline ] |
48 | #[target_feature (enable = "bmi1" )] |
49 | #[cfg_attr (test, assert_instr(andn))] |
50 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
51 | pub unsafe fn _andn_u64(a: u64, b: u64) -> u64 { |
52 | !a & b |
53 | } |
54 | |
55 | /// Extracts lowest set isolated bit. |
56 | /// |
57 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsi_u64) |
58 | #[inline ] |
59 | #[target_feature (enable = "bmi1" )] |
60 | #[cfg_attr (test, assert_instr(blsi))] |
61 | #[cfg (not(target_arch = "x86" ))] // generates lots of instructions |
62 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
63 | pub unsafe fn _blsi_u64(x: u64) -> u64 { |
64 | x & x.wrapping_neg() |
65 | } |
66 | |
67 | /// Gets mask up to lowest set bit. |
68 | /// |
69 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsmsk_u64) |
70 | #[inline ] |
71 | #[target_feature (enable = "bmi1" )] |
72 | #[cfg_attr (test, assert_instr(blsmsk))] |
73 | #[cfg (not(target_arch = "x86" ))] // generates lots of instructions |
74 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
75 | pub unsafe fn _blsmsk_u64(x: u64) -> u64 { |
76 | x ^ (x.wrapping_sub(1_u64)) |
77 | } |
78 | |
79 | /// Resets the lowest set bit of `x`. |
80 | /// |
81 | /// If `x` is sets CF. |
82 | /// |
83 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsr_u64) |
84 | #[inline ] |
85 | #[target_feature (enable = "bmi1" )] |
86 | #[cfg_attr (test, assert_instr(blsr))] |
87 | #[cfg (not(target_arch = "x86" ))] // generates lots of instructions |
88 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
89 | pub unsafe fn _blsr_u64(x: u64) -> u64 { |
90 | x & (x.wrapping_sub(1)) |
91 | } |
92 | |
93 | /// Counts the number of trailing least significant zero bits. |
94 | /// |
95 | /// When the source operand is `0`, it returns its size in bits. |
96 | /// |
97 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tzcnt_u64) |
98 | #[inline ] |
99 | #[target_feature (enable = "bmi1" )] |
100 | #[cfg_attr (test, assert_instr(tzcnt))] |
101 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
102 | pub unsafe fn _tzcnt_u64(x: u64) -> u64 { |
103 | x.trailing_zeros() as u64 |
104 | } |
105 | |
106 | /// Counts the number of trailing least significant zero bits. |
107 | /// |
108 | /// When the source operand is `0`, it returns its size in bits. |
109 | /// |
110 | /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_tzcnt_64) |
111 | #[inline ] |
112 | #[target_feature (enable = "bmi1" )] |
113 | #[cfg_attr (test, assert_instr(tzcnt))] |
114 | #[stable (feature = "simd_x86" , since = "1.27.0" )] |
115 | pub unsafe fn _mm_tzcnt_64(x: u64) -> i64 { |
116 | x.trailing_zeros() as i64 |
117 | } |
118 | |
119 | extern "C" { |
120 | #[link_name = "llvm.x86.bmi.bextr.64" ] |
121 | fn x86_bmi_bextr_64(x: u64, y: u64) -> u64; |
122 | } |
123 | |
124 | #[cfg (test)] |
125 | mod tests { |
126 | use stdarch_test::simd_test; |
127 | |
128 | use crate::core_arch::{x86::*, x86_64::*}; |
129 | |
130 | #[simd_test(enable = "bmi1" )] |
131 | unsafe fn test_bextr_u64() { |
132 | let r = _bextr_u64(0b0101_0000u64, 4, 4); |
133 | assert_eq!(r, 0b0000_0101u64); |
134 | } |
135 | |
136 | #[simd_test(enable = "bmi1" )] |
137 | unsafe fn test_andn_u64() { |
138 | assert_eq!(_andn_u64(0, 0), 0); |
139 | assert_eq!(_andn_u64(0, 1), 1); |
140 | assert_eq!(_andn_u64(1, 0), 0); |
141 | assert_eq!(_andn_u64(1, 1), 0); |
142 | |
143 | let r = _andn_u64(0b0000_0000u64, 0b0000_0000u64); |
144 | assert_eq!(r, 0b0000_0000u64); |
145 | |
146 | let r = _andn_u64(0b0000_0000u64, 0b1111_1111u64); |
147 | assert_eq!(r, 0b1111_1111u64); |
148 | |
149 | let r = _andn_u64(0b1111_1111u64, 0b0000_0000u64); |
150 | assert_eq!(r, 0b0000_0000u64); |
151 | |
152 | let r = _andn_u64(0b1111_1111u64, 0b1111_1111u64); |
153 | assert_eq!(r, 0b0000_0000u64); |
154 | |
155 | let r = _andn_u64(0b0100_0000u64, 0b0101_1101u64); |
156 | assert_eq!(r, 0b0001_1101u64); |
157 | } |
158 | |
159 | #[simd_test(enable = "bmi1" )] |
160 | unsafe fn test_blsi_u64() { |
161 | assert_eq!(_blsi_u64(0b1101_0000u64), 0b0001_0000u64); |
162 | } |
163 | |
164 | #[simd_test(enable = "bmi1" )] |
165 | unsafe fn test_blsmsk_u64() { |
166 | let r = _blsmsk_u64(0b0011_0000u64); |
167 | assert_eq!(r, 0b0001_1111u64); |
168 | } |
169 | |
170 | #[simd_test(enable = "bmi1" )] |
171 | unsafe fn test_blsr_u64() { |
172 | // TODO: test the behavior when the input is `0`. |
173 | let r = _blsr_u64(0b0011_0000u64); |
174 | assert_eq!(r, 0b0010_0000u64); |
175 | } |
176 | |
177 | #[simd_test(enable = "bmi1" )] |
178 | unsafe fn test_tzcnt_u64() { |
179 | assert_eq!(_tzcnt_u64(0b0000_0001u64), 0u64); |
180 | assert_eq!(_tzcnt_u64(0b0000_0000u64), 64u64); |
181 | assert_eq!(_tzcnt_u64(0b1001_0000u64), 4u64); |
182 | } |
183 | } |
184 | |