rtl.def source code [gcc/rtl.def]

1	/ This file contains the definitions and documentation for the*
2	Register Transfer Expressions (rtx's) that make up the
3	Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4	Copyright (C) 1987-2023 Free Software Foundation, Inc.
5
6	This file is part of GCC.
7
8	GCC is free software; you can redistribute it and/or modify it under
9	the terms of the GNU General Public License as published by the Free
10	Software Foundation; either version 3, or (at your option) any later
11	version.
12
13	GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14	WARRANTY; without even the implied warranty of MERCHANTABILITY or
15	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16	for more details.
17
18	You should have received a copy of the GNU General Public License
19	along with GCC; see the file COPYING3. If not see
20	<http://www.gnu.org/licenses/>. /*
21
22
23	/ Expression definitions and descriptions for all targets are in this file.*
24	Some will not be used for some targets.
25
26	The fields in the cpp macro call "DEF_RTL_EXPR()"
27	are used to create declarations in the C source of the compiler.
28
29	The fields are:
30
31	1. The internal name of the rtx used in the C source.
32	It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33	By convention these are in UPPER_CASE.
34
35	2. The name of the rtx in the external ASCII format read by
36	read_rtx(), and printed by print_rtx().
37	These names are stored in rtx_name[].
38	By convention these are the internal (field 1) names in lower_case.
39
40	3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
41	These formats are stored in rtx_format[].
42	The meaning of the formats is documented in front of this array in rtl.cc
43
44	4. The class of the rtx. These are stored in rtx_class and are accessed
45	via the GET_RTX_CLASS macro. They are defined as follows:
46
47	RTX_CONST_OBJ
48	an rtx code that can be used to represent a constant object
49	(e.g, CONST_INT)
50	RTX_OBJ
51	an rtx code that can be used to represent an object (e.g, REG, MEM)
52	RTX_COMPARE
53	an rtx code for a comparison (e.g, LT, GT)
54	RTX_COMM_COMPARE
55	an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
56	RTX_UNARY
57	an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
58	RTX_COMM_ARITH
59	an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
60	RTX_TERNARY
61	an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
62	RTX_BIN_ARITH
63	an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
64	RTX_BITFIELD_OPS
65	an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
66	RTX_INSN
67	an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68	data that will be output as assembly pseudo-ops (DEBUG_INSN)
69	RTX_MATCH
70	an rtx code for something that matches in insns (e.g, MATCH_DUP)
71	RTX_AUTOINC
72	an rtx code for autoincrement addressing modes (e.g. POST_DEC)
73	RTX_EXTRA
74	everything else
75
76	All of the expressions that appear only in machine descriptions,
77	not in RTL used by the compiler itself, are at the end of the file. /*
78
79	/ Unknown, or no such operation; the enumeration constant should have*
80	value zero. /*
81	DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
82
83	/ Used in the cselib routines to describe a value. Objects of this*
84	kind are only allocated in cselib.cc, in an alloc pool instead of in
85	GC memory. The only operand of a VALUE is a cselib_val.
86	var-tracking requires this to have a distinct integral value from
87	DECL codes in trees. /*
88	DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
89
90	/ The RTL generated for a DEBUG_EXPR_DECL. It links back to the*
91	DEBUG_EXPR_DECL in the first operand. /*
92	DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
93
94	/ ---------------------------------------------------------------------*
95	Expressions used in constructing lists.
96	--------------------------------------------------------------------- /*
97
98	/ A linked list of expressions. /
99	DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
100
101	/ A linked list of instructions.*
102	The insns are represented in print by their uids. /*
103	DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
104
105	/ A linked list of integers. /
106	DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA)
107
108	/ SEQUENCE is used in late passes of the compiler to group insns for*
109	one reason or another.
110
111	For example, after delay slot filling, branch instructions with filled
112	delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
113	with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
114	occupying the delay slots in the remaining XEXPVEC slots.
115
116	Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
117	notes, to express complex operations that are not obvious from the insn
118	to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of
119	SEQUENCE, the sequence vector slots do not hold real instructions but
120	only pseudo-instructions that can be translated to DWARF CFA expressions.
121
122	Some back ends also use SEQUENCE to group insns in bundles.
123
124	Much of the compiler infrastructure is not prepared to handle SEQUENCE
125	objects. Only passes after pass_free_cfg are expected to handle them. /*
126	DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
127
128	/ Represents a non-global base address. This is only used in alias.cc. /
129	DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
130
131	/ ----------------------------------------------------------------------*
132	Expression types used for things in the instruction chain.
133
134	All formats must start with "uu" to handle the chain.
135	Each insn expression holds an rtl instruction and its semantics
136	during back-end processing.
137	See macros in "rtl.h" for the meaning of each rtx->u.fld[].
138
139	---------------------------------------------------------------------- /*
140
141	/ An annotation for variable assignment tracking. /
142	DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "uuBeiie", RTX_INSN)
143
144	/ An instruction that cannot jump. /
145	DEF_RTL_EXPR(INSN, "insn", "uuBeiie", RTX_INSN)
146
147	/ An instruction that can possibly jump.*
148	Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. /*
149	DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "uuBeiie0", RTX_INSN)
150
151	/ An instruction that can possibly call a subroutine*
152	but which will not change which instruction comes next
153	in the current function.
154	Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
155	All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. /*
156	DEF_RTL_EXPR(CALL_INSN, "call_insn", "uuBeiiee", RTX_INSN)
157
158	/ Placeholder for tablejump JUMP_INSNs. The pattern of this kind*
159	of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
160	placeholders do not appear as real instructions inside a basic
161	block, but are considered active_insn_p instructions for historical
162	reasons, when jump table data was represented with JUMP_INSNs. /*
163	DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "uuBe0000", RTX_INSN)
164
165	/ A marker that indicates that control will not flow through. /
166	DEF_RTL_EXPR(BARRIER, "barrier", "uu00000", RTX_EXTRA)
167
168	/ Holds a label that is followed by instructions.*
169	Operand:
170	3: is used in jump.cc for the use-count of the label.
171	4: is used in the sh backend.
172	5: is a number that is unique in the entire compilation.
173	6: is the user-given name of the label, if any. /*
174	DEF_RTL_EXPR(CODE_LABEL, "code_label", "uuB00is", RTX_EXTRA)
175
176	/ Say where in the code a source line starts, for symbol table's sake.*
177	Operand:
178	3: note-specific data
179	4: enum insn_note
180	5: unique number if insn_note == note_insn_deleted_label. /*
181	DEF_RTL_EXPR(NOTE, "note", "uuB0ni", RTX_EXTRA)
182
183	/ ----------------------------------------------------------------------*
184	Top level constituents of INSN, JUMP_INSN and CALL_INSN.
185	---------------------------------------------------------------------- /*
186
187	/ Conditionally execute code.*
188	Operand 0 is the condition that if true, the code is executed.
189	Operand 1 is the code to be executed (typically a SET).
190
191	Semantics are that there are no side effects if the condition
192	is false. This pattern is created automatically by the if_convert
193	pass run after reload or by target-specific splitters. /*
194	DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
195
196	/ Several operations to be done in parallel (perhaps under COND_EXEC). /
197	DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
198
199	/ A string that is passed through to the assembler as input.*
200	One can obviously pass comments through by using the
201	assembler comment syntax.
202	These occur in an insn all by themselves as the PATTERN.
203	They also appear inside an ASM_OPERANDS
204	as a convenient way to hold a string. /*
205	DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
206
207	/ An assembler instruction with operands.*
208	1st operand is the instruction template.
209	2nd operand is the constraint for the output.
210	3rd operand is the number of the output this expression refers to.
211	When an insn stores more than one value, a separate ASM_OPERANDS
212	is made for each output; this integer distinguishes them.
213	4th is a vector of values of input operands.
214	5th is a vector of modes and constraints for the input operands.
215	Each element is an ASM_INPUT containing a constraint string
216	and whose mode indicates the mode of the input operand.
217	6th is a vector of labels that may be branched to by the asm.
218	7th is the source line number. /*
219	DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
220
221	/ A machine-specific operation.*
222	1st operand is a vector of operands being used by the operation so that
223	any needed reloads can be done.
224	2nd operand is a unique value saying which of a number of machine-specific
225	operations is to be performed.
226	(Note that the vector must be the first operand because of the way that
227	genrecog.cc record positions within an insn.)
228
229	UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
230	or inside an expression.
231	UNSPEC by itself or as a component of a PARALLEL
232	is currently considered not deletable.
233
234	FIXME: Replace all uses of UNSPEC that appears by itself or as a component
235	of a PARALLEL with USE.
236	*/
237	DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
238
239	/ Similar, but a volatile operation and one which may trap. /
240	DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
241
242	/ ----------------------------------------------------------------------*
243	Table jump addresses.
244	---------------------------------------------------------------------- /*
245
246	/ Vector of addresses, stored as full words.*
247	Each element is a LABEL_REF to a CODE_LABEL whose address we want. /*
248	DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
249
250	/ Vector of address differences X0 - BASE, X1 - BASE, ...*
251	First operand is BASE; the vector contains the X's.
252	The machine mode of this rtx says how much space to leave
253	for each difference and is adjusted by branch shortening if
254	CASE_VECTOR_SHORTEN_MODE is defined.
255	The third and fourth operands store the target labels with the
256	minimum and maximum addresses respectively.
257	The fifth operand stores flags for use by branch shortening.
258	Set at the start of shorten_branches:
259	min_align: the minimum alignment for any of the target labels.
260	base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
261	min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
262	max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
263	min_after_base: true iff minimum address target label is after BASE.
264	max_after_base: true iff maximum address target label is after BASE.
265	Set by the actual branch shortening process:
266	offset_unsigned: true iff offsets have to be treated as unsigned.
267	scale: scaling that is necessary to make offsets fit into the mode.
268
269	The third, fourth and fifth operands are only valid when
270	CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
271	compilation. /*
272	DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
273
274	/ Memory prefetch, with attributes supported on some targets.*
275	Operand 1 is the address of the memory to fetch.
276	Operand 2 is 1 for a write access, 0 otherwise.
277	Operand 3 is the level of temporal locality; 0 means there is no
278	temporal locality and 1, 2, and 3 are for increasing levels of temporal
279	locality.
280
281	The attributes specified by operands 2 and 3 are ignored for targets
282	whose prefetch instructions do not support them. /*
283	DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
284
285	/ ----------------------------------------------------------------------*
286	At the top level of an instruction (perhaps under PARALLEL).
287	---------------------------------------------------------------------- /*
288
289	/ Assignment.*
290	Operand 1 is the location (REG, MEM, PC or whatever) assigned to.
291	Operand 2 is the value stored there.
292	ALL assignment must use SET.
293	Instructions that do multiple assignments must use multiple SET,
294	under PARALLEL. /*
295	DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
296
297	/ Indicate something is used in a way that we don't want to explain.*
298	For example, subroutine calls will use the register
299	in which the static chain is passed.
300
301	USE cannot appear as an operand of other rtx except for PARALLEL.
302	USE is not deletable, as it indicates that the operand
303	is used in some unknown way. /*
304	DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
305
306	/ Indicate something is clobbered in a way that we don't want to explain.*
307	For example, subroutine calls will clobber some physical registers
308	(the ones that are by convention not saved).
309
310	CLOBBER cannot appear as an operand of other rtx except for PARALLEL.
311	CLOBBER of a hard register appearing by itself (not within PARALLEL)
312	is considered undeletable before reload. /*
313	DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
314
315	/ Call a subroutine.*
316	Operand 1 is the address to call.
317	Operand 2 is the number of arguments. /*
318
319	DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
320
321	/ Return from a subroutine. /
322
323	DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
324
325	/ Like RETURN, but truly represents only a function return, while*
326	RETURN may represent an insn that also performs other functions
327	of the function epilogue. Like RETURN, this may also occur in
328	conditional jumps. /*
329	DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
330
331	/ Special for EH return from subroutine. /
332
333	DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
334
335	/ Conditional trap.*
336	Operand 1 is the condition.
337	Operand 2 is the trap code.
338	For an unconditional trap, make the condition (const_int 1). /*
339	DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
340
341	/ ----------------------------------------------------------------------*
342	Primitive values for use in expressions.
343	---------------------------------------------------------------------- /*
344
345	/ numeric integer constant /
346	DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
347
348	/ numeric integer constant /
349	DEF_RTL_EXPR(CONST_WIDE_INT, "const_wide_int", "", RTX_CONST_OBJ)
350
351	/ An rtx representation of a poly_wide_int. /
352	DEF_RTL_EXPR(CONST_POLY_INT, "const_poly_int", "", RTX_CONST_OBJ)
353
354	/ fixed-point constant /
355	DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
356
357	/ numeric floating point or integer constant. If the mode is*
358	VOIDmode it is an int otherwise it has a floating point mode and a
359	floating point value. Operands hold the value. They are all 'w'
360	and there may be from 2 to 6; see real.h. /*
361	DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
362
363	/ Describes a vector constant. /
364	DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
365
366	/ String constant. Used for attributes in machine descriptions and*
367	for special cases in DWARF2 debug output. NOT used for source-
368	language string constants. /*
369	DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
370
371	/ This is used to encapsulate an expression whose value is constant*
372	(such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
373	recognized as a constant operand rather than by arithmetic instructions. /*
374
375	DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
376
377	/ program counter. Ordinary jumps are represented*
378	by a SET whose first operand is (PC). /*
379	DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
380
381	/ A register. The "operand" is the register number, accessed with*
382	the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
383	then a hardware register is being referred to. The second operand
384	points to a reg_attrs structure.
385	This rtx needs to have as many (or more) fields as a MEM, since we
386	can change REG rtx's into MEMs during reload. /*
387	DEF_RTL_EXPR(REG, "reg", "r", RTX_OBJ)
388
389	/ A scratch register. This represents a register used only within a*
390	single insn. It will be replaced by a REG during register allocation
391	or reload unless the constraint indicates that the register won't be
392	needed, in which case it can remain a SCRATCH. /*
393	DEF_RTL_EXPR(SCRATCH, "scratch", "", RTX_OBJ)
394
395	/ A reference to a part of another value. The first operand is the*
396	complete value and the second is the byte offset of the selected part. /*
397	DEF_RTL_EXPR(SUBREG, "subreg", "ep", RTX_EXTRA)
398
399	/ This one-argument rtx is used for move instructions*
400	that are guaranteed to alter only the low part of a destination.
401	Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
402	has an unspecified effect on the high part of REG,
403	but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
404	is guaranteed to alter only the bits of REG that are in HImode.
405
406	The actual instruction used is probably the same in both cases,
407	but the register constraints may be tighter when STRICT_LOW_PART
408	is in use. /*
409
410	DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
411
412	/ (CONCAT a b) represents the virtual concatenation of a and b*
413	to make a value that has as many bits as a and b put together.
414	This is used for complex values. Normally it appears only
415	in DECL_RTLs and during RTL generation, but not in the insn chain. /*
416	DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
417
418	/ (CONCATN [a1 a2 ... an]) represents the virtual concatenation of*
419	all An to make a value. This is an extension of CONCAT to larger
420	number of components. Like CONCAT, it should not appear in the
421	insn chain. Every element of the CONCATN is the same size. /*
422	DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
423
424	/ A memory location; operand is the address. The second operand is the*
425	alias set to which this MEM belongs. We use `0' instead of `w' for this
426	field so that the field need not be specified in machine descriptions. /*
427	DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
428
429	/ Reference to an assembler label in the code for this function.*
430	The operand is a CODE_LABEL found in the insn chain. /*
431	DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
432
433	/ Reference to a named label:*
434	Operand 0: label name
435	Operand 1: tree from which this symbol is derived, or null.
436	This is either a DECL node, or some kind of constant. /*
437	DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s0", RTX_CONST_OBJ)
438
439	/ ----------------------------------------------------------------------*
440	Expressions for operators in an rtl pattern
441	---------------------------------------------------------------------- /*
442
443	/ if_then_else. This is used in representing ordinary*
444	conditional jump instructions.
445	Operand:
446	0: condition
447	1: then expr
448	2: else expr /*
449	DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
450
451	/ Comparison, produces a condition code result. /
452	DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
453
454	/ plus /
455	DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
456
457	/ Operand 0 minus operand 1. /
458	DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
459
460	/ Minus operand 0. /
461	DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
462
463	DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
464
465	/ Multiplication with signed saturation /
466	DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
467	/ Multiplication with unsigned saturation /
468	DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
469
470	/ Signed high-part multiplication. /
471	DEF_RTL_EXPR(SMUL_HIGHPART, "smul_highpart", "ee", RTX_COMM_ARITH)
472	/ Unsigned high-part multiplication. /
473	DEF_RTL_EXPR(UMUL_HIGHPART, "umul_highpart", "ee", RTX_COMM_ARITH)
474
475	/ Operand 0 divided by operand 1. /
476	DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
477	/ Division with signed saturation /
478	DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
479	/ Division with unsigned saturation /
480	DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
481
482	/ Remainder of operand 0 divided by operand 1. /
483	DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
484
485	/ Unsigned divide and remainder. /
486	DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
487	DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
488
489	/ Bitwise operations. /
490	DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
491	DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
492	DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
493	DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
494
495	/ Operand:*
496	0: value to be shifted.
497	1: number of bits. /*
498	DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) / shift left /
499	DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) / rotate left /
500	DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) / arithmetic shift right /
501	DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) / logical shift right /
502	DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) / rotate right /
503
504	/ Minimum and maximum values of two operands. We need both signed and*
505	unsigned forms. (We cannot use MIN for SMIN because it conflicts
506	with a macro of the same name.) The signed variants should be used
507	with floating point. Further, if both operands are zeros, or if either
508	operand is NaN, then it is unspecified which of the two operands is
509	returned as the result. /*
510
511	DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
512	DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
513	DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
514	DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
515
516	/ These unary operations are used to represent incrementation*
517	and decrementation as they occur in memory addresses.
518	The amount of increment or decrement are not represented
519	because they can be understood from the machine-mode of the
520	containing MEM. These operations exist in only two cases:
521	1. pushes onto the stack.
522	2. created automatically by the auto-inc-dec pass. /*
523	DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
524	DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
525	DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
526	DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
527
528	/ These binary operations are used to represent generic address*
529	side-effects in memory addresses, except for simple incrementation
530	or decrementation which use the above operations. They are
531	created automatically by the life_analysis pass in flow.c.
532	The first operand is a REG which is used as the address.
533	The second operand is an expression that is assigned to the
534	register, either before (PRE_MODIFY) or after (POST_MODIFY)
535	evaluating the address.
536	Currently, the compiler can only handle second operands of the
537	form (plus (reg) (reg)) and (plus (reg) (const_int)), where
538	the first operand of the PLUS has to be the same register as
539	the first operand of the _MODIFY. /
540	DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
541	DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
542
543	/ Comparison operations. The first 6 are allowed only for integral,*
544	floating-point and vector modes. LTGT is only allowed for floating-point
545	modes. The last 4 are allowed only for integral and vector modes.
546	For floating-point operations, if either operand is a NaN, then NE returns
547	true and the remaining operations return false. The operations other than
548	EQ and NE may generate an exception on quiet NaNs. /*
549	DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
550	DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
551	DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
552	DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
553	DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
554	DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
555	DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
556	DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
557	DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
558	DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
559	DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
560
561	/ Additional floating-point unordered comparison flavors. /
562	DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
563	DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
564
565	/ These are equivalent to unordered or ... /
566	DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
567	DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
568	DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
569	DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
570	DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
571
572	/ Represents the result of sign-extending the sole operand.*
573	The machine modes of the operand and of the SIGN_EXTEND expression
574	determine how much sign-extension is going on. /*
575	DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
576
577	/ Similar for zero-extension (such as unsigned short to int). /
578	DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
579
580	/ Similar but here the operand has a wider mode. /
581	DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
582
583	/ Similar for extending floating-point values (such as SFmode to DFmode). /
584	DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
585	DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
586
587	/ Conversion of fixed point operand to floating point value. /
588	DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
589
590	/ With fixed-point machine mode:*
591	Conversion of floating point operand to fixed point value.
592	Value is defined only when the operand's value is an integer.
593	With floating-point machine mode (and operand with same mode):
594	Operand is rounded toward zero to produce an integer value
595	represented in floating point. /*
596	DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
597
598	/ Conversion of unsigned fixed point operand to floating point value. /
599	DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
600
601	/ With fixed-point machine mode:*
602	Conversion of floating point operand to unsigned* fixed point value.*
603	Value is defined only when the operand's value is an integer. /*
604	DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
605
606	/ Conversions involving fractional fixed-point types without saturation,*
607	including:
608	fractional to fractional (of different precision),
609	signed integer to fractional,
610	fractional to signed integer,
611	floating point to fractional,
612	fractional to floating point.
613	NOTE: fractional can be either signed or unsigned for conversions. /*
614	DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
615
616	/ Conversions involving fractional fixed-point types and unsigned integer*
617	without saturation, including:
618	unsigned integer to fractional,
619	fractional to unsigned integer.
620	NOTE: fractional can be either signed or unsigned for conversions. /*
621	DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
622
623	/ Conversions involving fractional fixed-point types with saturation,*
624	including:
625	fractional to fractional (of different precision),
626	signed integer to fractional,
627	floating point to fractional.
628	NOTE: fractional can be either signed or unsigned for conversions. /*
629	DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
630
631	/ Conversions involving fractional fixed-point types and unsigned integer*
632	with saturation, including:
633	unsigned integer to fractional.
634	NOTE: fractional can be either signed or unsigned for conversions. /*
635	DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
636
637	/ Absolute value /
638	DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
639
640	/ Square root /
641	DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
642
643	/ Swap bytes. /
644	DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
645
646	/ Find first bit that is set.*
647	Value is 1 + number of trailing zeros in the arg.,
648	or 0 if arg is 0. /*
649	DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
650
651	/ Count number of leading redundant sign bits (number of leading*
652	sign bits minus one). /*
653	DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
654
655	/ Count leading zeros. /
656	DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
657
658	/ Count trailing zeros. /
659	DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
660
661	/ Population count (number of 1 bits). /
662	DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
663
664	/ Population parity (number of 1 bits modulo 2). /
665	DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
666
667	/ Reverse bits. /
668	DEF_RTL_EXPR(BITREVERSE, "bitreverse", "e", RTX_UNARY)
669
670	/ Reference to a signed bit-field of specified size and position.*
671	Operand 0 is the memory unit (usually SImode or QImode) which
672	contains the field's first bit. Operand 1 is the width, in bits.
673	Operand 2 is the number of bits in the memory unit before the
674	first bit of this field.
675	If BITS_BIG_ENDIAN is defined, the first bit is the msb and
676	operand 2 counts from the msb of the memory unit.
677	Otherwise, the first bit is the lsb and operand 2 counts from
678	the lsb of the memory unit.
679	This kind of expression cannot appear as an lvalue in RTL. /*
680	DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
681
682	/ Similar for unsigned bit-field.*
683	But note! This kind of expression _can_ appear as an lvalue. /*
684	DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
685
686	/ For RISC machines. These save memory when splitting insns. /
687
688	/ HIGH are the high-order bits of a constant expression. /
689	DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
690
691	/ LO_SUM is the sum of a register and the low-order bits*
692	of a constant expression. /*
693	DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
694
695	/ Describes a merge operation between two vector values.*
696	Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
697	that specifies where the parts of the result are taken from. Set bits
698	indicate operand 0, clear bits indicate operand 1. The parts are defined
699	by the mode of the vectors. /*
700	DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
701
702	/ Describes an operation that selects parts of a vector.*
703	Operands 0 is the source vector, operand 1 is a PARALLEL that contains
704	a CONST_INT for each of the subparts of the result vector, giving the
705	number of the source subpart that should be stored into it. /*
706	DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
707
708	/ Describes a vector concat operation. Operands 0 and 1 are the source*
709	vectors, the result is a vector that is as long as operands 0 and 1
710	combined and is the concatenation of the two source vectors. /*
711	DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
712
713	/ Describes an operation that converts a small vector into a larger one by*
714	duplicating the input values. The output vector mode must have the same
715	submodes as the input vector mode, and the number of output parts must be
716	an integer multiple of the number of input parts. /*
717	DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
718
719	/ Creation of a vector in which element I has the value BASE + I * STEP,*
720	where BASE is the first operand and STEP is the second. The result
721	must have a vector integer mode. /*
722	DEF_RTL_EXPR(VEC_SERIES, "vec_series", "ee", RTX_BIN_ARITH)
723
724	/ Addition with signed saturation /
725	DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
726
727	/ Addition with unsigned saturation /
728	DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
729
730	/ Operand 0 minus operand 1, with signed saturation. /
731	DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
732
733	/ Negation with signed saturation. /
734	DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
735	/ Negation with unsigned saturation. /
736	DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
737
738	/ Absolute value with signed saturation. /
739	DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
740
741	/ Shift left with signed saturation. /
742	DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
743
744	/ Shift left with unsigned saturation. /
745	DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
746
747	/ Operand 0 minus operand 1, with unsigned saturation. /
748	DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
749
750	/ Signed saturating truncate. /
751	DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
752
753	/ Unsigned saturating truncate. /
754	DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
755
756	/ Floating point multiply/add combined instruction. /
757	DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
758
759	/ Floating point copysign. Operand 0 with the sign of operand 1. /
760	DEF_RTL_EXPR(COPYSIGN, "copysign", "ee", RTX_BIN_ARITH)
761
762	/ Information about the variable and its location. /
763	DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
764
765	/ Used in VAR_LOCATION for a pointer to a decl that is no longer*
766	addressable. /*
767	DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
768
769	/ Represents value that argument had on function entry. The*
770	single argument is the DECL_INCOMING_RTL of the corresponding
771	parameter. /*
772	DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
773
774	/ Used in VAR_LOCATION for a reference to a parameter that has*
775	been optimized away completely. /*
776	DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
777
778	/ Used in marker DEBUG_INSNs to avoid being recognized as an insn. /
779	DEF_RTL_EXPR(DEBUG_MARKER, "debug_marker", "", RTX_EXTRA)
780
781	/ All expressions from this point forward appear only in machine*
782	descriptions. /*
783	#ifdef GENERATOR_FILE
784
785	/ Pattern-matching operators: /
786
787	/ Use the function named by the second arg (the string)*
788	as a predicate; if matched, store the structure that was matched
789	in the operand table at index specified by the first arg (the integer).
790	If the second arg is the null string, the structure is just stored.
791
792	A third string argument indicates to the register allocator restrictions
793	on where the operand can be allocated.
794
795	If the target needs no restriction on any instruction this field should
796	be the null string.
797
798	The string is prepended by:
799	'=' to indicate the operand is only written to.
800	'+' to indicate the operand is both read and written to.
801
802	Each character in the string represents an allocable class for an operand.
803	'g' indicates the operand can be any valid class.
804	'i' indicates the operand can be immediate (in the instruction) data.
805	'r' indicates the operand can be in a register.
806	'm' indicates the operand can be in memory.
807	'o' a subset of the 'm' class. Those memory addressing modes that
808	can be offset at compile time (have a constant added to them).
809
810	Other characters indicate target dependent operand classes and
811	are described in each target's machine description.
812
813	For instructions with more than one operand, sets of classes can be
814	separated by a comma to indicate the appropriate multi-operand constraints.
815	There must be a 1 to 1 correspondence between these sets of classes in
816	all operands for an instruction.
817	*/
818	DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
819
820	/ Match a SCRATCH or a register. When used to generate rtl, a*
821	SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
822	the desired mode and the first argument is the operand number.
823	The second argument is the constraint. /*
824	DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
825
826	/ Apply a predicate, AND match recursively the operands of the rtx.*
827	Operand 0 is the operand-number, as in match_operand.
828	Operand 1 is a predicate to apply (as a string, a function name).
829	Operand 2 is a vector of expressions, each of which must match
830	one subexpression of the rtx this construct is matching. /*
831	DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
832
833	/ Match a PARALLEL of arbitrary length. The predicate is applied*
834	to the PARALLEL and the initial expressions in the PARALLEL are matched.
835	Operand 0 is the operand-number, as in match_operand.
836	Operand 1 is a predicate to apply to the PARALLEL.
837	Operand 2 is a vector of expressions, each of which must match the
838	corresponding element in the PARALLEL. /*
839	DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
840
841	/ Match only something equal to what is stored in the operand table*
842	at the index specified by the argument. Use with MATCH_OPERAND. /*
843	DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
844
845	/ Match only something equal to what is stored in the operand table*
846	at the index specified by the argument. Use with MATCH_OPERATOR. /*
847	DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
848
849	/ Match only something equal to what is stored in the operand table*
850	at the index specified by the argument. Use with MATCH_PARALLEL. /*
851	DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
852
853	/ Appears only in define_predicate/define_special_predicate*
854	expressions. Evaluates true only if the operand has an RTX code
855	from the set given by the argument (a comma-separated list). If the
856	second argument is present and nonempty, it is a sequence of digits
857	and/or letters which indicates the subexpression to test, using the
858	same syntax as genextract/genrecog's location strings: 0-9 for
859	XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
860	the result of the one before it. /*
861	DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
862
863	/ Used to inject a C conditional expression into an .md file. It can*
864	appear in a predicate definition or an attribute expression. /*
865	DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
866
867	/ Insn (and related) definitions. /
868
869	/ Definition of the pattern for one kind of instruction.*
870	Operand:
871	0: names this instruction.
872	If the name is the null string, the instruction is in the
873	machine description just to be recognized, and will never be emitted by
874	the tree to rtl expander.
875	1: is the pattern.
876	2: is a string which is a C expression
877	giving an additional condition for recognizing this pattern.
878	A null string means no extra condition.
879	3: is the action to execute if this pattern is matched.
880	If this assembler code template starts with a then it is a fragment of*
881	C code to run to decide on a template to use. Otherwise, it is the
882	template to use.
883	4: optionally, a vector of attributes for this insn.
884	*/
885	DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
886
887	/ Definition of a peephole optimization.*
888	1st operand: vector of insn patterns to match
889	2nd operand: C expression that must be true
890	3rd operand: template or C code to produce assembler output.
891	4: optionally, a vector of attributes for this insn.
892
893	This form is deprecated; use define_peephole2 instead. /*
894	DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
895
896	/ Definition of a split operation.*
897	1st operand: insn pattern to match
898	2nd operand: C expression that must be true
899	3rd operand: vector of insn patterns to place into a SEQUENCE
900	4th operand: optionally, some C code to execute before generating the
901	insns. This might, for example, create some RTX's and store them in
902	elements of `recog_data.operand' for use by the vector of
903	insn-patterns.
904	(`operands' is an alias here for `recog_data.operand'). /*
905	DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
906
907	/ Definition of an insn and associated split.*
908	This is the concatenation, with a few modifications, of a define_insn
909	and a define_split which share the same pattern.
910	Operand:
911	0: names this instruction.
912	If the name is the null string, the instruction is in the
913	machine description just to be recognized, and will never be emitted by
914	the tree to rtl expander.
915	1: is the pattern.
916	2: is a string which is a C expression
917	giving an additional condition for recognizing this pattern.
918	A null string means no extra condition.
919	3: is the action to execute if this pattern is matched.
920	If this assembler code template starts with a then it is a fragment of*
921	C code to run to decide on a template to use. Otherwise, it is the
922	template to use.
923	4: C expression that must be true for split. This may start with "&&"
924	in which case the split condition is the logical and of the insn
925	condition and what follows the "&&" of this operand.
926	5: vector of insn patterns to place into a SEQUENCE
927	6: optionally, some C code to execute before generating the
928	insns. This might, for example, create some RTX's and store them in
929	elements of `recog_data.operand' for use by the vector of
930	insn-patterns.
931	(`operands' is an alias here for `recog_data.operand').
932	7: optionally, a vector of attributes for this insn. /*
933	DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
934
935	/ A form of define_insn_and_split in which the split insn pattern (operand 5)*
936	is determined automatically by replacing match_operands with match_dups
937	and match_operators with match_op_dups. The operands are the same as
938	define_insn_and_split but with operand 5 removed. /*
939	DEF_RTL_EXPR(DEFINE_INSN_AND_REWRITE, "define_insn_and_rewrite", "sEsTsSV", RTX_EXTRA)
940
941	/ Definition of an RTL peephole operation.*
942	Follows the same arguments as define_split. /*
943	DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
944
945	/ Define how to generate multiple insns for a standard insn name.*
946	1st operand: the insn name.
947	2nd operand: vector of insn-patterns.
948	Use match_operand to substitute an element of `recog_data.operand'.
949	3rd operand: C expression that must be true for this to be available.
950	This may not test any operands.
951	4th operand: Extra C code to execute before generating the insns.
952	This might, for example, create some RTX's and store them in
953	elements of `recog_data.operand' for use by the vector of
954	insn-patterns.
955	(`operands' is an alias here for `recog_data.operand').
956	5th: optionally, a vector of attributes for this expand. /*
957	DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
958
959	/ Define a requirement for delay slots.*
960	1st operand: Condition involving insn attributes that, if true,
961	indicates that the insn requires the number of delay slots
962	shown.
963	2nd operand: Vector whose length is the three times the number of delay
964	slots required.
965	Each entry gives three conditions, each involving attributes.
966	The first must be true for an insn to occupy that delay slot
967	location. The second is true for all insns that can be
968	annulled if the branch is true and the third is true for all
969	insns that can be annulled if the branch is false.
970
971	Multiple DEFINE_DELAYs may be present. They indicate differing
972	requirements for delay slots. /*
973	DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
974
975	/ Define attribute computation for `asm' instructions. /
976	DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
977
978	/ Definition of a conditional execution meta operation. Automatically*
979	generates new instances of DEFINE_INSN, selected by having attribute
980	"predicable" true. The new pattern will contain a COND_EXEC and the
981	predicate at top-level.
982
983	Operand:
984	0: The predicate pattern. The top-level form should match a
985	relational operator. Operands should have only one alternative.
986	1: A C expression giving an additional condition for recognizing
987	the generated pattern.
988	2: A template or C code to produce assembler output.
989	3: A vector of attributes to append to the resulting cond_exec insn. /*
990	DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
991
992	/ Definition of an operand predicate. The difference between*
993	DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
994	not warn about a match_operand with no mode if it has a predicate
995	defined with DEFINE_SPECIAL_PREDICATE.
996
997	Operand:
998	0: The name of the predicate.
999	1: A boolean expression which computes whether or not the predicate
1000	matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
1001	MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
1002	can calculate the set of RTX codes that can possibly match.
1003	2: A C function body which must return true for the predicate to match.
1004	Optional. Use this when the test is too complicated to fit into a
1005	match_test expression. /*
1006	DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
1007	DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
1008
1009	/ Definition of a register operand constraint. This simply maps the*
1010	constraint string to a register class.
1011
1012	Operand:
1013	0: The name of the constraint (often, but not always, a single letter).
1014	1: A C expression which evaluates to the appropriate register class for
1015	this constraint. If this is not just a constant, it should look only
1016	at -m switches and the like.
1017	2: A docstring for this constraint, in Texinfo syntax; not currently
1018	used, in future will be incorporated into the manual's list of
1019	machine-specific operand constraints. /*
1020	DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
1021
1022	/ Definition of a non-register operand constraint. These look at the*
1023	operand and decide whether it fits the constraint.
1024
1025	DEFINE_CONSTRAINT gets no special treatment if it fails to match.
1026	It is appropriate for constant-only constraints, and most others.
1027
1028	DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
1029	to match, if it doesn't already, by converting the operand to the form
1030	(mem (reg X)) where X is a base register. It is suitable for constraints
1031	that describe a subset of all memory references.
1032
1033	DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
1034	to match, if it doesn't already, by converting the operand to the form
1035	(reg X) where X is a base register. It is suitable for constraints that
1036	describe a subset of all address references.
1037
1038	When in doubt, use plain DEFINE_CONSTRAINT.
1039
1040	Operand:
1041	0: The name of the constraint (often, but not always, a single letter).
1042	1: A docstring for this constraint, in Texinfo syntax; not currently
1043	used, in future will be incorporated into the manual's list of
1044	machine-specific operand constraints.
1045	2: A boolean expression which computes whether or not the constraint
1046	matches. It should follow the same rules as a define_predicate
1047	expression, including the bit about specifying the set of RTX codes
1048	that could possibly match. MATCH_TEST subexpressions may make use of
1049	these variables:
1050	`op' - the RTL object defining the operand.
1051	`mode' - the mode of `op'.
1052	`ival' - INTVAL(op), if op is a CONST_INT.
1053	`hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1054	`lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1055	`rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1056	CONST_DOUBLE.
1057	Do not use ival/hval/lval/rval if op is not the appropriate kind of
1058	RTL object. /*
1059	DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1060	DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1061	DEF_RTL_EXPR(DEFINE_SPECIAL_MEMORY_CONSTRAINT, "define_special_memory_constraint", "sse", RTX_EXTRA)
1062	DEF_RTL_EXPR(DEFINE_RELAXED_MEMORY_CONSTRAINT, "define_relaxed_memory_constraint", "sse", RTX_EXTRA)
1063	DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1064
1065
1066	/ Constructions for CPU pipeline description described by NDFAs. /
1067
1068	/ (define_cpu_unit string [string]) describes cpu functional*
1069	units (separated by comma).
1070
1071	1st operand: Names of cpu functional units.
1072	2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1073
1074	All define_reservations, define_cpu_units, and
1075	define_query_cpu_units should have unique names which may not be
1076	"nothing". /*
1077	DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1078
1079	/ (define_query_cpu_unit string [string]) describes cpu functional*
1080	units analogously to define_cpu_unit. The reservation of such
1081	units can be queried for automaton state. /*
1082	DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1083
1084	/ (exclusion_set string string) means that each CPU functional unit*
1085	in the first string cannot be reserved simultaneously with any
1086	unit whose name is in the second string and vise versa. CPU units
1087	in the string are separated by commas. For example, it is useful
1088	for description CPU with fully pipelined floating point functional
1089	unit which can execute simultaneously only single floating point
1090	insns or only double floating point insns. All CPU functional
1091	units in a set should belong to the same automaton. /*
1092	DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1093
1094	/ (presence_set string string) means that each CPU functional unit in*
1095	the first string cannot be reserved unless at least one of pattern
1096	of units whose names are in the second string is reserved. This is
1097	an asymmetric relation. CPU units or unit patterns in the strings
1098	are separated by commas. Pattern is one unit name or unit names
1099	separated by white-spaces.
1100
1101	For example, it is useful for description that slot1 is reserved
1102	after slot0 reservation for a VLIW processor. We could describe it
1103	by the following construction
1104
1105	(presence_set "slot1" "slot0")
1106
1107	Or slot1 is reserved only after slot0 and unit b0 reservation. In
1108	this case we could write
1109
1110	(presence_set "slot1" "slot0 b0")
1111
1112	All CPU functional units in a set should belong to the same
1113	automaton. /*
1114	DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1115
1116	/ (final_presence_set string string) is analogous to `presence_set'.*
1117	The difference between them is when checking is done. When an
1118	instruction is issued in given automaton state reflecting all
1119	current and planned unit reservations, the automaton state is
1120	changed. The first state is a source state, the second one is a
1121	result state. Checking for `presence_set' is done on the source
1122	state reservation, checking for `final_presence_set' is done on the
1123	result reservation. This construction is useful to describe a
1124	reservation which is actually two subsequent reservations. For
1125	example, if we use
1126
1127	(presence_set "slot1" "slot0")
1128
1129	the following insn will be never issued (because slot1 requires
1130	slot0 which is absent in the source state).
1131
1132	(define_reservation "insn_and_nop" "slot0 + slot1")
1133
1134	but it can be issued if we use analogous `final_presence_set'. /*
1135	DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1136
1137	/ (absence_set string string) means that each CPU functional unit in*
1138	the first string can be reserved only if each pattern of units
1139	whose names are in the second string is not reserved. This is an
1140	asymmetric relation (actually exclusion set is analogous to this
1141	one but it is symmetric). CPU units or unit patterns in the string
1142	are separated by commas. Pattern is one unit name or unit names
1143	separated by white-spaces.
1144
1145	For example, it is useful for description that slot0 cannot be
1146	reserved after slot1 or slot2 reservation for a VLIW processor. We
1147	could describe it by the following construction
1148
1149	(absence_set "slot2" "slot0, slot1")
1150
1151	Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
1152	slot1 and unit b1 are reserved . In this case we could write
1153
1154	(absence_set "slot2" "slot0 b0, slot1 b1")
1155
1156	All CPU functional units in a set should to belong the same
1157	automaton. /*
1158	DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1159
1160	/ (final_absence_set string string) is analogous to `absence_set' but*
1161	checking is done on the result (state) reservation. See comments
1162	for `final_presence_set'. /*
1163	DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1164
1165	/ (define_bypass number out_insn_names in_insn_names) names bypass*
1166	with given latency (the first number) from insns given by the first
1167	string (see define_insn_reservation) into insns given by the second
1168	string. Insn names in the strings are separated by commas. The
1169	third operand is optional name of function which is additional
1170	guard for the bypass. The function will get the two insns as
1171	parameters. If the function returns zero the bypass will be
1172	ignored for this case. Additional guard is necessary to recognize
1173	complicated bypasses, e.g. when consumer is load address. If there
1174	are more one bypass with the same output and input insns, the
1175	chosen bypass is the first bypass with a guard in description whose
1176	guard function returns nonzero. If there is no such bypass, then
1177	bypass without the guard function is chosen. /*
1178	DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1179
1180	/ (define_automaton string) describes names of automata generated and*
1181	used for pipeline hazards recognition. The names are separated by
1182	comma. Actually it is possibly to generate the single automaton
1183	but unfortunately it can be very large. If we use more one
1184	automata, the summary size of the automata usually is less than the
1185	single one. The automaton name is used in define_cpu_unit and
1186	define_query_cpu_unit. All automata should have unique names. /*
1187	DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1188
1189	/ (automata_option string) describes option for generation of*
1190	automata. Currently there are the following options:
1191
1192	o "no-minimization" which makes no minimization of automata. This
1193	is only worth to do when we are debugging the description and
1194	need to look more accurately at reservations of states.
1195
1196	o "time" which means printing additional time statistics about
1197	generation of automata.
1198
1199	o "v" which means generation of file describing the result
1200	automata. The file has suffix `.dfa' and can be used for the
1201	description verification and debugging.
1202
1203	o "w" which means generation of warning instead of error for
1204	non-critical errors.
1205
1206	o "ndfa" which makes nondeterministic finite state automata.
1207
1208	o "progress" which means output of a progress bar showing how many
1209	states were generated so far for automaton being processed. /*
1210	DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1211
1212	/ (define_reservation string string) names reservation (the first*
1213	string) of cpu functional units (the 2nd string). Sometimes unit
1214	reservations for different insns contain common parts. In such
1215	case, you can describe common part and use its name (the 1st
1216	parameter) in regular expression in define_insn_reservation. All
1217	define_reservations, define_cpu_units, and define_query_cpu_units
1218	should have unique names which may not be "nothing". /*
1219	DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1220
1221	/ (define_insn_reservation name default_latency condition regexpr)*
1222	describes reservation of cpu functional units (the 3nd operand) for
1223	instruction which is selected by the condition (the 2nd parameter).
1224	The first parameter is used for output of debugging information.
1225	The reservations are described by a regular expression according
1226	the following syntax:
1227
1228	regexp = regexp "," oneof
1229	\| oneof
1230
1231	oneof = oneof "\|" allof
1232	\| allof
1233
1234	allof = allof "+" repeat
1235	\| repeat
1236
1237	repeat = element "" number*
1238	\| element
1239
1240	element = cpu_function_unit_name
1241	\| reservation_name
1242	\| result_name
1243	\| "nothing"
1244	\| "(" regexp ")"
1245
1246	1. "," is used for describing start of the next cycle in
1247	reservation.
1248
1249	2. "\|" is used for describing the reservation described by the
1250	first regular expression or* the reservation described by the*
1251	second regular expression or* etc.*
1252
1253	3. "+" is used for describing the reservation described by the
1254	first regular expression and* the reservation described by the*
1255	second regular expression and* etc.*
1256
1257	4. "" is used for convenience and simply means sequence in*
1258	which the regular expression are repeated NUMBER times with
1259	cycle advancing (see ",").
1260
1261	5. cpu functional unit name which means its reservation.
1262
1263	6. reservation name -- see define_reservation.
1264
1265	7. string "nothing" means no units reservation. /*
1266
1267	DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1268
1269	/ Expressions used for insn attributes. /
1270
1271	/ Definition of an insn attribute.*
1272	1st operand: name of the attribute
1273	2nd operand: comma-separated list of possible attribute values
1274	3rd operand: expression for the default value of the attribute. /*
1275	DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1276
1277	/ Definition of an insn attribute that uses an existing enumerated type.*
1278	1st operand: name of the attribute
1279	2nd operand: the name of the enumerated type
1280	3rd operand: expression for the default value of the attribute. /*
1281	DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1282
1283	/ Marker for the name of an attribute. /
1284	DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1285
1286	/ For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and*
1287	in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1288	pattern.
1289
1290	(set_attr "name" "value") is equivalent to
1291	(set (attr "name") (const_string "value")) /*
1292	DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1293
1294	/ In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to*
1295	specify that attribute values are to be assigned according to the
1296	alternative matched.
1297
1298	The following three expressions are equivalent:
1299
1300	(set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1301	(eq_attrq "alternative" "2") (const_string "a2")]
1302	(const_string "a3")))
1303	(set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1304	(const_string "a3")])
1305	(set_attr "att" "a1,a2,a3")
1306	*/
1307	DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1308
1309	/ A conditional expression true if the value of the specified attribute of*
1310	the current insn equals the specified value. The first operand is the
1311	attribute name and the second is the comparison value. /*
1312	DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1313
1314	/ A special case of the above representing a set of alternatives. The first*
1315	operand is bitmap of the set, the second one is the default value. /*
1316	DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ww", RTX_EXTRA)
1317
1318	/ A conditional expression which is true if the specified flag is*
1319	true for the insn being scheduled in reorg.
1320
1321	genattr.cc defines the following flags which can be tested by
1322	(attr_flag "foo") expressions in eligible_for_delay: forward, backward. /*
1323
1324	DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1325
1326	/ General conditional. The first operand is a vector composed of pairs of*
1327	expressions. The first element of each pair is evaluated, in turn.
1328	The value of the conditional is the second expression of the first pair
1329	whose first expression evaluates nonzero. If none of the expressions is
1330	true, the second operand will be used as the value of the conditional. /*
1331	DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1332
1333	/ Definition of a pattern substitution meta operation on a DEFINE_EXPAND*
1334	or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
1335	that match the substitution pattern.
1336
1337	Operand:
1338	0: The name of the substitition template.
1339	1: Input template to match to see if a substitution is applicable.
1340	2: A C expression giving an additional condition for the generated
1341	new define_expand or define_insn.
1342	3: Output tempalate to generate via substitution.
1343
1344	Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1345	different from their usual interpretation: a MATCH_OPERAND matches any
1346	expression tree with matching machine mode or with VOIDmode. Likewise,
1347	MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1348	in other RTL expressions. MATCH_OPERATOR matches all common operators
1349	but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1350	DEFINE_EXPAND or DEFINE_INSN. /*
1351	DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1352
1353	/ Substitution attribute to apply a DEFINE_SUBST to a pattern.*
1354
1355	Operand:
1356	0: The name of the subst-attribute.
1357	1: The name of the DEFINE_SUBST to be applied for this attribute.
1358	2: String to substitute for the subst-attribute name in the pattern
1359	name, for the case that the DEFINE_SUBST is not applied (i.e. the
1360	unmodified version of the pattern).
1361	3: String to substitute for the subst-attribute name in the pattern
1362	name, for the case that the DEFINE_SUBST is applied to the patten.
1363
1364	The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1365	GCC internals manual, under "RTL Templates Transformations". /*
1366	DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1367
1368	#endif /* GENERATOR_FILE */
1369
1370	/*
1371	Local variables:
1372	mode:c
1373	End:
1374	*/
1375

source code of gcc/rtl.def