1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * linux/arch/alpha/kernel/core_cia.c |
4 | * |
5 | * Written by David A Rusling (david.rusling@reo.mts.dec.com). |
6 | * December 1995. |
7 | * |
8 | * Copyright (C) 1995 David A Rusling |
9 | * Copyright (C) 1997, 1998 Jay Estabrook |
10 | * Copyright (C) 1998, 1999, 2000 Richard Henderson |
11 | * |
12 | * Code common to all CIA core logic chips. |
13 | */ |
14 | |
15 | #define __EXTERN_INLINE inline |
16 | #include <asm/io.h> |
17 | #include <asm/core_cia.h> |
18 | #undef __EXTERN_INLINE |
19 | |
20 | #include <linux/types.h> |
21 | #include <linux/pci.h> |
22 | #include <linux/sched.h> |
23 | #include <linux/init.h> |
24 | #include <linux/memblock.h> |
25 | |
26 | #include <asm/ptrace.h> |
27 | #include <asm/mce.h> |
28 | |
29 | #include "proto.h" |
30 | #include "pci_impl.h" |
31 | |
32 | |
33 | /* |
34 | * NOTE: Herein lie back-to-back mb instructions. They are magic. |
35 | * One plausible explanation is that the i/o controller does not properly |
36 | * handle the system transaction. Another involves timing. Ho hum. |
37 | */ |
38 | |
39 | #define DEBUG_CONFIG 0 |
40 | #if DEBUG_CONFIG |
41 | # define DBGC(args) printk args |
42 | #else |
43 | # define DBGC(args) |
44 | #endif |
45 | |
46 | #define vip volatile int * |
47 | |
48 | /* |
49 | * Given a bus, device, and function number, compute resulting |
50 | * configuration space address. It is therefore not safe to have |
51 | * concurrent invocations to configuration space access routines, but |
52 | * there really shouldn't be any need for this. |
53 | * |
54 | * Type 0: |
55 | * |
56 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
57 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
58 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
59 | * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| |
60 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
61 | * |
62 | * 31:11 Device select bit. |
63 | * 10:8 Function number |
64 | * 7:2 Register number |
65 | * |
66 | * Type 1: |
67 | * |
68 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
69 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
70 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
71 | * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| |
72 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
73 | * |
74 | * 31:24 reserved |
75 | * 23:16 bus number (8 bits = 128 possible buses) |
76 | * 15:11 Device number (5 bits) |
77 | * 10:8 function number |
78 | * 7:2 register number |
79 | * |
80 | * Notes: |
81 | * The function number selects which function of a multi-function device |
82 | * (e.g., SCSI and Ethernet). |
83 | * |
84 | * The register selects a DWORD (32 bit) register offset. Hence it |
85 | * doesn't get shifted by 2 bits as we want to "drop" the bottom two |
86 | * bits. |
87 | */ |
88 | |
89 | static int |
90 | mk_conf_addr(struct pci_bus *bus_dev, unsigned int device_fn, int where, |
91 | unsigned long *pci_addr, unsigned char *type1) |
92 | { |
93 | u8 bus = bus_dev->number; |
94 | |
95 | *type1 = (bus != 0); |
96 | *pci_addr = (bus << 16) | (device_fn << 8) | where; |
97 | |
98 | DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x," |
99 | " returning address 0x%p\n" |
100 | bus, device_fn, where, *pci_addr)); |
101 | |
102 | return 0; |
103 | } |
104 | |
105 | static unsigned int |
106 | conf_read(unsigned long addr, unsigned char type1) |
107 | { |
108 | unsigned long flags; |
109 | int stat0, value; |
110 | int cia_cfg = 0; |
111 | |
112 | DBGC(("conf_read(addr=0x%lx, type1=%d) " , addr, type1)); |
113 | local_irq_save(flags); |
114 | |
115 | /* Reset status register to avoid losing errors. */ |
116 | stat0 = *(vip)CIA_IOC_CIA_ERR; |
117 | *(vip)CIA_IOC_CIA_ERR = stat0; |
118 | mb(); |
119 | *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ |
120 | |
121 | /* If Type1 access, must set CIA CFG. */ |
122 | if (type1) { |
123 | cia_cfg = *(vip)CIA_IOC_CFG; |
124 | *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; |
125 | mb(); |
126 | *(vip)CIA_IOC_CFG; |
127 | } |
128 | |
129 | mb(); |
130 | draina(); |
131 | mcheck_expected(0) = 1; |
132 | mcheck_taken(0) = 0; |
133 | mb(); |
134 | |
135 | /* Access configuration space. */ |
136 | value = *(vip)addr; |
137 | mb(); |
138 | mb(); /* magic */ |
139 | if (mcheck_taken(0)) { |
140 | mcheck_taken(0) = 0; |
141 | value = 0xffffffff; |
142 | mb(); |
143 | } |
144 | mcheck_expected(0) = 0; |
145 | mb(); |
146 | |
147 | /* If Type1 access, must reset IOC CFG so normal IO space ops work. */ |
148 | if (type1) { |
149 | *(vip)CIA_IOC_CFG = cia_cfg; |
150 | mb(); |
151 | *(vip)CIA_IOC_CFG; |
152 | } |
153 | |
154 | local_irq_restore(flags); |
155 | DBGC(("done\n" )); |
156 | |
157 | return value; |
158 | } |
159 | |
160 | static void |
161 | conf_write(unsigned long addr, unsigned int value, unsigned char type1) |
162 | { |
163 | unsigned long flags; |
164 | int stat0, cia_cfg = 0; |
165 | |
166 | DBGC(("conf_write(addr=0x%lx, type1=%d) " , addr, type1)); |
167 | local_irq_save(flags); |
168 | |
169 | /* Reset status register to avoid losing errors. */ |
170 | stat0 = *(vip)CIA_IOC_CIA_ERR; |
171 | *(vip)CIA_IOC_CIA_ERR = stat0; |
172 | mb(); |
173 | *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ |
174 | |
175 | /* If Type1 access, must set CIA CFG. */ |
176 | if (type1) { |
177 | cia_cfg = *(vip)CIA_IOC_CFG; |
178 | *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; |
179 | mb(); |
180 | *(vip)CIA_IOC_CFG; |
181 | } |
182 | |
183 | mb(); |
184 | draina(); |
185 | mcheck_expected(0) = 1; |
186 | mcheck_taken(0) = 0; |
187 | mb(); |
188 | |
189 | /* Access configuration space. */ |
190 | *(vip)addr = value; |
191 | mb(); |
192 | *(vip)addr; /* read back to force the write */ |
193 | |
194 | mcheck_expected(0) = 0; |
195 | mb(); |
196 | |
197 | /* If Type1 access, must reset IOC CFG so normal IO space ops work. */ |
198 | if (type1) { |
199 | *(vip)CIA_IOC_CFG = cia_cfg; |
200 | mb(); |
201 | *(vip)CIA_IOC_CFG; |
202 | } |
203 | |
204 | local_irq_restore(flags); |
205 | DBGC(("done\n" )); |
206 | } |
207 | |
208 | static int |
209 | cia_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, |
210 | u32 *value) |
211 | { |
212 | unsigned long addr, pci_addr; |
213 | long mask; |
214 | unsigned char type1; |
215 | int shift; |
216 | |
217 | if (mk_conf_addr(bus_dev: bus, device_fn: devfn, where, pci_addr: &pci_addr, type1: &type1)) |
218 | return PCIBIOS_DEVICE_NOT_FOUND; |
219 | |
220 | mask = (size - 1) * 8; |
221 | shift = (where & 3) * 8; |
222 | addr = (pci_addr << 5) + mask + CIA_CONF; |
223 | *value = conf_read(addr, type1) >> (shift); |
224 | return PCIBIOS_SUCCESSFUL; |
225 | } |
226 | |
227 | static int |
228 | cia_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, |
229 | u32 value) |
230 | { |
231 | unsigned long addr, pci_addr; |
232 | long mask; |
233 | unsigned char type1; |
234 | |
235 | if (mk_conf_addr(bus_dev: bus, device_fn: devfn, where, pci_addr: &pci_addr, type1: &type1)) |
236 | return PCIBIOS_DEVICE_NOT_FOUND; |
237 | |
238 | mask = (size - 1) * 8; |
239 | addr = (pci_addr << 5) + mask + CIA_CONF; |
240 | conf_write(addr, value: value << ((where & 3) * 8), type1); |
241 | return PCIBIOS_SUCCESSFUL; |
242 | } |
243 | |
244 | struct pci_ops cia_pci_ops = |
245 | { |
246 | .read = cia_read_config, |
247 | .write = cia_write_config, |
248 | }; |
249 | |
250 | /* |
251 | * CIA Pass 1 and PYXIS Pass 1 and 2 have a broken scatter-gather tlb. |
252 | * It cannot be invalidated. Rather than hard code the pass numbers, |
253 | * actually try the tbia to see if it works. |
254 | */ |
255 | |
256 | void |
257 | cia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) |
258 | { |
259 | wmb(); |
260 | *(vip)CIA_IOC_PCI_TBIA = 3; /* Flush all locked and unlocked. */ |
261 | mb(); |
262 | *(vip)CIA_IOC_PCI_TBIA; |
263 | } |
264 | |
265 | /* |
266 | * On PYXIS, even if the tbia works, we cannot use it. It effectively locks |
267 | * the chip (as well as direct write to the tag registers) if there is a |
268 | * SG DMA operation in progress. This is true at least for PYXIS rev. 1, |
269 | * so always use the method below. |
270 | */ |
271 | /* |
272 | * This is the method NT and NetBSD use. |
273 | * |
274 | * Allocate mappings, and put the chip into DMA loopback mode to read a |
275 | * garbage page. This works by causing TLB misses, causing old entries to |
276 | * be purged to make room for the new entries coming in for the garbage page. |
277 | */ |
278 | |
279 | #define CIA_BROKEN_TBIA_BASE 0x30000000 |
280 | #define CIA_BROKEN_TBIA_SIZE 1024 |
281 | |
282 | /* Always called with interrupts disabled */ |
283 | void |
284 | cia_pci_tbi_try2(struct pci_controller *hose, |
285 | dma_addr_t start, dma_addr_t end) |
286 | { |
287 | void __iomem *bus_addr; |
288 | int ctrl; |
289 | |
290 | /* Put the chip into PCI loopback mode. */ |
291 | mb(); |
292 | ctrl = *(vip)CIA_IOC_CIA_CTRL; |
293 | *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; |
294 | mb(); |
295 | *(vip)CIA_IOC_CIA_CTRL; |
296 | mb(); |
297 | |
298 | /* Read from PCI dense memory space at TBI_ADDR, skipping 32k on |
299 | each read. This forces SG TLB misses. NetBSD claims that the |
300 | TLB entries are not quite LRU, meaning that we need to read more |
301 | times than there are actual tags. The 2117x docs claim strict |
302 | round-robin. Oh well, we've come this far... */ |
303 | /* Even better - as seen on the PYXIS rev 1 the TLB tags 0-3 can |
304 | be filled by the TLB misses *only once* after being invalidated |
305 | (by tbia or direct write). Next misses won't update them even |
306 | though the lock bits are cleared. Tags 4-7 are "quite LRU" though, |
307 | so use them and read at window 3 base exactly 4 times. Reading |
308 | more sometimes makes the chip crazy. -ink */ |
309 | |
310 | bus_addr = cia_ioremap(CIA_BROKEN_TBIA_BASE, 32768 * 4); |
311 | |
312 | cia_readl(bus_addr + 0x00000); |
313 | cia_readl(bus_addr + 0x08000); |
314 | cia_readl(bus_addr + 0x10000); |
315 | cia_readl(bus_addr + 0x18000); |
316 | |
317 | cia_iounmap(bus_addr); |
318 | |
319 | /* Restore normal PCI operation. */ |
320 | mb(); |
321 | *(vip)CIA_IOC_CIA_CTRL = ctrl; |
322 | mb(); |
323 | *(vip)CIA_IOC_CIA_CTRL; |
324 | mb(); |
325 | } |
326 | |
327 | static inline void |
328 | cia_prepare_tbia_workaround(int window) |
329 | { |
330 | unsigned long *ppte, pte; |
331 | long i; |
332 | |
333 | /* Use minimal 1K map. */ |
334 | ppte = memblock_alloc(CIA_BROKEN_TBIA_SIZE, align: 32768); |
335 | if (!ppte) |
336 | panic(fmt: "%s: Failed to allocate %u bytes align=0x%x\n" , |
337 | __func__, CIA_BROKEN_TBIA_SIZE, 32768); |
338 | pte = (virt_to_phys(address: ppte) >> (PAGE_SHIFT - 1)) | 1; |
339 | |
340 | for (i = 0; i < CIA_BROKEN_TBIA_SIZE / sizeof(unsigned long); ++i) |
341 | ppte[i] = pte; |
342 | |
343 | *(vip)CIA_IOC_PCI_Wn_BASE(window) = CIA_BROKEN_TBIA_BASE | 3; |
344 | *(vip)CIA_IOC_PCI_Wn_MASK(window) |
345 | = (CIA_BROKEN_TBIA_SIZE*1024 - 1) & 0xfff00000; |
346 | *(vip)CIA_IOC_PCI_Tn_BASE(window) = virt_to_phys(address: ppte) >> 2; |
347 | } |
348 | |
349 | static void __init |
350 | verify_tb_operation(void) |
351 | { |
352 | static int page[PAGE_SIZE/4] |
353 | __attribute__((aligned(PAGE_SIZE))) |
354 | __initdata = { 0 }; |
355 | |
356 | struct pci_iommu_arena *arena = pci_isa_hose->sg_isa; |
357 | int ctrl, addr0, tag0, pte0, data0; |
358 | int temp, use_tbia_try2 = 0; |
359 | void __iomem *bus_addr; |
360 | |
361 | /* pyxis -- tbia is broken */ |
362 | if (pci_isa_hose->dense_io_base) |
363 | use_tbia_try2 = 1; |
364 | |
365 | /* Put the chip into PCI loopback mode. */ |
366 | mb(); |
367 | ctrl = *(vip)CIA_IOC_CIA_CTRL; |
368 | *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; |
369 | mb(); |
370 | *(vip)CIA_IOC_CIA_CTRL; |
371 | mb(); |
372 | |
373 | /* Write a valid entry directly into the TLB registers. */ |
374 | |
375 | addr0 = arena->dma_base; |
376 | tag0 = addr0 | 1; |
377 | pte0 = (virt_to_phys(address: page) >> (PAGE_SHIFT - 1)) | 1; |
378 | |
379 | *(vip)CIA_IOC_TB_TAGn(0) = tag0; |
380 | *(vip)CIA_IOC_TB_TAGn(1) = 0; |
381 | *(vip)CIA_IOC_TB_TAGn(2) = 0; |
382 | *(vip)CIA_IOC_TB_TAGn(3) = 0; |
383 | *(vip)CIA_IOC_TB_TAGn(4) = 0; |
384 | *(vip)CIA_IOC_TB_TAGn(5) = 0; |
385 | *(vip)CIA_IOC_TB_TAGn(6) = 0; |
386 | *(vip)CIA_IOC_TB_TAGn(7) = 0; |
387 | *(vip)CIA_IOC_TBn_PAGEm(0,0) = pte0; |
388 | *(vip)CIA_IOC_TBn_PAGEm(0,1) = 0; |
389 | *(vip)CIA_IOC_TBn_PAGEm(0,2) = 0; |
390 | *(vip)CIA_IOC_TBn_PAGEm(0,3) = 0; |
391 | mb(); |
392 | |
393 | /* Get a usable bus address */ |
394 | bus_addr = cia_ioremap(addr0, 8*PAGE_SIZE); |
395 | |
396 | /* First, verify we can read back what we've written. If |
397 | this fails, we can't be sure of any of the other testing |
398 | we're going to do, so bail. */ |
399 | /* ??? Actually, we could do the work with machine checks. |
400 | By passing this register update test, we pretty much |
401 | guarantee that cia_pci_tbi_try1 works. If this test |
402 | fails, cia_pci_tbi_try2 might still work. */ |
403 | |
404 | temp = *(vip)CIA_IOC_TB_TAGn(0); |
405 | if (temp != tag0) { |
406 | printk("pci: failed tb register update test " |
407 | "(tag0 %#x != %#x)\n" , temp, tag0); |
408 | goto failed; |
409 | } |
410 | temp = *(vip)CIA_IOC_TB_TAGn(1); |
411 | if (temp != 0) { |
412 | printk("pci: failed tb register update test " |
413 | "(tag1 %#x != 0)\n" , temp); |
414 | goto failed; |
415 | } |
416 | temp = *(vip)CIA_IOC_TBn_PAGEm(0,0); |
417 | if (temp != pte0) { |
418 | printk("pci: failed tb register update test " |
419 | "(pte0 %#x != %#x)\n" , temp, pte0); |
420 | goto failed; |
421 | } |
422 | printk("pci: passed tb register update test\n" ); |
423 | |
424 | /* Second, verify we can actually do I/O through this entry. */ |
425 | |
426 | data0 = 0xdeadbeef; |
427 | page[0] = data0; |
428 | mcheck_expected(0) = 1; |
429 | mcheck_taken(0) = 0; |
430 | mb(); |
431 | temp = cia_readl(bus_addr); |
432 | mb(); |
433 | mcheck_expected(0) = 0; |
434 | mb(); |
435 | if (mcheck_taken(0)) { |
436 | printk("pci: failed sg loopback i/o read test (mcheck)\n" ); |
437 | goto failed; |
438 | } |
439 | if (temp != data0) { |
440 | printk("pci: failed sg loopback i/o read test " |
441 | "(%#x != %#x)\n" , temp, data0); |
442 | goto failed; |
443 | } |
444 | printk("pci: passed sg loopback i/o read test\n" ); |
445 | |
446 | /* Third, try to invalidate the TLB. */ |
447 | |
448 | if (! use_tbia_try2) { |
449 | cia_pci_tbi(hose: arena->hose, start: 0, end: -1); |
450 | temp = *(vip)CIA_IOC_TB_TAGn(0); |
451 | if (temp & 1) { |
452 | use_tbia_try2 = 1; |
453 | printk("pci: failed tbia test; workaround available\n" ); |
454 | } else { |
455 | printk("pci: passed tbia test\n" ); |
456 | } |
457 | } |
458 | |
459 | /* Fourth, verify the TLB snoops the EV5's caches when |
460 | doing a tlb fill. */ |
461 | |
462 | data0 = 0x5adda15e; |
463 | page[0] = data0; |
464 | arena->ptes[4] = pte0; |
465 | mcheck_expected(0) = 1; |
466 | mcheck_taken(0) = 0; |
467 | mb(); |
468 | temp = cia_readl(bus_addr + 4*PAGE_SIZE); |
469 | mb(); |
470 | mcheck_expected(0) = 0; |
471 | mb(); |
472 | if (mcheck_taken(0)) { |
473 | printk("pci: failed pte write cache snoop test (mcheck)\n" ); |
474 | goto failed; |
475 | } |
476 | if (temp != data0) { |
477 | printk("pci: failed pte write cache snoop test " |
478 | "(%#x != %#x)\n" , temp, data0); |
479 | goto failed; |
480 | } |
481 | printk("pci: passed pte write cache snoop test\n" ); |
482 | |
483 | /* Fifth, verify that a previously invalid PTE entry gets |
484 | filled from the page table. */ |
485 | |
486 | data0 = 0xabcdef12; |
487 | page[0] = data0; |
488 | arena->ptes[5] = pte0; |
489 | mcheck_expected(0) = 1; |
490 | mcheck_taken(0) = 0; |
491 | mb(); |
492 | temp = cia_readl(bus_addr + 5*PAGE_SIZE); |
493 | mb(); |
494 | mcheck_expected(0) = 0; |
495 | mb(); |
496 | if (mcheck_taken(0)) { |
497 | printk("pci: failed valid tag invalid pte reload test " |
498 | "(mcheck; workaround available)\n" ); |
499 | /* Work around this bug by aligning new allocations |
500 | on 4 page boundaries. */ |
501 | arena->align_entry = 4; |
502 | } else if (temp != data0) { |
503 | printk("pci: failed valid tag invalid pte reload test " |
504 | "(%#x != %#x)\n" , temp, data0); |
505 | goto failed; |
506 | } else { |
507 | printk("pci: passed valid tag invalid pte reload test\n" ); |
508 | } |
509 | |
510 | /* Sixth, verify machine checks are working. Test invalid |
511 | pte under the same valid tag as we used above. */ |
512 | |
513 | mcheck_expected(0) = 1; |
514 | mcheck_taken(0) = 0; |
515 | mb(); |
516 | temp = cia_readl(bus_addr + 6*PAGE_SIZE); |
517 | mb(); |
518 | mcheck_expected(0) = 0; |
519 | mb(); |
520 | printk("pci: %s pci machine check test\n" , |
521 | mcheck_taken(0) ? "passed" : "failed" ); |
522 | |
523 | /* Clean up after the tests. */ |
524 | arena->ptes[4] = 0; |
525 | arena->ptes[5] = 0; |
526 | |
527 | if (use_tbia_try2) { |
528 | alpha_mv.mv_pci_tbi = cia_pci_tbi_try2; |
529 | |
530 | /* Tags 0-3 must be disabled if we use this workaround. */ |
531 | wmb(); |
532 | *(vip)CIA_IOC_TB_TAGn(0) = 2; |
533 | *(vip)CIA_IOC_TB_TAGn(1) = 2; |
534 | *(vip)CIA_IOC_TB_TAGn(2) = 2; |
535 | *(vip)CIA_IOC_TB_TAGn(3) = 2; |
536 | |
537 | printk("pci: tbia workaround enabled\n" ); |
538 | } |
539 | alpha_mv.mv_pci_tbi(arena->hose, 0, -1); |
540 | |
541 | exit: |
542 | /* unmap the bus addr */ |
543 | cia_iounmap(bus_addr); |
544 | |
545 | /* Restore normal PCI operation. */ |
546 | mb(); |
547 | *(vip)CIA_IOC_CIA_CTRL = ctrl; |
548 | mb(); |
549 | *(vip)CIA_IOC_CIA_CTRL; |
550 | mb(); |
551 | return; |
552 | |
553 | failed: |
554 | printk("pci: disabling sg translation window\n" ); |
555 | *(vip)CIA_IOC_PCI_W0_BASE = 0; |
556 | *(vip)CIA_IOC_PCI_W1_BASE = 0; |
557 | pci_isa_hose->sg_isa = NULL; |
558 | alpha_mv.mv_pci_tbi = NULL; |
559 | goto exit; |
560 | } |
561 | |
562 | #if defined(ALPHA_RESTORE_SRM_SETUP) |
563 | /* Save CIA configuration data as the console had it set up. */ |
564 | struct |
565 | { |
566 | unsigned int hae_mem; |
567 | unsigned int hae_io; |
568 | unsigned int pci_dac_offset; |
569 | unsigned int err_mask; |
570 | unsigned int cia_ctrl; |
571 | unsigned int cia_cnfg; |
572 | struct { |
573 | unsigned int w_base; |
574 | unsigned int w_mask; |
575 | unsigned int t_base; |
576 | } window[4]; |
577 | } saved_config __attribute((common)); |
578 | |
579 | void |
580 | cia_save_srm_settings(int is_pyxis) |
581 | { |
582 | int i; |
583 | |
584 | /* Save some important registers. */ |
585 | saved_config.err_mask = *(vip)CIA_IOC_ERR_MASK; |
586 | saved_config.cia_ctrl = *(vip)CIA_IOC_CIA_CTRL; |
587 | saved_config.hae_mem = *(vip)CIA_IOC_HAE_MEM; |
588 | saved_config.hae_io = *(vip)CIA_IOC_HAE_IO; |
589 | saved_config.pci_dac_offset = *(vip)CIA_IOC_PCI_W_DAC; |
590 | |
591 | if (is_pyxis) |
592 | saved_config.cia_cnfg = *(vip)CIA_IOC_CIA_CNFG; |
593 | else |
594 | saved_config.cia_cnfg = 0; |
595 | |
596 | /* Save DMA windows configuration. */ |
597 | for (i = 0; i < 4; i++) { |
598 | saved_config.window[i].w_base = *(vip)CIA_IOC_PCI_Wn_BASE(i); |
599 | saved_config.window[i].w_mask = *(vip)CIA_IOC_PCI_Wn_MASK(i); |
600 | saved_config.window[i].t_base = *(vip)CIA_IOC_PCI_Tn_BASE(i); |
601 | } |
602 | mb(); |
603 | } |
604 | |
605 | void |
606 | cia_restore_srm_settings(void) |
607 | { |
608 | int i; |
609 | |
610 | for (i = 0; i < 4; i++) { |
611 | *(vip)CIA_IOC_PCI_Wn_BASE(i) = saved_config.window[i].w_base; |
612 | *(vip)CIA_IOC_PCI_Wn_MASK(i) = saved_config.window[i].w_mask; |
613 | *(vip)CIA_IOC_PCI_Tn_BASE(i) = saved_config.window[i].t_base; |
614 | } |
615 | |
616 | *(vip)CIA_IOC_HAE_MEM = saved_config.hae_mem; |
617 | *(vip)CIA_IOC_HAE_IO = saved_config.hae_io; |
618 | *(vip)CIA_IOC_PCI_W_DAC = saved_config.pci_dac_offset; |
619 | *(vip)CIA_IOC_ERR_MASK = saved_config.err_mask; |
620 | *(vip)CIA_IOC_CIA_CTRL = saved_config.cia_ctrl; |
621 | |
622 | if (saved_config.cia_cnfg) /* Must be pyxis. */ |
623 | *(vip)CIA_IOC_CIA_CNFG = saved_config.cia_cnfg; |
624 | |
625 | mb(); |
626 | } |
627 | #else /* ALPHA_RESTORE_SRM_SETUP */ |
628 | #define cia_save_srm_settings(p) do {} while (0) |
629 | #define cia_restore_srm_settings() do {} while (0) |
630 | #endif /* ALPHA_RESTORE_SRM_SETUP */ |
631 | |
632 | |
633 | static void __init |
634 | do_init_arch(int is_pyxis) |
635 | { |
636 | struct pci_controller *hose; |
637 | int temp, cia_rev, tbia_window; |
638 | |
639 | cia_rev = *(vip)CIA_IOC_CIA_REV & CIA_REV_MASK; |
640 | printk("pci: cia revision %d%s\n" , |
641 | cia_rev, is_pyxis ? " (pyxis)" : "" ); |
642 | |
643 | if (alpha_using_srm) |
644 | cia_save_srm_settings(is_pyxis); |
645 | |
646 | /* Set up error reporting. */ |
647 | temp = *(vip)CIA_IOC_ERR_MASK; |
648 | temp &= ~(CIA_ERR_CPU_PE | CIA_ERR_MEM_NEM | CIA_ERR_PA_PTE_INV |
649 | | CIA_ERR_RCVD_MAS_ABT | CIA_ERR_RCVD_TAR_ABT); |
650 | *(vip)CIA_IOC_ERR_MASK = temp; |
651 | |
652 | /* Clear all currently pending errors. */ |
653 | temp = *(vip)CIA_IOC_CIA_ERR; |
654 | *(vip)CIA_IOC_CIA_ERR = temp; |
655 | |
656 | /* Turn on mchecks. */ |
657 | temp = *(vip)CIA_IOC_CIA_CTRL; |
658 | temp |= CIA_CTRL_FILL_ERR_EN | CIA_CTRL_MCHK_ERR_EN; |
659 | *(vip)CIA_IOC_CIA_CTRL = temp; |
660 | |
661 | /* Clear the CFG register, which gets used for PCI config space |
662 | accesses. That is the way we want to use it, and we do not |
663 | want to depend on what ARC or SRM might have left behind. */ |
664 | *(vip)CIA_IOC_CFG = 0; |
665 | |
666 | /* Zero the HAEs. */ |
667 | *(vip)CIA_IOC_HAE_MEM = 0; |
668 | *(vip)CIA_IOC_HAE_IO = 0; |
669 | |
670 | /* For PYXIS, we always use BWX bus and i/o accesses. To that end, |
671 | make sure they're enabled on the controller. At the same time, |
672 | enable the monster window. */ |
673 | if (is_pyxis) { |
674 | temp = *(vip)CIA_IOC_CIA_CNFG; |
675 | temp |= CIA_CNFG_IOA_BWEN | CIA_CNFG_PCI_MWEN; |
676 | *(vip)CIA_IOC_CIA_CNFG = temp; |
677 | } |
678 | |
679 | /* Synchronize with all previous changes. */ |
680 | mb(); |
681 | *(vip)CIA_IOC_CIA_REV; |
682 | |
683 | /* |
684 | * Create our single hose. |
685 | */ |
686 | |
687 | pci_isa_hose = hose = alloc_pci_controller(); |
688 | hose->io_space = &ioport_resource; |
689 | hose->mem_space = &iomem_resource; |
690 | hose->index = 0; |
691 | |
692 | if (! is_pyxis) { |
693 | struct resource *hae_mem = alloc_resource(); |
694 | hose->mem_space = hae_mem; |
695 | |
696 | hae_mem->start = 0; |
697 | hae_mem->end = CIA_MEM_R1_MASK; |
698 | hae_mem->name = pci_hae0_name; |
699 | hae_mem->flags = IORESOURCE_MEM; |
700 | |
701 | if (request_resource(root: &iomem_resource, new: hae_mem) < 0) |
702 | printk(KERN_ERR "Failed to request HAE_MEM\n" ); |
703 | |
704 | hose->sparse_mem_base = CIA_SPARSE_MEM - IDENT_ADDR; |
705 | hose->dense_mem_base = CIA_DENSE_MEM - IDENT_ADDR; |
706 | hose->sparse_io_base = CIA_IO - IDENT_ADDR; |
707 | hose->dense_io_base = 0; |
708 | } else { |
709 | hose->sparse_mem_base = 0; |
710 | hose->dense_mem_base = CIA_BW_MEM - IDENT_ADDR; |
711 | hose->sparse_io_base = 0; |
712 | hose->dense_io_base = CIA_BW_IO - IDENT_ADDR; |
713 | } |
714 | |
715 | /* |
716 | * Set up the PCI to main memory translation windows. |
717 | * |
718 | * Window 0 is S/G 8MB at 8MB (for isa) |
719 | * Window 1 is S/G 1MB at 768MB (for tbia) (unused for CIA rev 1) |
720 | * Window 2 is direct access 2GB at 2GB |
721 | * Window 3 is DAC access 4GB at 8GB (or S/G for tbia if CIA rev 1) |
722 | * |
723 | * ??? NetBSD hints that page tables must be aligned to 32K, |
724 | * possibly due to a hardware bug. This is over-aligned |
725 | * from the 8K alignment one would expect for an 8MB window. |
726 | * No description of what revisions affected. |
727 | */ |
728 | |
729 | hose->sg_pci = NULL; |
730 | hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 32768); |
731 | |
732 | __direct_map_base = 0x80000000; |
733 | __direct_map_size = 0x80000000; |
734 | |
735 | *(vip)CIA_IOC_PCI_W0_BASE = hose->sg_isa->dma_base | 3; |
736 | *(vip)CIA_IOC_PCI_W0_MASK = (hose->sg_isa->size - 1) & 0xfff00000; |
737 | *(vip)CIA_IOC_PCI_T0_BASE = virt_to_phys(hose->sg_isa->ptes) >> 2; |
738 | |
739 | *(vip)CIA_IOC_PCI_W2_BASE = __direct_map_base | 1; |
740 | *(vip)CIA_IOC_PCI_W2_MASK = (__direct_map_size - 1) & 0xfff00000; |
741 | *(vip)CIA_IOC_PCI_T2_BASE = 0 >> 2; |
742 | |
743 | /* On PYXIS we have the monster window, selected by bit 40, so |
744 | there is no need for window3 to be enabled. |
745 | |
746 | On CIA, we don't have true arbitrary addressing -- bits <39:32> |
747 | are compared against W_DAC. We can, however, directly map 4GB, |
748 | which is better than before. However, due to assumptions made |
749 | elsewhere, we should not claim that we support DAC unless that |
750 | 4GB covers all of physical memory. |
751 | |
752 | On CIA rev 1, apparently W1 and W2 can't be used for SG. |
753 | At least, there are reports that it doesn't work for Alcor. |
754 | In that case, we have no choice but to use W3 for the TBIA |
755 | workaround, which means we can't use DAC at all. */ |
756 | |
757 | tbia_window = 1; |
758 | if (is_pyxis) { |
759 | *(vip)CIA_IOC_PCI_W3_BASE = 0; |
760 | } else if (cia_rev == 1) { |
761 | *(vip)CIA_IOC_PCI_W1_BASE = 0; |
762 | tbia_window = 3; |
763 | } else if (max_low_pfn > (0x100000000UL >> PAGE_SHIFT)) { |
764 | *(vip)CIA_IOC_PCI_W3_BASE = 0; |
765 | } else { |
766 | *(vip)CIA_IOC_PCI_W3_BASE = 0x00000000 | 1 | 8; |
767 | *(vip)CIA_IOC_PCI_W3_MASK = 0xfff00000; |
768 | *(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2; |
769 | |
770 | alpha_mv.pci_dac_offset = 0x200000000UL; |
771 | *(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32; |
772 | } |
773 | |
774 | /* Prepare workaround for apparently broken tbia. */ |
775 | cia_prepare_tbia_workaround(window: tbia_window); |
776 | } |
777 | |
778 | void __init |
779 | cia_init_arch(void) |
780 | { |
781 | do_init_arch(is_pyxis: 0); |
782 | } |
783 | |
784 | void __init |
785 | pyxis_init_arch(void) |
786 | { |
787 | /* On pyxis machines we can precisely calculate the |
788 | CPU clock frequency using pyxis real time counter. |
789 | It's especially useful for SX164 with broken RTC. |
790 | |
791 | Both CPU and chipset are driven by the single 16.666M |
792 | or 16.667M crystal oscillator. PYXIS_RT_COUNT clock is |
793 | 66.66 MHz. -ink */ |
794 | |
795 | unsigned int cc0, cc1; |
796 | unsigned long pyxis_cc; |
797 | |
798 | __asm__ __volatile__ ("rpcc %0" : "=r" (cc0)); |
799 | pyxis_cc = *(vulp)PYXIS_RT_COUNT; |
800 | do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096); |
801 | __asm__ __volatile__ ("rpcc %0" : "=r" (cc1)); |
802 | cc1 -= cc0; |
803 | hwrpb->cycle_freq = ((cc1 >> 11) * 100000000UL) / 3; |
804 | hwrpb_update_checksum(hwrpb); |
805 | |
806 | do_init_arch(is_pyxis: 1); |
807 | } |
808 | |
809 | void |
810 | cia_kill_arch(int mode) |
811 | { |
812 | if (alpha_using_srm) |
813 | cia_restore_srm_settings(); |
814 | } |
815 | |
816 | void __init |
817 | cia_init_pci(void) |
818 | { |
819 | /* Must delay this from init_arch, as we need machine checks. */ |
820 | verify_tb_operation(); |
821 | common_init_pci(); |
822 | } |
823 | |
824 | static inline void |
825 | cia_pci_clr_err(void) |
826 | { |
827 | int jd; |
828 | |
829 | jd = *(vip)CIA_IOC_CIA_ERR; |
830 | *(vip)CIA_IOC_CIA_ERR = jd; |
831 | mb(); |
832 | *(vip)CIA_IOC_CIA_ERR; /* re-read to force write. */ |
833 | } |
834 | |
835 | #ifdef CONFIG_VERBOSE_MCHECK |
836 | static void |
837 | cia_decode_pci_error(struct el_CIA_sysdata_mcheck *cia, const char *msg) |
838 | { |
839 | static const char * const pci_cmd_desc[16] = { |
840 | "Interrupt Acknowledge" , "Special Cycle" , "I/O Read" , |
841 | "I/O Write" , "Reserved 0x4" , "Reserved 0x5" , "Memory Read" , |
842 | "Memory Write" , "Reserved 0x8" , "Reserved 0x9" , |
843 | "Configuration Read" , "Configuration Write" , |
844 | "Memory Read Multiple" , "Dual Address Cycle" , |
845 | "Memory Read Line" , "Memory Write and Invalidate" |
846 | }; |
847 | |
848 | if (cia->cia_err & (CIA_ERR_COR_ERR |
849 | | CIA_ERR_UN_COR_ERR |
850 | | CIA_ERR_MEM_NEM |
851 | | CIA_ERR_PA_PTE_INV)) { |
852 | static const char * const window_desc[6] = { |
853 | "No window active" , "Window 0 hit" , "Window 1 hit" , |
854 | "Window 2 hit" , "Window 3 hit" , "Monster window hit" |
855 | }; |
856 | |
857 | const char *window; |
858 | const char *cmd; |
859 | unsigned long addr, tmp; |
860 | int lock, dac; |
861 | |
862 | cmd = pci_cmd_desc[cia->pci_err0 & 0x7]; |
863 | lock = (cia->pci_err0 >> 4) & 1; |
864 | dac = (cia->pci_err0 >> 5) & 1; |
865 | |
866 | tmp = (cia->pci_err0 >> 8) & 0x1F; |
867 | tmp = ffs(tmp); |
868 | window = window_desc[tmp]; |
869 | |
870 | addr = cia->pci_err1; |
871 | if (dac) { |
872 | tmp = *(vip)CIA_IOC_PCI_W_DAC & 0xFFUL; |
873 | addr |= tmp << 32; |
874 | } |
875 | |
876 | printk(KERN_CRIT "CIA machine check: %s\n" , msg); |
877 | printk(KERN_CRIT " DMA command: %s\n" , cmd); |
878 | printk(KERN_CRIT " PCI address: %#010lx\n" , addr); |
879 | printk(KERN_CRIT " %s, Lock: %d, DAC: %d\n" , |
880 | window, lock, dac); |
881 | } else if (cia->cia_err & (CIA_ERR_PERR |
882 | | CIA_ERR_PCI_ADDR_PE |
883 | | CIA_ERR_RCVD_MAS_ABT |
884 | | CIA_ERR_RCVD_TAR_ABT |
885 | | CIA_ERR_IOA_TIMEOUT)) { |
886 | static const char * const master_st_desc[16] = { |
887 | "Idle" , "Drive bus" , "Address step cycle" , |
888 | "Address cycle" , "Data cycle" , "Last read data cycle" , |
889 | "Last write data cycle" , "Read stop cycle" , |
890 | "Write stop cycle" , "Read turnaround cycle" , |
891 | "Write turnaround cycle" , "Reserved 0xB" , |
892 | "Reserved 0xC" , "Reserved 0xD" , "Reserved 0xE" , |
893 | "Unknown state" |
894 | }; |
895 | static const char * const target_st_desc[16] = { |
896 | "Idle" , "Busy" , "Read data cycle" , "Write data cycle" , |
897 | "Read stop cycle" , "Write stop cycle" , |
898 | "Read turnaround cycle" , "Write turnaround cycle" , |
899 | "Read wait cycle" , "Write wait cycle" , |
900 | "Reserved 0xA" , "Reserved 0xB" , "Reserved 0xC" , |
901 | "Reserved 0xD" , "Reserved 0xE" , "Unknown state" |
902 | }; |
903 | |
904 | const char *cmd; |
905 | const char *master, *target; |
906 | unsigned long addr, tmp; |
907 | int dac; |
908 | |
909 | master = master_st_desc[(cia->pci_err0 >> 16) & 0xF]; |
910 | target = target_st_desc[(cia->pci_err0 >> 20) & 0xF]; |
911 | cmd = pci_cmd_desc[(cia->pci_err0 >> 24) & 0xF]; |
912 | dac = (cia->pci_err0 >> 28) & 1; |
913 | |
914 | addr = cia->pci_err2; |
915 | if (dac) { |
916 | tmp = *(volatile int *)CIA_IOC_PCI_W_DAC & 0xFFUL; |
917 | addr |= tmp << 32; |
918 | } |
919 | |
920 | printk(KERN_CRIT "CIA machine check: %s\n" , msg); |
921 | printk(KERN_CRIT " PCI command: %s\n" , cmd); |
922 | printk(KERN_CRIT " Master state: %s, Target state: %s\n" , |
923 | master, target); |
924 | printk(KERN_CRIT " PCI address: %#010lx, DAC: %d\n" , |
925 | addr, dac); |
926 | } else { |
927 | printk(KERN_CRIT "CIA machine check: %s\n" , msg); |
928 | printk(KERN_CRIT " Unknown PCI error\n" ); |
929 | printk(KERN_CRIT " PCI_ERR0 = %#08lx" , cia->pci_err0); |
930 | printk(KERN_CRIT " PCI_ERR1 = %#08lx" , cia->pci_err1); |
931 | printk(KERN_CRIT " PCI_ERR2 = %#08lx" , cia->pci_err2); |
932 | } |
933 | } |
934 | |
935 | static void |
936 | cia_decode_mem_error(struct el_CIA_sysdata_mcheck *cia, const char *msg) |
937 | { |
938 | unsigned long mem_port_addr; |
939 | unsigned long mem_port_mask; |
940 | const char *mem_port_cmd; |
941 | const char *seq_state; |
942 | const char *set_select; |
943 | unsigned long tmp; |
944 | |
945 | /* If this is a DMA command, also decode the PCI bits. */ |
946 | if ((cia->mem_err1 >> 20) & 1) |
947 | cia_decode_pci_error(cia, msg); |
948 | else |
949 | printk(KERN_CRIT "CIA machine check: %s\n" , msg); |
950 | |
951 | mem_port_addr = cia->mem_err0 & 0xfffffff0; |
952 | mem_port_addr |= (cia->mem_err1 & 0x83UL) << 32; |
953 | |
954 | mem_port_mask = (cia->mem_err1 >> 12) & 0xF; |
955 | |
956 | tmp = (cia->mem_err1 >> 8) & 0xF; |
957 | tmp |= ((cia->mem_err1 >> 20) & 1) << 4; |
958 | if ((tmp & 0x1E) == 0x06) |
959 | mem_port_cmd = "WRITE BLOCK or WRITE BLOCK LOCK" ; |
960 | else if ((tmp & 0x1C) == 0x08) |
961 | mem_port_cmd = "READ MISS or READ MISS MODIFY" ; |
962 | else if (tmp == 0x1C) |
963 | mem_port_cmd = "BC VICTIM" ; |
964 | else if ((tmp & 0x1E) == 0x0E) |
965 | mem_port_cmd = "READ MISS MODIFY" ; |
966 | else if ((tmp & 0x1C) == 0x18) |
967 | mem_port_cmd = "DMA READ or DMA READ MODIFY" ; |
968 | else if ((tmp & 0x1E) == 0x12) |
969 | mem_port_cmd = "DMA WRITE" ; |
970 | else |
971 | mem_port_cmd = "Unknown" ; |
972 | |
973 | tmp = (cia->mem_err1 >> 16) & 0xF; |
974 | switch (tmp) { |
975 | case 0x0: |
976 | seq_state = "Idle" ; |
977 | break; |
978 | case 0x1: |
979 | seq_state = "DMA READ or DMA WRITE" ; |
980 | break; |
981 | case 0x2: case 0x3: |
982 | seq_state = "READ MISS (or READ MISS MODIFY) with victim" ; |
983 | break; |
984 | case 0x4: case 0x5: case 0x6: |
985 | seq_state = "READ MISS (or READ MISS MODIFY) with no victim" ; |
986 | break; |
987 | case 0x8: case 0x9: case 0xB: |
988 | seq_state = "Refresh" ; |
989 | break; |
990 | case 0xC: |
991 | seq_state = "Idle, waiting for DMA pending read" ; |
992 | break; |
993 | case 0xE: case 0xF: |
994 | seq_state = "Idle, ras precharge" ; |
995 | break; |
996 | default: |
997 | seq_state = "Unknown" ; |
998 | break; |
999 | } |
1000 | |
1001 | tmp = (cia->mem_err1 >> 24) & 0x1F; |
1002 | switch (tmp) { |
1003 | case 0x00: set_select = "Set 0 selected" ; break; |
1004 | case 0x01: set_select = "Set 1 selected" ; break; |
1005 | case 0x02: set_select = "Set 2 selected" ; break; |
1006 | case 0x03: set_select = "Set 3 selected" ; break; |
1007 | case 0x04: set_select = "Set 4 selected" ; break; |
1008 | case 0x05: set_select = "Set 5 selected" ; break; |
1009 | case 0x06: set_select = "Set 6 selected" ; break; |
1010 | case 0x07: set_select = "Set 7 selected" ; break; |
1011 | case 0x08: set_select = "Set 8 selected" ; break; |
1012 | case 0x09: set_select = "Set 9 selected" ; break; |
1013 | case 0x0A: set_select = "Set A selected" ; break; |
1014 | case 0x0B: set_select = "Set B selected" ; break; |
1015 | case 0x0C: set_select = "Set C selected" ; break; |
1016 | case 0x0D: set_select = "Set D selected" ; break; |
1017 | case 0x0E: set_select = "Set E selected" ; break; |
1018 | case 0x0F: set_select = "Set F selected" ; break; |
1019 | case 0x10: set_select = "No set selected" ; break; |
1020 | case 0x1F: set_select = "Refresh cycle" ; break; |
1021 | default: set_select = "Unknown" ; break; |
1022 | } |
1023 | |
1024 | printk(KERN_CRIT " Memory port command: %s\n" , mem_port_cmd); |
1025 | printk(KERN_CRIT " Memory port address: %#010lx, mask: %#lx\n" , |
1026 | mem_port_addr, mem_port_mask); |
1027 | printk(KERN_CRIT " Memory sequencer state: %s\n" , seq_state); |
1028 | printk(KERN_CRIT " Memory set: %s\n" , set_select); |
1029 | } |
1030 | |
1031 | static void |
1032 | cia_decode_ecc_error(struct el_CIA_sysdata_mcheck *cia, const char *msg) |
1033 | { |
1034 | long syn; |
1035 | long i; |
1036 | const char *fmt; |
1037 | |
1038 | cia_decode_mem_error(cia, msg); |
1039 | |
1040 | syn = cia->cia_syn & 0xff; |
1041 | if (syn == (syn & -syn)) { |
1042 | fmt = KERN_CRIT " ECC syndrome %#x -- check bit %d\n" ; |
1043 | i = ffs(syn) - 1; |
1044 | } else { |
1045 | static unsigned char const data_bit[64] = { |
1046 | 0xCE, 0xCB, 0xD3, 0xD5, |
1047 | 0xD6, 0xD9, 0xDA, 0xDC, |
1048 | 0x23, 0x25, 0x26, 0x29, |
1049 | 0x2A, 0x2C, 0x31, 0x34, |
1050 | 0x0E, 0x0B, 0x13, 0x15, |
1051 | 0x16, 0x19, 0x1A, 0x1C, |
1052 | 0xE3, 0xE5, 0xE6, 0xE9, |
1053 | 0xEA, 0xEC, 0xF1, 0xF4, |
1054 | 0x4F, 0x4A, 0x52, 0x54, |
1055 | 0x57, 0x58, 0x5B, 0x5D, |
1056 | 0xA2, 0xA4, 0xA7, 0xA8, |
1057 | 0xAB, 0xAD, 0xB0, 0xB5, |
1058 | 0x8F, 0x8A, 0x92, 0x94, |
1059 | 0x97, 0x98, 0x9B, 0x9D, |
1060 | 0x62, 0x64, 0x67, 0x68, |
1061 | 0x6B, 0x6D, 0x70, 0x75 |
1062 | }; |
1063 | |
1064 | for (i = 0; i < 64; ++i) |
1065 | if (data_bit[i] == syn) |
1066 | break; |
1067 | |
1068 | if (i < 64) |
1069 | fmt = KERN_CRIT " ECC syndrome %#x -- data bit %d\n" ; |
1070 | else |
1071 | fmt = KERN_CRIT " ECC syndrome %#x -- unknown bit\n" ; |
1072 | } |
1073 | |
1074 | printk (fmt, syn, i); |
1075 | } |
1076 | |
1077 | static void |
1078 | cia_decode_parity_error(struct el_CIA_sysdata_mcheck *cia) |
1079 | { |
1080 | static const char * const cmd_desc[16] = { |
1081 | "NOP" , "LOCK" , "FETCH" , "FETCH_M" , "MEMORY BARRIER" , |
1082 | "SET DIRTY" , "WRITE BLOCK" , "WRITE BLOCK LOCK" , |
1083 | "READ MISS0" , "READ MISS1" , "READ MISS MOD0" , |
1084 | "READ MISS MOD1" , "BCACHE VICTIM" , "Spare" , |
1085 | "READ MISS MOD STC0" , "READ MISS MOD STC1" |
1086 | }; |
1087 | |
1088 | unsigned long addr; |
1089 | unsigned long mask; |
1090 | const char *cmd; |
1091 | int par; |
1092 | |
1093 | addr = cia->cpu_err0 & 0xfffffff0; |
1094 | addr |= (cia->cpu_err1 & 0x83UL) << 32; |
1095 | cmd = cmd_desc[(cia->cpu_err1 >> 8) & 0xF]; |
1096 | mask = (cia->cpu_err1 >> 12) & 0xF; |
1097 | par = (cia->cpu_err1 >> 21) & 1; |
1098 | |
1099 | printk(KERN_CRIT "CIA machine check: System bus parity error\n" ); |
1100 | printk(KERN_CRIT " Command: %s, Parity bit: %d\n" , cmd, par); |
1101 | printk(KERN_CRIT " Address: %#010lx, Mask: %#lx\n" , addr, mask); |
1102 | } |
1103 | #endif /* CONFIG_VERBOSE_MCHECK */ |
1104 | |
1105 | |
1106 | static int |
1107 | cia_decode_mchk(unsigned long la_ptr) |
1108 | { |
1109 | struct el_common *com; |
1110 | struct el_CIA_sysdata_mcheck *cia; |
1111 | |
1112 | com = (void *)la_ptr; |
1113 | cia = (void *)(la_ptr + com->sys_offset); |
1114 | |
1115 | if ((cia->cia_err & CIA_ERR_VALID) == 0) |
1116 | return 0; |
1117 | |
1118 | #ifdef CONFIG_VERBOSE_MCHECK |
1119 | if (!alpha_verbose_mcheck) |
1120 | return 1; |
1121 | |
1122 | switch (ffs(cia->cia_err & 0xfff) - 1) { |
1123 | case 0: /* CIA_ERR_COR_ERR */ |
1124 | cia_decode_ecc_error(cia, "Corrected ECC error" ); |
1125 | break; |
1126 | case 1: /* CIA_ERR_UN_COR_ERR */ |
1127 | cia_decode_ecc_error(cia, "Uncorrected ECC error" ); |
1128 | break; |
1129 | case 2: /* CIA_ERR_CPU_PE */ |
1130 | cia_decode_parity_error(cia); |
1131 | break; |
1132 | case 3: /* CIA_ERR_MEM_NEM */ |
1133 | cia_decode_mem_error(cia, "Access to nonexistent memory" ); |
1134 | break; |
1135 | case 4: /* CIA_ERR_PCI_SERR */ |
1136 | cia_decode_pci_error(cia, "PCI bus system error" ); |
1137 | break; |
1138 | case 5: /* CIA_ERR_PERR */ |
1139 | cia_decode_pci_error(cia, "PCI data parity error" ); |
1140 | break; |
1141 | case 6: /* CIA_ERR_PCI_ADDR_PE */ |
1142 | cia_decode_pci_error(cia, "PCI address parity error" ); |
1143 | break; |
1144 | case 7: /* CIA_ERR_RCVD_MAS_ABT */ |
1145 | cia_decode_pci_error(cia, "PCI master abort" ); |
1146 | break; |
1147 | case 8: /* CIA_ERR_RCVD_TAR_ABT */ |
1148 | cia_decode_pci_error(cia, "PCI target abort" ); |
1149 | break; |
1150 | case 9: /* CIA_ERR_PA_PTE_INV */ |
1151 | cia_decode_pci_error(cia, "PCI invalid PTE" ); |
1152 | break; |
1153 | case 10: /* CIA_ERR_FROM_WRT_ERR */ |
1154 | cia_decode_mem_error(cia, "Write to flash ROM attempted" ); |
1155 | break; |
1156 | case 11: /* CIA_ERR_IOA_TIMEOUT */ |
1157 | cia_decode_pci_error(cia, "I/O timeout" ); |
1158 | break; |
1159 | } |
1160 | |
1161 | if (cia->cia_err & CIA_ERR_LOST_CORR_ERR) |
1162 | printk(KERN_CRIT "CIA lost machine check: " |
1163 | "Correctable ECC error\n" ); |
1164 | if (cia->cia_err & CIA_ERR_LOST_UN_CORR_ERR) |
1165 | printk(KERN_CRIT "CIA lost machine check: " |
1166 | "Uncorrectable ECC error\n" ); |
1167 | if (cia->cia_err & CIA_ERR_LOST_CPU_PE) |
1168 | printk(KERN_CRIT "CIA lost machine check: " |
1169 | "System bus parity error\n" ); |
1170 | if (cia->cia_err & CIA_ERR_LOST_MEM_NEM) |
1171 | printk(KERN_CRIT "CIA lost machine check: " |
1172 | "Access to nonexistent memory\n" ); |
1173 | if (cia->cia_err & CIA_ERR_LOST_PERR) |
1174 | printk(KERN_CRIT "CIA lost machine check: " |
1175 | "PCI data parity error\n" ); |
1176 | if (cia->cia_err & CIA_ERR_LOST_PCI_ADDR_PE) |
1177 | printk(KERN_CRIT "CIA lost machine check: " |
1178 | "PCI address parity error\n" ); |
1179 | if (cia->cia_err & CIA_ERR_LOST_RCVD_MAS_ABT) |
1180 | printk(KERN_CRIT "CIA lost machine check: " |
1181 | "PCI master abort\n" ); |
1182 | if (cia->cia_err & CIA_ERR_LOST_RCVD_TAR_ABT) |
1183 | printk(KERN_CRIT "CIA lost machine check: " |
1184 | "PCI target abort\n" ); |
1185 | if (cia->cia_err & CIA_ERR_LOST_PA_PTE_INV) |
1186 | printk(KERN_CRIT "CIA lost machine check: " |
1187 | "PCI invalid PTE\n" ); |
1188 | if (cia->cia_err & CIA_ERR_LOST_FROM_WRT_ERR) |
1189 | printk(KERN_CRIT "CIA lost machine check: " |
1190 | "Write to flash ROM attempted\n" ); |
1191 | if (cia->cia_err & CIA_ERR_LOST_IOA_TIMEOUT) |
1192 | printk(KERN_CRIT "CIA lost machine check: " |
1193 | "I/O timeout\n" ); |
1194 | #endif /* CONFIG_VERBOSE_MCHECK */ |
1195 | |
1196 | return 1; |
1197 | } |
1198 | |
1199 | void |
1200 | cia_machine_check(unsigned long vector, unsigned long la_ptr) |
1201 | { |
1202 | int expected; |
1203 | |
1204 | /* Clear the error before any reporting. */ |
1205 | mb(); |
1206 | mb(); /* magic */ |
1207 | draina(); |
1208 | cia_pci_clr_err(); |
1209 | wrmces(mces: rdmces()); /* reset machine check pending flag. */ |
1210 | mb(); |
1211 | |
1212 | expected = mcheck_expected(0); |
1213 | if (!expected && vector == 0x660) |
1214 | expected = cia_decode_mchk(la_ptr); |
1215 | process_mcheck_info(vector, la_ptr, machine: "CIA" , expected); |
1216 | } |
1217 | |