| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Chip specific defines for DA8XX/OMAP L1XX SoC |
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| 4 | * |
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| 5 | * Author: Mark A. Greer <mgreer@mvista.com> |
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| 6 | * |
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| 7 | * 2007, 2009-2010 (c) MontaVista Software, Inc. |
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| 8 | */ |
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| 9 | #ifndef __ASM_ARCH_DAVINCI_DA8XX_H |
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| 10 | #define __ASM_ARCH_DAVINCI_DA8XX_H |
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| 11 | |
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| 12 | #include <linux/dma-mapping.h> |
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| 13 | #include <linux/platform_device.h> |
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| 14 | #include <linux/videodev2.h> |
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| 15 | #include <linux/reboot.h> |
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| 16 | #include <linux/regmap.h> |
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| 17 | |
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| 18 | #include "hardware.h" |
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| 19 | #include "pm.h" |
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| 20 | |
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| 21 | #include <media/davinci/vpif_types.h> |
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| 22 | |
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| 23 | extern void __iomem *da8xx_syscfg0_base; |
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| 24 | extern void __iomem *da8xx_syscfg1_base; |
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| 25 | |
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| 26 | /* |
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| 27 | * The cp_intc interrupt controller for the da8xx isn't in the same |
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| 28 | * chunk of physical memory space as the other registers (like it is |
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| 29 | * on the davincis) so it needs to be mapped separately. It will be |
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| 30 | * mapped early on when the I/O space is mapped and we'll put it just |
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| 31 | * before the I/O space in the processor's virtual memory space. |
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| 32 | */ |
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| 33 | #define DA8XX_CP_INTC_BASE 0xfffee000 |
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| 34 | #define DA8XX_CP_INTC_SIZE SZ_8K |
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| 35 | #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) |
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| 36 | |
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| 37 | #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) |
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| 38 | #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) |
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| 39 | #define DA8XX_JTAG_ID_REG 0x18 |
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| 40 | #define DA8XX_HOST1CFG_REG 0x44 |
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| 41 | #define DA8XX_CHIPSIG_REG 0x174 |
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| 42 | #define DA8XX_CFGCHIP0_REG 0x17c |
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| 43 | #define DA8XX_CFGCHIP1_REG 0x180 |
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| 44 | #define DA8XX_CFGCHIP2_REG 0x184 |
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| 45 | #define DA8XX_CFGCHIP3_REG 0x188 |
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| 46 | #define DA8XX_CFGCHIP4_REG 0x18c |
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| 47 | |
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| 48 | #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) |
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| 49 | #define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) |
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| 50 | #define DA8XX_DEEPSLEEP_REG 0x8 |
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| 51 | #define DA8XX_PWRDN_REG 0x18 |
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| 52 | |
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| 53 | #define DA8XX_PSC0_BASE 0x01c10000 |
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| 54 | #define DA8XX_PLL0_BASE 0x01c11000 |
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| 55 | #define DA8XX_TIMER64P0_BASE 0x01c20000 |
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| 56 | #define DA8XX_TIMER64P1_BASE 0x01c21000 |
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| 57 | #define DA8XX_VPIF_BASE 0x01e17000 |
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| 58 | #define DA8XX_GPIO_BASE 0x01e26000 |
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| 59 | #define DA8XX_PSC1_BASE 0x01e27000 |
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| 60 | |
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| 61 | #define DA8XX_DSP_L2_RAM_BASE 0x11800000 |
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| 62 | #define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000) |
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| 63 | #define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000) |
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| 64 | |
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| 65 | #define DA8XX_AEMIF_CS2_BASE 0x60000000 |
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| 66 | #define DA8XX_AEMIF_CS3_BASE 0x62000000 |
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| 67 | #define DA8XX_AEMIF_CTL_BASE 0x68000000 |
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| 68 | #define DA8XX_SHARED_RAM_BASE 0x80000000 |
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| 69 | #define DA8XX_ARM_RAM_BASE 0xffff0000 |
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| 70 | |
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| 71 | void da850_init(void); |
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| 72 | |
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| 73 | int da850_register_vpif_display |
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| 74 | (struct vpif_display_config *display_config); |
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| 75 | int da850_register_vpif_capture |
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| 76 | (struct vpif_capture_config *capture_config); |
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| 77 | struct regmap *da8xx_get_cfgchip(void); |
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| 78 | void __iomem *da8xx_get_mem_ctlr(void); |
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| 79 | |
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| 80 | #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ |
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| 81 | |
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