| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Mbus-L to Mbus Bridge Registers */ |
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| 3 | |
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| 4 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
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| 5 | #define __ASM_ARCH_BRIDGE_REGS_H |
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| 6 | |
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| 7 | #include "dove.h" |
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| 8 | |
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| 9 | #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) |
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| 10 | |
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| 11 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
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| 12 | #define CPU_CTRL_PCIE0_LINK 0x00000001 |
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| 13 | #define CPU_RESET 0x00000002 |
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| 14 | #define CPU_CTRL_PCIE1_LINK 0x00000008 |
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| 15 | |
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| 16 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
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| 17 | #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) |
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| 18 | #define SOFT_RESET_OUT_EN 0x00000004 |
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| 19 | |
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| 20 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
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| 21 | #define SOFT_RESET 0x00000001 |
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| 22 | |
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| 23 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) |
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| 24 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
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| 25 | |
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| 26 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
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| 27 | #define IRQ_CAUSE_LOW_OFF 0x0000 |
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| 28 | #define IRQ_MASK_LOW_OFF 0x0004 |
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| 29 | #define FIQ_MASK_LOW_OFF 0x0008 |
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| 30 | #define ENDPOINT_MASK_LOW_OFF 0x000c |
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| 31 | #define IRQ_CAUSE_HIGH_OFF 0x0010 |
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| 32 | #define IRQ_MASK_HIGH_OFF 0x0014 |
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| 33 | #define FIQ_MASK_HIGH_OFF 0x0018 |
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| 34 | #define ENDPOINT_MASK_HIGH_OFF 0x001c |
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| 35 | #define PCIE_INTERRUPT_MASK_OFF 0x0020 |
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| 36 | |
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| 37 | #define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) |
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| 38 | #define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) |
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| 39 | #define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) |
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| 40 | #define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) |
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| 41 | #define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) |
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| 42 | #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) |
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| 43 | #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) |
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| 44 | |
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| 45 | #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) |
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| 46 | |
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| 47 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
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| 48 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
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| 49 | |
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| 50 | #endif |
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| 51 | |
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