1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * arch/arm/mach-dove/common.c |
4 | * |
5 | * Core functions for Marvell Dove 88AP510 System On Chip |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/dma-mapping.h> |
10 | #include <linux/init.h> |
11 | #include <linux/io.h> |
12 | #include <linux/platform_data/dma-mv_xor.h> |
13 | #include <linux/platform_data/usb-ehci-orion.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/soc/dove/pmu.h> |
16 | #include <asm/hardware/cache-tauros2.h> |
17 | #include <asm/mach/arch.h> |
18 | #include <asm/mach/map.h> |
19 | #include <asm/mach/time.h> |
20 | #include <plat/common.h> |
21 | #include <plat/irq.h> |
22 | #include <plat/time.h> |
23 | #include "bridge-regs.h" |
24 | #include "pm.h" |
25 | #include "common.h" |
26 | |
27 | /* These can go away once Dove uses the mvebu-mbus DT binding */ |
28 | #define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 |
29 | #define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 |
30 | #define DOVE_MBUS_PCIE0_IO_TARGET 0x4 |
31 | #define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 |
32 | #define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 |
33 | #define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 |
34 | #define DOVE_MBUS_PCIE1_IO_TARGET 0x8 |
35 | #define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 |
36 | #define DOVE_MBUS_CESA_TARGET 0x3 |
37 | #define DOVE_MBUS_CESA_ATTR 0x1 |
38 | #define DOVE_MBUS_BOOTROM_TARGET 0x1 |
39 | #define DOVE_MBUS_BOOTROM_ATTR 0xfd |
40 | #define DOVE_MBUS_SCRATCHPAD_TARGET 0xd |
41 | #define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 |
42 | |
43 | /***************************************************************************** |
44 | * I/O Address Mapping |
45 | ****************************************************************************/ |
46 | static struct map_desc __maybe_unused dove_io_desc[] __initdata = { |
47 | { |
48 | .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, |
49 | .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), |
50 | .length = DOVE_SB_REGS_SIZE, |
51 | .type = MT_DEVICE, |
52 | }, { |
53 | .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, |
54 | .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), |
55 | .length = DOVE_NB_REGS_SIZE, |
56 | .type = MT_DEVICE, |
57 | }, |
58 | }; |
59 | |
60 | void __init dove_map_io(void) |
61 | { |
62 | iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); |
63 | } |
64 | |
65 | /***************************************************************************** |
66 | * CLK tree |
67 | ****************************************************************************/ |
68 | static int dove_tclk; |
69 | |
70 | static DEFINE_SPINLOCK(gating_lock); |
71 | static struct clk *tclk; |
72 | |
73 | static struct clk __init *dove_register_gate(const char *name, |
74 | const char *parent, u8 bit_idx) |
75 | { |
76 | return clk_register_gate(NULL, name, parent_name: parent, flags: 0, |
77 | reg: (void __iomem *)CLOCK_GATING_CONTROL, |
78 | bit_idx, clk_gate_flags: 0, lock: &gating_lock); |
79 | } |
80 | |
81 | static void __init dove_clk_init(void) |
82 | { |
83 | struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; |
84 | struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; |
85 | struct clk *xor0, *xor1, *ge, *gephy; |
86 | |
87 | tclk = clk_register_fixed_rate(NULL, name: "tclk" , NULL, flags: 0, fixed_rate: dove_tclk); |
88 | |
89 | usb0 = dove_register_gate(name: "usb0" , parent: "tclk" , CLOCK_GATING_BIT_USB0); |
90 | usb1 = dove_register_gate(name: "usb1" , parent: "tclk" , CLOCK_GATING_BIT_USB1); |
91 | sata = dove_register_gate(name: "sata" , parent: "tclk" , CLOCK_GATING_BIT_SATA); |
92 | pex0 = dove_register_gate(name: "pex0" , parent: "tclk" , CLOCK_GATING_BIT_PCIE0); |
93 | pex1 = dove_register_gate(name: "pex1" , parent: "tclk" , CLOCK_GATING_BIT_PCIE1); |
94 | sdio0 = dove_register_gate(name: "sdio0" , parent: "tclk" , CLOCK_GATING_BIT_SDIO0); |
95 | sdio1 = dove_register_gate(name: "sdio1" , parent: "tclk" , CLOCK_GATING_BIT_SDIO1); |
96 | nand = dove_register_gate(name: "nand" , parent: "tclk" , CLOCK_GATING_BIT_NAND); |
97 | camera = dove_register_gate(name: "camera" , parent: "tclk" , CLOCK_GATING_BIT_CAMERA); |
98 | i2s0 = dove_register_gate(name: "i2s0" , parent: "tclk" , CLOCK_GATING_BIT_I2S0); |
99 | i2s1 = dove_register_gate(name: "i2s1" , parent: "tclk" , CLOCK_GATING_BIT_I2S1); |
100 | crypto = dove_register_gate(name: "crypto" , parent: "tclk" , CLOCK_GATING_BIT_CRYPTO); |
101 | ac97 = dove_register_gate(name: "ac97" , parent: "tclk" , CLOCK_GATING_BIT_AC97); |
102 | pdma = dove_register_gate(name: "pdma" , parent: "tclk" , CLOCK_GATING_BIT_PDMA); |
103 | xor0 = dove_register_gate(name: "xor0" , parent: "tclk" , CLOCK_GATING_BIT_XOR0); |
104 | xor1 = dove_register_gate(name: "xor1" , parent: "tclk" , CLOCK_GATING_BIT_XOR1); |
105 | gephy = dove_register_gate(name: "gephy" , parent: "tclk" , CLOCK_GATING_BIT_GIGA_PHY); |
106 | ge = dove_register_gate(name: "ge" , parent: "gephy" , CLOCK_GATING_BIT_GBE); |
107 | |
108 | orion_clkdev_add(NULL, "orion_spi.0" , tclk); |
109 | orion_clkdev_add(NULL, "orion_spi.1" , tclk); |
110 | orion_clkdev_add(NULL, "orion_wdt" , tclk); |
111 | orion_clkdev_add(NULL, "mv64xxx_i2c.0" , tclk); |
112 | |
113 | orion_clkdev_add(NULL, "orion-ehci.0" , usb0); |
114 | orion_clkdev_add(NULL, "orion-ehci.1" , usb1); |
115 | orion_clkdev_add(NULL, "mv643xx_eth_port.0" , ge); |
116 | orion_clkdev_add(NULL, "sata_mv.0" , sata); |
117 | orion_clkdev_add("0" , "pcie" , pex0); |
118 | orion_clkdev_add("1" , "pcie" , pex1); |
119 | orion_clkdev_add(NULL, "sdhci-dove.0" , sdio0); |
120 | orion_clkdev_add(NULL, "sdhci-dove.1" , sdio1); |
121 | orion_clkdev_add(NULL, "orion_nand" , nand); |
122 | orion_clkdev_add(NULL, "cafe1000-ccic.0" , camera); |
123 | orion_clkdev_add(NULL, "mvebu-audio.0" , i2s0); |
124 | orion_clkdev_add(NULL, "mvebu-audio.1" , i2s1); |
125 | orion_clkdev_add(NULL, "mv_crypto" , crypto); |
126 | orion_clkdev_add(NULL, "dove-ac97" , ac97); |
127 | orion_clkdev_add(NULL, "dove-pdma" , pdma); |
128 | orion_clkdev_add(NULL, MV_XOR_NAME ".0" , xor0); |
129 | orion_clkdev_add(NULL, MV_XOR_NAME ".1" , xor1); |
130 | } |
131 | |
132 | /***************************************************************************** |
133 | * EHCI0 |
134 | ****************************************************************************/ |
135 | void __init dove_ehci0_init(void) |
136 | { |
137 | orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); |
138 | } |
139 | |
140 | /***************************************************************************** |
141 | * EHCI1 |
142 | ****************************************************************************/ |
143 | void __init dove_ehci1_init(void) |
144 | { |
145 | orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); |
146 | } |
147 | |
148 | /***************************************************************************** |
149 | * GE00 |
150 | ****************************************************************************/ |
151 | void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
152 | { |
153 | orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, |
154 | IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, |
155 | 1600); |
156 | } |
157 | |
158 | /***************************************************************************** |
159 | * SoC RTC |
160 | ****************************************************************************/ |
161 | static void __init dove_rtc_init(void) |
162 | { |
163 | orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); |
164 | } |
165 | |
166 | /***************************************************************************** |
167 | * SATA |
168 | ****************************************************************************/ |
169 | void __init dove_sata_init(struct mv_sata_platform_data *sata_data) |
170 | { |
171 | orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); |
172 | |
173 | } |
174 | |
175 | /***************************************************************************** |
176 | * UART0 |
177 | ****************************************************************************/ |
178 | void __init dove_uart0_init(void) |
179 | { |
180 | orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, |
181 | IRQ_DOVE_UART_0, tclk); |
182 | } |
183 | |
184 | /***************************************************************************** |
185 | * UART1 |
186 | ****************************************************************************/ |
187 | void __init dove_uart1_init(void) |
188 | { |
189 | orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, |
190 | IRQ_DOVE_UART_1, tclk); |
191 | } |
192 | |
193 | /***************************************************************************** |
194 | * UART2 |
195 | ****************************************************************************/ |
196 | void __init dove_uart2_init(void) |
197 | { |
198 | orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, |
199 | IRQ_DOVE_UART_2, tclk); |
200 | } |
201 | |
202 | /***************************************************************************** |
203 | * UART3 |
204 | ****************************************************************************/ |
205 | void __init dove_uart3_init(void) |
206 | { |
207 | orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, |
208 | IRQ_DOVE_UART_3, tclk); |
209 | } |
210 | |
211 | /***************************************************************************** |
212 | * SPI |
213 | ****************************************************************************/ |
214 | void __init dove_spi0_init(void) |
215 | { |
216 | orion_spi_init(DOVE_SPI0_PHYS_BASE); |
217 | } |
218 | |
219 | void __init dove_spi1_init(void) |
220 | { |
221 | orion_spi_1_init(DOVE_SPI1_PHYS_BASE); |
222 | } |
223 | |
224 | /***************************************************************************** |
225 | * I2C |
226 | ****************************************************************************/ |
227 | void __init dove_i2c_init(void) |
228 | { |
229 | orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); |
230 | } |
231 | |
232 | /***************************************************************************** |
233 | * Time handling |
234 | ****************************************************************************/ |
235 | void __init dove_init_early(void) |
236 | { |
237 | orion_time_set_base(TIMER_VIRT_BASE); |
238 | mvebu_mbus_init("marvell,dove-mbus" , |
239 | BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, |
240 | DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); |
241 | } |
242 | |
243 | static int __init dove_find_tclk(void) |
244 | { |
245 | return 166666667; |
246 | } |
247 | |
248 | void __init dove_timer_init(void) |
249 | { |
250 | dove_tclk = dove_find_tclk(); |
251 | orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, |
252 | IRQ_DOVE_BRIDGE, dove_tclk); |
253 | } |
254 | |
255 | /***************************************************************************** |
256 | * XOR 0 |
257 | ****************************************************************************/ |
258 | static void __init dove_xor0_init(void) |
259 | { |
260 | orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, |
261 | IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); |
262 | } |
263 | |
264 | /***************************************************************************** |
265 | * XOR 1 |
266 | ****************************************************************************/ |
267 | static void __init dove_xor1_init(void) |
268 | { |
269 | orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, |
270 | IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); |
271 | } |
272 | |
273 | /***************************************************************************** |
274 | * SDIO |
275 | ****************************************************************************/ |
276 | static u64 sdio_dmamask = DMA_BIT_MASK(32); |
277 | |
278 | static struct resource dove_sdio0_resources[] = { |
279 | { |
280 | .start = DOVE_SDIO0_PHYS_BASE, |
281 | .end = DOVE_SDIO0_PHYS_BASE + 0xff, |
282 | .flags = IORESOURCE_MEM, |
283 | }, { |
284 | .start = IRQ_DOVE_SDIO0, |
285 | .end = IRQ_DOVE_SDIO0, |
286 | .flags = IORESOURCE_IRQ, |
287 | }, |
288 | }; |
289 | |
290 | static struct platform_device dove_sdio0 = { |
291 | .name = "sdhci-dove" , |
292 | .id = 0, |
293 | .dev = { |
294 | .dma_mask = &sdio_dmamask, |
295 | .coherent_dma_mask = DMA_BIT_MASK(32), |
296 | }, |
297 | .resource = dove_sdio0_resources, |
298 | .num_resources = ARRAY_SIZE(dove_sdio0_resources), |
299 | }; |
300 | |
301 | void __init dove_sdio0_init(void) |
302 | { |
303 | platform_device_register(&dove_sdio0); |
304 | } |
305 | |
306 | static struct resource dove_sdio1_resources[] = { |
307 | { |
308 | .start = DOVE_SDIO1_PHYS_BASE, |
309 | .end = DOVE_SDIO1_PHYS_BASE + 0xff, |
310 | .flags = IORESOURCE_MEM, |
311 | }, { |
312 | .start = IRQ_DOVE_SDIO1, |
313 | .end = IRQ_DOVE_SDIO1, |
314 | .flags = IORESOURCE_IRQ, |
315 | }, |
316 | }; |
317 | |
318 | static struct platform_device dove_sdio1 = { |
319 | .name = "sdhci-dove" , |
320 | .id = 1, |
321 | .dev = { |
322 | .dma_mask = &sdio_dmamask, |
323 | .coherent_dma_mask = DMA_BIT_MASK(32), |
324 | }, |
325 | .resource = dove_sdio1_resources, |
326 | .num_resources = ARRAY_SIZE(dove_sdio1_resources), |
327 | }; |
328 | |
329 | void __init dove_sdio1_init(void) |
330 | { |
331 | platform_device_register(&dove_sdio1); |
332 | } |
333 | |
334 | void __init dove_setup_cpu_wins(void) |
335 | { |
336 | /* |
337 | * The PCIe windows will no longer be statically allocated |
338 | * here once Dove is migrated to the pci-mvebu driver. The |
339 | * non-PCIe windows will no longer be created here once Dove |
340 | * fully moves to DT. |
341 | */ |
342 | mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, |
343 | DOVE_MBUS_PCIE0_IO_ATTR, |
344 | DOVE_PCIE0_IO_PHYS_BASE, |
345 | DOVE_PCIE0_IO_SIZE, |
346 | DOVE_PCIE0_IO_BUS_BASE); |
347 | mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, |
348 | DOVE_MBUS_PCIE1_IO_ATTR, |
349 | DOVE_PCIE1_IO_PHYS_BASE, |
350 | DOVE_PCIE1_IO_SIZE, |
351 | DOVE_PCIE1_IO_BUS_BASE); |
352 | mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, |
353 | DOVE_MBUS_PCIE0_MEM_ATTR, |
354 | DOVE_PCIE0_MEM_PHYS_BASE, |
355 | DOVE_PCIE0_MEM_SIZE); |
356 | mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, |
357 | DOVE_MBUS_PCIE1_MEM_ATTR, |
358 | DOVE_PCIE1_MEM_PHYS_BASE, |
359 | DOVE_PCIE1_MEM_SIZE); |
360 | mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, |
361 | DOVE_MBUS_CESA_ATTR, |
362 | DOVE_CESA_PHYS_BASE, |
363 | DOVE_CESA_SIZE); |
364 | mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, |
365 | DOVE_MBUS_BOOTROM_ATTR, |
366 | DOVE_BOOTROM_PHYS_BASE, |
367 | DOVE_BOOTROM_SIZE); |
368 | mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, |
369 | DOVE_MBUS_SCRATCHPAD_ATTR, |
370 | DOVE_SCRATCHPAD_PHYS_BASE, |
371 | DOVE_SCRATCHPAD_SIZE); |
372 | } |
373 | |
374 | static struct resource orion_wdt_resource[] = { |
375 | DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), |
376 | DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), |
377 | }; |
378 | |
379 | static struct platform_device orion_wdt_device = { |
380 | .name = "orion_wdt" , |
381 | .id = -1, |
382 | .num_resources = ARRAY_SIZE(orion_wdt_resource), |
383 | .resource = orion_wdt_resource, |
384 | }; |
385 | |
386 | static void __init __maybe_unused orion_wdt_init(void) |
387 | { |
388 | platform_device_register(&orion_wdt_device); |
389 | } |
390 | |
391 | static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = { |
392 | { |
393 | .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK, |
394 | .rst_mask = PMU_SW_RST_VIDEO_MASK, |
395 | .iso_mask = PMU_ISO_VIDEO_MASK, |
396 | .name = "vpu-domain" , |
397 | }, { |
398 | .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, |
399 | .rst_mask = PMU_SW_RST_GPU_MASK, |
400 | .iso_mask = PMU_ISO_GPU_MASK, |
401 | .name = "gpu-domain" , |
402 | }, { |
403 | /* sentinel */ |
404 | }, |
405 | }; |
406 | |
407 | static const struct dove_pmu_initdata pmu_data __initconst = { |
408 | .pmc_base = DOVE_PMU_VIRT_BASE, |
409 | .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000, |
410 | .irq = IRQ_DOVE_PMU, |
411 | .irq_domain_start = IRQ_DOVE_PMU_START, |
412 | .domains = pmu_domains, |
413 | }; |
414 | |
415 | void __init dove_init(void) |
416 | { |
417 | pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n" , |
418 | (dove_tclk + 499999) / 1000000); |
419 | |
420 | #ifdef CONFIG_CACHE_TAUROS2 |
421 | tauros2_init(0); |
422 | #endif |
423 | dove_setup_cpu_wins(); |
424 | |
425 | /* Setup root of clk tree */ |
426 | dove_clk_init(); |
427 | |
428 | /* internal devices that every board has */ |
429 | dove_init_pmu_legacy(&pmu_data); |
430 | dove_rtc_init(); |
431 | dove_xor0_init(); |
432 | dove_xor1_init(); |
433 | } |
434 | |
435 | void dove_restart(enum reboot_mode mode, const char *cmd) |
436 | { |
437 | /* |
438 | * Enable soft reset to assert RSTOUTn. |
439 | */ |
440 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); |
441 | |
442 | /* |
443 | * Assert soft reset. |
444 | */ |
445 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); |
446 | |
447 | while (1) |
448 | ; |
449 | } |
450 | |