1 | /* |
2 | * linux/arch/arm/mach-omap1/pm.c |
3 | * |
4 | * OMAP Power Management Routines |
5 | * |
6 | * Original code for the SA11x0: |
7 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> |
8 | * |
9 | * Modified for the PXA250 by Nicolas Pitre: |
10 | * Copyright (c) 2002 Monta Vista Software, Inc. |
11 | * |
12 | * Modified for the OMAP1510 by David Singleton: |
13 | * Copyright (c) 2002 Monta Vista Software, Inc. |
14 | * |
15 | * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com> |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify it |
18 | * under the terms of the GNU General Public License as published by the |
19 | * Free Software Foundation; either version 2 of the License, or (at your |
20 | * option) any later version. |
21 | * |
22 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
25 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
32 | * |
33 | * You should have received a copy of the GNU General Public License along |
34 | * with this program; if not, write to the Free Software Foundation, Inc., |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
36 | */ |
37 | |
38 | #include <linux/suspend.h> |
39 | #include <linux/sched.h> |
40 | #include <linux/debugfs.h> |
41 | #include <linux/seq_file.h> |
42 | #include <linux/interrupt.h> |
43 | #include <linux/sysfs.h> |
44 | #include <linux/module.h> |
45 | #include <linux/io.h> |
46 | #include <linux/atomic.h> |
47 | #include <linux/cpu.h> |
48 | |
49 | #include <asm/fncpy.h> |
50 | #include <asm/system_misc.h> |
51 | #include <asm/irq.h> |
52 | #include <asm/mach/time.h> |
53 | #include <asm/mach/irq.h> |
54 | |
55 | #include <linux/soc/ti/omap1-io.h> |
56 | #include "tc.h" |
57 | #include <linux/omap-dma.h> |
58 | #include <clocksource/timer-ti-dm.h> |
59 | |
60 | #include "hardware.h" |
61 | #include "mux.h" |
62 | #include "irqs.h" |
63 | #include "iomap.h" |
64 | #include "clock.h" |
65 | #include "pm.h" |
66 | #include "soc.h" |
67 | #include "sram.h" |
68 | |
69 | static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; |
70 | static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; |
71 | static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; |
72 | static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; |
73 | static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; |
74 | |
75 | static unsigned short enable_dyn_sleep; |
76 | |
77 | static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, |
78 | char *buf) |
79 | { |
80 | return sprintf(buf, fmt: "%hu\n" , enable_dyn_sleep); |
81 | } |
82 | |
83 | static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, |
84 | const char * buf, size_t n) |
85 | { |
86 | unsigned short value; |
87 | if (sscanf(buf, "%hu" , &value) != 1 || |
88 | (value != 0 && value != 1) || |
89 | (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) { |
90 | pr_err("idle_sleep_store: Invalid value\n" ); |
91 | return -EINVAL; |
92 | } |
93 | enable_dyn_sleep = value; |
94 | return n; |
95 | } |
96 | |
97 | static struct kobj_attribute sleep_while_idle_attr = |
98 | __ATTR(sleep_while_idle, 0644, idle_show, idle_store); |
99 | |
100 | |
101 | static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; |
102 | |
103 | /* |
104 | * Let's power down on idle, but only if we are really |
105 | * idle, because once we start down the path of |
106 | * going idle we continue to do idle even if we get |
107 | * a clock tick interrupt . . |
108 | */ |
109 | void omap1_pm_idle(void) |
110 | { |
111 | extern __u32 arm_idlect1_mask; |
112 | __u32 use_idlect1 = arm_idlect1_mask; |
113 | |
114 | local_fiq_disable(); |
115 | |
116 | #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER) |
117 | use_idlect1 = use_idlect1 & ~(1 << 9); |
118 | #endif |
119 | |
120 | #ifdef CONFIG_OMAP_DM_TIMER |
121 | use_idlect1 = omap_dm_timer_modify_idlect_mask(inputmask: use_idlect1); |
122 | #endif |
123 | |
124 | if (omap_dma_running()) |
125 | use_idlect1 &= ~(1 << 6); |
126 | |
127 | /* |
128 | * We should be able to remove the do_sleep variable and multiple |
129 | * tests above as soon as drivers, timer and DMA code have been fixed. |
130 | * Even the sleep block count should become obsolete. |
131 | */ |
132 | if ((use_idlect1 != ~0) || !enable_dyn_sleep) { |
133 | |
134 | __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); |
135 | if (cpu_is_omap15xx()) |
136 | use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; |
137 | else |
138 | use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; |
139 | omap_writel(v: use_idlect1, ARM_IDLECT1); |
140 | __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4" ); |
141 | omap_writel(v: saved_idlect1, ARM_IDLECT1); |
142 | |
143 | local_fiq_enable(); |
144 | return; |
145 | } |
146 | omap_sram_suspend(omap_readl(ARM_IDLECT1), |
147 | omap_readl(ARM_IDLECT2)); |
148 | |
149 | local_fiq_enable(); |
150 | } |
151 | |
152 | /* |
153 | * Configuration of the wakeup event is board specific. For the |
154 | * moment we put it into this helper function. Later it may move |
155 | * to board specific files. |
156 | */ |
157 | static void omap_pm_wakeup_setup(void) |
158 | { |
159 | u32 level1_wake = 0; |
160 | u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); |
161 | |
162 | /* |
163 | * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, |
164 | * and the L2 wakeup interrupts: keypad and UART2. Note that the |
165 | * drivers must still separately call omap_set_gpio_wakeup() to |
166 | * wake up to a GPIO interrupt. |
167 | */ |
168 | if (cpu_is_omap15xx()) |
169 | level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | |
170 | OMAP_IRQ_BIT(INT_1510_IH2_IRQ); |
171 | else if (cpu_is_omap16xx()) |
172 | level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | |
173 | OMAP_IRQ_BIT(INT_1610_IH2_IRQ); |
174 | |
175 | omap_writel(v: ~level1_wake, pa: OMAP_IH1_MIR); |
176 | |
177 | if (cpu_is_omap15xx()) { |
178 | level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); |
179 | omap_writel(v: ~level2_wake, pa: OMAP_IH2_MIR); |
180 | } else if (cpu_is_omap16xx()) { |
181 | level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); |
182 | omap_writel(v: ~level2_wake, pa: OMAP_IH2_0_MIR); |
183 | |
184 | /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ |
185 | omap_writel(v: ~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), |
186 | pa: OMAP_IH2_1_MIR); |
187 | omap_writel(v: ~0x0, pa: OMAP_IH2_2_MIR); |
188 | omap_writel(v: ~0x0, pa: OMAP_IH2_3_MIR); |
189 | } |
190 | |
191 | /* New IRQ agreement, recalculate in cascade order */ |
192 | omap_writel(v: 1, pa: OMAP_IH2_CONTROL); |
193 | omap_writel(v: 1, pa: OMAP_IH1_CONTROL); |
194 | } |
195 | |
196 | #define EN_DSPCK 13 /* ARM_CKCTL */ |
197 | #define EN_APICK 6 /* ARM_IDLECT2 */ |
198 | #define DSP_EN 1 /* ARM_RSTCT1 */ |
199 | |
200 | void omap1_pm_suspend(void) |
201 | { |
202 | unsigned long arg0 = 0, arg1 = 0; |
203 | |
204 | printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n" , |
205 | omap_rev()); |
206 | |
207 | omap_serial_wake_trigger(1); |
208 | |
209 | if (!cpu_is_omap15xx()) |
210 | omap_writew(v: 0xffff, ULPD_SOFT_DISABLE_REQ_REG); |
211 | |
212 | /* |
213 | * Step 1: turn off interrupts (FIXME: NOTE: already disabled) |
214 | */ |
215 | |
216 | local_irq_disable(); |
217 | local_fiq_disable(); |
218 | |
219 | /* |
220 | * Step 2: save registers |
221 | * |
222 | * The omap is a strange/beautiful device. The caches, memory |
223 | * and register state are preserved across power saves. |
224 | * We have to save and restore very little register state to |
225 | * idle the omap. |
226 | * |
227 | * Save interrupt, MPUI, ARM and UPLD control registers. |
228 | */ |
229 | |
230 | if (cpu_is_omap15xx()) { |
231 | MPUI1510_SAVE(OMAP_IH1_MIR); |
232 | MPUI1510_SAVE(OMAP_IH2_MIR); |
233 | MPUI1510_SAVE(MPUI_CTRL); |
234 | MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); |
235 | MPUI1510_SAVE(MPUI_DSP_API_CONFIG); |
236 | MPUI1510_SAVE(EMIFS_CONFIG); |
237 | MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); |
238 | } else if (cpu_is_omap16xx()) { |
239 | MPUI1610_SAVE(OMAP_IH1_MIR); |
240 | MPUI1610_SAVE(OMAP_IH2_0_MIR); |
241 | MPUI1610_SAVE(OMAP_IH2_1_MIR); |
242 | MPUI1610_SAVE(OMAP_IH2_2_MIR); |
243 | MPUI1610_SAVE(OMAP_IH2_3_MIR); |
244 | MPUI1610_SAVE(MPUI_CTRL); |
245 | MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); |
246 | MPUI1610_SAVE(MPUI_DSP_API_CONFIG); |
247 | MPUI1610_SAVE(EMIFS_CONFIG); |
248 | MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); |
249 | } |
250 | |
251 | ARM_SAVE(ARM_CKCTL); |
252 | ARM_SAVE(ARM_IDLECT1); |
253 | ARM_SAVE(ARM_IDLECT2); |
254 | if (!(cpu_is_omap15xx())) |
255 | ARM_SAVE(ARM_IDLECT3); |
256 | ARM_SAVE(ARM_EWUPCT); |
257 | ARM_SAVE(ARM_RSTCT1); |
258 | ARM_SAVE(ARM_RSTCT2); |
259 | ARM_SAVE(ARM_SYSST); |
260 | ULPD_SAVE(ULPD_CLOCK_CTRL); |
261 | ULPD_SAVE(ULPD_STATUS_REQ); |
262 | |
263 | /* (Step 3 removed - we now allow deep sleep by default) */ |
264 | |
265 | /* |
266 | * Step 4: OMAP DSP Shutdown |
267 | */ |
268 | |
269 | /* stop DSP */ |
270 | omap_writew(v: omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); |
271 | |
272 | /* shut down dsp_ck */ |
273 | omap_writew(v: omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); |
274 | |
275 | /* temporarily enabling api_ck to access DSP registers */ |
276 | omap_writew(v: omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); |
277 | |
278 | /* save DSP registers */ |
279 | DSP_SAVE(DSP_IDLECT2); |
280 | |
281 | /* Stop all DSP domain clocks */ |
282 | __raw_writew(val: 0, DSP_IDLECT2); |
283 | |
284 | /* |
285 | * Step 5: Wakeup Event Setup |
286 | */ |
287 | |
288 | omap_pm_wakeup_setup(); |
289 | |
290 | /* |
291 | * Step 6: ARM and Traffic controller shutdown |
292 | */ |
293 | |
294 | /* disable ARM watchdog */ |
295 | omap_writel(v: 0x00F5, OMAP_WDT_TIMER_MODE); |
296 | omap_writel(v: 0x00A0, OMAP_WDT_TIMER_MODE); |
297 | |
298 | /* |
299 | * Step 6b: ARM and Traffic controller shutdown |
300 | * |
301 | * Step 6 continues here. Prepare jump to power management |
302 | * assembly code in internal SRAM. |
303 | * |
304 | * Since the omap_cpu_suspend routine has been copied to |
305 | * SRAM, we'll do an indirect procedure call to it and pass the |
306 | * contents of arm_idlect1 and arm_idlect2 so it can restore |
307 | * them when it wakes up and it will return. |
308 | */ |
309 | |
310 | arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; |
311 | arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; |
312 | |
313 | /* |
314 | * Step 6c: ARM and Traffic controller shutdown |
315 | * |
316 | * Jump to assembly code. The processor will stay there |
317 | * until wake up. |
318 | */ |
319 | omap_sram_suspend(arg0, arg1); |
320 | |
321 | /* |
322 | * If we are here, processor is woken up! |
323 | */ |
324 | |
325 | /* |
326 | * Restore DSP clocks |
327 | */ |
328 | |
329 | /* again temporarily enabling api_ck to access DSP registers */ |
330 | omap_writew(v: omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); |
331 | |
332 | /* Restore DSP domain clocks */ |
333 | DSP_RESTORE(DSP_IDLECT2); |
334 | |
335 | /* |
336 | * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did |
337 | */ |
338 | |
339 | if (!(cpu_is_omap15xx())) |
340 | ARM_RESTORE(ARM_IDLECT3); |
341 | ARM_RESTORE(ARM_CKCTL); |
342 | ARM_RESTORE(ARM_EWUPCT); |
343 | ARM_RESTORE(ARM_RSTCT1); |
344 | ARM_RESTORE(ARM_RSTCT2); |
345 | ARM_RESTORE(ARM_SYSST); |
346 | ULPD_RESTORE(ULPD_CLOCK_CTRL); |
347 | ULPD_RESTORE(ULPD_STATUS_REQ); |
348 | |
349 | if (cpu_is_omap15xx()) { |
350 | MPUI1510_RESTORE(MPUI_CTRL); |
351 | MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); |
352 | MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); |
353 | MPUI1510_RESTORE(EMIFS_CONFIG); |
354 | MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); |
355 | MPUI1510_RESTORE(OMAP_IH1_MIR); |
356 | MPUI1510_RESTORE(OMAP_IH2_MIR); |
357 | } else if (cpu_is_omap16xx()) { |
358 | MPUI1610_RESTORE(MPUI_CTRL); |
359 | MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); |
360 | MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); |
361 | MPUI1610_RESTORE(EMIFS_CONFIG); |
362 | MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); |
363 | |
364 | MPUI1610_RESTORE(OMAP_IH1_MIR); |
365 | MPUI1610_RESTORE(OMAP_IH2_0_MIR); |
366 | MPUI1610_RESTORE(OMAP_IH2_1_MIR); |
367 | MPUI1610_RESTORE(OMAP_IH2_2_MIR); |
368 | MPUI1610_RESTORE(OMAP_IH2_3_MIR); |
369 | } |
370 | |
371 | if (!cpu_is_omap15xx()) |
372 | omap_writew(v: 0, ULPD_SOFT_DISABLE_REQ_REG); |
373 | |
374 | /* |
375 | * Re-enable interrupts |
376 | */ |
377 | |
378 | local_irq_enable(); |
379 | local_fiq_enable(); |
380 | |
381 | omap_serial_wake_trigger(0); |
382 | |
383 | printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n" , |
384 | omap_rev()); |
385 | } |
386 | |
387 | #ifdef CONFIG_DEBUG_FS |
388 | /* |
389 | * Read system PM registers for debugging |
390 | */ |
391 | static int omap_pm_debug_show(struct seq_file *m, void *v) |
392 | { |
393 | ARM_SAVE(ARM_CKCTL); |
394 | ARM_SAVE(ARM_IDLECT1); |
395 | ARM_SAVE(ARM_IDLECT2); |
396 | if (!(cpu_is_omap15xx())) |
397 | ARM_SAVE(ARM_IDLECT3); |
398 | ARM_SAVE(ARM_EWUPCT); |
399 | ARM_SAVE(ARM_RSTCT1); |
400 | ARM_SAVE(ARM_RSTCT2); |
401 | ARM_SAVE(ARM_SYSST); |
402 | |
403 | ULPD_SAVE(ULPD_IT_STATUS); |
404 | ULPD_SAVE(ULPD_CLOCK_CTRL); |
405 | ULPD_SAVE(ULPD_SOFT_REQ); |
406 | ULPD_SAVE(ULPD_STATUS_REQ); |
407 | ULPD_SAVE(ULPD_DPLL_CTRL); |
408 | ULPD_SAVE(ULPD_POWER_CTRL); |
409 | |
410 | if (cpu_is_omap15xx()) { |
411 | MPUI1510_SAVE(MPUI_CTRL); |
412 | MPUI1510_SAVE(MPUI_DSP_STATUS); |
413 | MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); |
414 | MPUI1510_SAVE(MPUI_DSP_API_CONFIG); |
415 | MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); |
416 | MPUI1510_SAVE(EMIFS_CONFIG); |
417 | } else if (cpu_is_omap16xx()) { |
418 | MPUI1610_SAVE(MPUI_CTRL); |
419 | MPUI1610_SAVE(MPUI_DSP_STATUS); |
420 | MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); |
421 | MPUI1610_SAVE(MPUI_DSP_API_CONFIG); |
422 | MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); |
423 | MPUI1610_SAVE(EMIFS_CONFIG); |
424 | } |
425 | |
426 | seq_printf(m, |
427 | fmt: "ARM_CKCTL_REG: 0x%-8x \n" |
428 | "ARM_IDLECT1_REG: 0x%-8x \n" |
429 | "ARM_IDLECT2_REG: 0x%-8x \n" |
430 | "ARM_IDLECT3_REG: 0x%-8x \n" |
431 | "ARM_EWUPCT_REG: 0x%-8x \n" |
432 | "ARM_RSTCT1_REG: 0x%-8x \n" |
433 | "ARM_RSTCT2_REG: 0x%-8x \n" |
434 | "ARM_SYSST_REG: 0x%-8x \n" |
435 | "ULPD_IT_STATUS_REG: 0x%-4x \n" |
436 | "ULPD_CLOCK_CTRL_REG: 0x%-4x \n" |
437 | "ULPD_SOFT_REQ_REG: 0x%-4x \n" |
438 | "ULPD_DPLL_CTRL_REG: 0x%-4x \n" |
439 | "ULPD_STATUS_REQ_REG: 0x%-4x \n" |
440 | "ULPD_POWER_CTRL_REG: 0x%-4x \n" , |
441 | ARM_SHOW(ARM_CKCTL), |
442 | ARM_SHOW(ARM_IDLECT1), |
443 | ARM_SHOW(ARM_IDLECT2), |
444 | ARM_SHOW(ARM_IDLECT3), |
445 | ARM_SHOW(ARM_EWUPCT), |
446 | ARM_SHOW(ARM_RSTCT1), |
447 | ARM_SHOW(ARM_RSTCT2), |
448 | ARM_SHOW(ARM_SYSST), |
449 | ULPD_SHOW(ULPD_IT_STATUS), |
450 | ULPD_SHOW(ULPD_CLOCK_CTRL), |
451 | ULPD_SHOW(ULPD_SOFT_REQ), |
452 | ULPD_SHOW(ULPD_DPLL_CTRL), |
453 | ULPD_SHOW(ULPD_STATUS_REQ), |
454 | ULPD_SHOW(ULPD_POWER_CTRL)); |
455 | |
456 | if (cpu_is_omap15xx()) { |
457 | seq_printf(m, |
458 | fmt: "MPUI1510_CTRL_REG 0x%-8x \n" |
459 | "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" |
460 | "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" |
461 | "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" |
462 | "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" |
463 | "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n" , |
464 | MPUI1510_SHOW(MPUI_CTRL), |
465 | MPUI1510_SHOW(MPUI_DSP_STATUS), |
466 | MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), |
467 | MPUI1510_SHOW(MPUI_DSP_API_CONFIG), |
468 | MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), |
469 | MPUI1510_SHOW(EMIFS_CONFIG)); |
470 | } else if (cpu_is_omap16xx()) { |
471 | seq_printf(m, |
472 | fmt: "MPUI1610_CTRL_REG 0x%-8x \n" |
473 | "MPUI1610_DSP_STATUS_REG: 0x%-8x \n" |
474 | "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" |
475 | "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" |
476 | "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" |
477 | "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n" , |
478 | MPUI1610_SHOW(MPUI_CTRL), |
479 | MPUI1610_SHOW(MPUI_DSP_STATUS), |
480 | MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), |
481 | MPUI1610_SHOW(MPUI_DSP_API_CONFIG), |
482 | MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), |
483 | MPUI1610_SHOW(EMIFS_CONFIG)); |
484 | } |
485 | |
486 | return 0; |
487 | } |
488 | |
489 | DEFINE_SHOW_ATTRIBUTE(omap_pm_debug); |
490 | |
491 | static void omap_pm_init_debugfs(void) |
492 | { |
493 | struct dentry *d; |
494 | |
495 | d = debugfs_create_dir(name: "pm_debug" , NULL); |
496 | debugfs_create_file(name: "omap_pm" , S_IWUSR | S_IRUGO, parent: d, NULL, |
497 | fops: &omap_pm_debug_fops); |
498 | } |
499 | |
500 | #endif /* CONFIG_DEBUG_FS */ |
501 | |
502 | /* |
503 | * omap_pm_prepare - Do preliminary suspend work. |
504 | * |
505 | */ |
506 | static int omap_pm_prepare(void) |
507 | { |
508 | /* We cannot sleep in idle until we have resumed */ |
509 | cpu_idle_poll_ctrl(enable: true); |
510 | return 0; |
511 | } |
512 | |
513 | |
514 | /* |
515 | * omap_pm_enter - Actually enter a sleep state. |
516 | * @state: State we're entering. |
517 | * |
518 | */ |
519 | |
520 | static int omap_pm_enter(suspend_state_t state) |
521 | { |
522 | switch (state) |
523 | { |
524 | case PM_SUSPEND_MEM: |
525 | omap1_pm_suspend(); |
526 | break; |
527 | default: |
528 | return -EINVAL; |
529 | } |
530 | |
531 | return 0; |
532 | } |
533 | |
534 | |
535 | /** |
536 | * omap_pm_finish - Finish up suspend sequence. |
537 | * |
538 | * This is called after we wake back up (or if entering the sleep state |
539 | * failed). |
540 | */ |
541 | |
542 | static void omap_pm_finish(void) |
543 | { |
544 | cpu_idle_poll_ctrl(enable: false); |
545 | } |
546 | |
547 | |
548 | static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) |
549 | { |
550 | return IRQ_HANDLED; |
551 | } |
552 | |
553 | |
554 | |
555 | static const struct platform_suspend_ops omap_pm_ops = { |
556 | .prepare = omap_pm_prepare, |
557 | .enter = omap_pm_enter, |
558 | .finish = omap_pm_finish, |
559 | .valid = suspend_valid_only_mem, |
560 | }; |
561 | |
562 | static int __init omap_pm_init(void) |
563 | { |
564 | int error = 0; |
565 | int irq; |
566 | |
567 | if (!cpu_class_is_omap1()) |
568 | return -ENODEV; |
569 | |
570 | pr_info("Power Management for TI OMAP.\n" ); |
571 | |
572 | if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER)) |
573 | pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n" ); |
574 | |
575 | if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER)) |
576 | pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n" ); |
577 | |
578 | if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) && |
579 | IS_ENABLED(CONFIG_OMAP_DM_TIMER)) { |
580 | /* OMAP16xx only */ |
581 | pr_info("OMAP1 PM: sleep states in idle enabled\n" ); |
582 | enable_dyn_sleep = 1; |
583 | } |
584 | |
585 | /* |
586 | * We copy the assembler sleep/wakeup routines to SRAM. |
587 | * These routines need to be in SRAM as that's the only |
588 | * memory the MPU can see when it wakes up. |
589 | */ |
590 | if (cpu_is_omap15xx()) { |
591 | omap_sram_suspend = omap_sram_push(funcp: omap1510_cpu_suspend, |
592 | size: omap1510_cpu_suspend_sz); |
593 | } else if (cpu_is_omap16xx()) { |
594 | omap_sram_suspend = omap_sram_push(funcp: omap1610_cpu_suspend, |
595 | size: omap1610_cpu_suspend_sz); |
596 | } |
597 | |
598 | if (omap_sram_suspend == NULL) { |
599 | printk(KERN_ERR "PM not initialized: Missing SRAM support\n" ); |
600 | return -ENODEV; |
601 | } |
602 | |
603 | arm_pm_idle = omap1_pm_idle; |
604 | |
605 | if (cpu_is_omap16xx()) |
606 | irq = INT_1610_WAKE_UP_REQ; |
607 | else |
608 | irq = -1; |
609 | |
610 | if (irq >= 0) { |
611 | if (request_irq(irq, handler: omap_wakeup_interrupt, flags: 0, name: "peripheral wakeup" , NULL)) |
612 | pr_err("Failed to request irq %d (peripheral wakeup)\n" , irq); |
613 | } |
614 | |
615 | /* Program new power ramp-up time |
616 | * (0 for most boards since we don't lower voltage when in deep sleep) |
617 | */ |
618 | omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); |
619 | |
620 | /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ |
621 | omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); |
622 | |
623 | /* Configure IDLECT3 */ |
624 | if (cpu_is_omap16xx()) |
625 | omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); |
626 | |
627 | suspend_set_ops(ops: &omap_pm_ops); |
628 | |
629 | #ifdef CONFIG_DEBUG_FS |
630 | omap_pm_init_debugfs(); |
631 | #endif |
632 | |
633 | error = sysfs_create_file(kobj: power_kobj, attr: &sleep_while_idle_attr.attr); |
634 | if (error) |
635 | pr_err("sysfs_create_file failed: %d\n" , error); |
636 | |
637 | if (cpu_is_omap16xx()) { |
638 | /* configure LOW_PWR pin */ |
639 | omap_cfg_reg(reg_cfg: T20_1610_LOW_PWR); |
640 | } |
641 | |
642 | return error; |
643 | } |
644 | __initcall(omap_pm_init); |
645 | |