1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Static Memory Controller |
4 | */ |
5 | |
6 | #include <linux/module.h> |
7 | #include <linux/kernel.h> |
8 | #include <linux/init.h> |
9 | #include <linux/io.h> |
10 | #include <linux/syscore_ops.h> |
11 | #include <linux/soc/pxa/cpu.h> |
12 | |
13 | #include "smemc.h" |
14 | #include <linux/soc/pxa/smemc.h> |
15 | |
16 | #ifdef CONFIG_PM |
17 | static unsigned long msc[2]; |
18 | static unsigned long sxcnfg, memclkcfg; |
19 | static unsigned long csadrcfg[4]; |
20 | |
21 | static int pxa3xx_smemc_suspend(void) |
22 | { |
23 | msc[0] = __raw_readl(MSC0); |
24 | msc[1] = __raw_readl(MSC1); |
25 | sxcnfg = __raw_readl(SXCNFG); |
26 | memclkcfg = __raw_readl(MEMCLKCFG); |
27 | csadrcfg[0] = __raw_readl(CSADRCFG0); |
28 | csadrcfg[1] = __raw_readl(CSADRCFG1); |
29 | csadrcfg[2] = __raw_readl(CSADRCFG2); |
30 | csadrcfg[3] = __raw_readl(CSADRCFG3); |
31 | |
32 | return 0; |
33 | } |
34 | |
35 | static void pxa3xx_smemc_resume(void) |
36 | { |
37 | __raw_writel(val: msc[0], MSC0); |
38 | __raw_writel(val: msc[1], MSC1); |
39 | __raw_writel(val: sxcnfg, SXCNFG); |
40 | __raw_writel(val: memclkcfg, MEMCLKCFG); |
41 | __raw_writel(val: csadrcfg[0], CSADRCFG0); |
42 | __raw_writel(val: csadrcfg[1], CSADRCFG1); |
43 | __raw_writel(val: csadrcfg[2], CSADRCFG2); |
44 | __raw_writel(val: csadrcfg[3], CSADRCFG3); |
45 | /* CSMSADRCFG wakes up in its default state (0), so we need to set it */ |
46 | __raw_writel(val: 0x2, CSMSADRCFG); |
47 | } |
48 | |
49 | static struct syscore_ops smemc_syscore_ops = { |
50 | .suspend = pxa3xx_smemc_suspend, |
51 | .resume = pxa3xx_smemc_resume, |
52 | }; |
53 | |
54 | static int __init smemc_init(void) |
55 | { |
56 | if (cpu_is_pxa3xx()) { |
57 | /* |
58 | * The only documentation we have on the |
59 | * Chip Select Configuration Register (CSMSADRCFG) is that |
60 | * it must be programmed to 0x2. |
61 | * Moreover, in the bit definitions, the second bit |
62 | * (CSMSADRCFG[1]) is called "SETALWAYS". |
63 | * Other bits are reserved in this register. |
64 | */ |
65 | __raw_writel(val: 0x2, CSMSADRCFG); |
66 | |
67 | register_syscore_ops(ops: &smemc_syscore_ops); |
68 | } |
69 | |
70 | return 0; |
71 | } |
72 | subsys_initcall(smemc_init); |
73 | #endif |
74 | |
75 | static const unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; |
76 | unsigned int pxa3xx_smemc_get_memclkdiv(void) |
77 | { |
78 | unsigned long memclkcfg = __raw_readl(MEMCLKCFG); |
79 | |
80 | return df_clkdiv[(memclkcfg >> 16) & 0x3]; |
81 | } |
82 | |