| 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | /* |
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| 3 | * R8A7740 processor support |
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| 4 | * |
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| 5 | * Copyright (C) 2011 Renesas Solutions Corp. |
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| 6 | * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
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| 7 | */ |
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| 8 | #include <linux/kernel.h> |
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| 9 | #include <linux/init.h> |
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| 10 | #include <linux/io.h> |
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| 11 | #include <linux/irqchip.h> |
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| 12 | #include <linux/irqchip/arm-gic.h> |
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| 13 | |
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| 14 | #include <asm/mach/map.h> |
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| 15 | #include <asm/mach/arch.h> |
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| 16 | #include <asm/mach/time.h> |
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| 17 | |
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| 18 | #include "common.h" |
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| 19 | |
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| 20 | /* |
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| 21 | * r8a7740 chip has lasting errata on MERAM buffer. |
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| 22 | * this is work-around for it. |
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| 23 | * see |
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| 24 | * "Media RAM (MERAM)" on r8a7740 documentation |
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| 25 | */ |
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| 26 | #define MEBUFCNTR 0xFE950098 |
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| 27 | static void __init r8a7740_meram_workaround(void) |
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| 28 | { |
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| 29 | void __iomem *reg; |
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| 30 | |
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| 31 | reg = ioremap(MEBUFCNTR, size: 4); |
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| 32 | if (reg) { |
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| 33 | iowrite32(0x01600164, reg); |
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| 34 | iounmap(addr: reg); |
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| 35 | } |
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| 36 | } |
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| 37 | |
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| 38 | static void __init r8a7740_init_irq_of(void) |
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| 39 | { |
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| 40 | void __iomem *intc_prio_base = ioremap(offset: 0xe6900010, size: 0x10); |
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| 41 | void __iomem *intc_msk_base = ioremap(offset: 0xe6900040, size: 0x10); |
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| 42 | void __iomem *pfc_inta_ctrl = ioremap(offset: 0xe605807c, size: 0x4); |
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| 43 | |
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| 44 | irqchip_init(); |
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| 45 | |
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| 46 | /* route signals to GIC */ |
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| 47 | iowrite32(0x0, pfc_inta_ctrl); |
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| 48 | |
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| 49 | /* |
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| 50 | * To mask the shared interrupt to SPI 149 we must ensure to set |
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| 51 | * PRIO *and* MASK. Else we run into IRQ floods when registering |
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| 52 | * the intc_irqpin devices |
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| 53 | */ |
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| 54 | iowrite32(0x0, intc_prio_base + 0x0); |
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| 55 | iowrite32(0x0, intc_prio_base + 0x4); |
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| 56 | iowrite32(0x0, intc_prio_base + 0x8); |
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| 57 | iowrite32(0x0, intc_prio_base + 0xc); |
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| 58 | iowrite8(0xff, intc_msk_base + 0x0); |
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| 59 | iowrite8(0xff, intc_msk_base + 0x4); |
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| 60 | iowrite8(0xff, intc_msk_base + 0x8); |
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| 61 | iowrite8(0xff, intc_msk_base + 0xc); |
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| 62 | |
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| 63 | iounmap(addr: intc_prio_base); |
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| 64 | iounmap(addr: intc_msk_base); |
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| 65 | iounmap(addr: pfc_inta_ctrl); |
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| 66 | } |
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| 67 | |
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| 68 | static void __init r8a7740_generic_init(void) |
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| 69 | { |
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| 70 | r8a7740_meram_workaround(); |
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| 71 | } |
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| 72 | |
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| 73 | static const char *const r8a7740_boards_compat_dt[] __initconst = { |
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| 74 | "renesas,r8a7740" , |
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| 75 | NULL |
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| 76 | }; |
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| 77 | |
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| 78 | DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)" ) |
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| 79 | .l2c_aux_val = 0, |
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| 80 | .l2c_aux_mask = ~0, |
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| 81 | .init_early = shmobile_init_delay, |
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| 82 | .init_irq = r8a7740_init_irq_of, |
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| 83 | .init_machine = r8a7740_generic_init, |
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| 84 | .init_late = shmobile_init_late, |
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| 85 | .dt_compat = r8a7740_boards_compat_dt, |
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| 86 | MACHINE_END |
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| 87 | |
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