1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * r8a7778 processor support |
4 | * |
5 | * Copyright (C) 2013 Renesas Solutions Corp. |
6 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
7 | * Copyright (C) 2013 Cogent Embedded, Inc. |
8 | */ |
9 | |
10 | #include <linux/io.h> |
11 | #include <linux/irqchip.h> |
12 | |
13 | #include <asm/mach/arch.h> |
14 | |
15 | #include "common.h" |
16 | |
17 | #define HPBREG_BASE 0xfe700000 |
18 | |
19 | #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ |
20 | #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ |
21 | |
22 | #define INT2NTSR0 0x00018 /* 0xfe700018 */ |
23 | #define INT2NTSR1 0x0002c /* 0xfe70002c */ |
24 | |
25 | static void __init r8a7778_init_irq_dt(void) |
26 | { |
27 | void __iomem *base = ioremap(HPBREG_BASE, size: 0x00100000); |
28 | |
29 | BUG_ON(!base); |
30 | |
31 | irqchip_init(); |
32 | |
33 | /* route all interrupts to ARM */ |
34 | writel(val: 0x73ffffff, addr: base + INT2NTSR0); |
35 | writel(val: 0xffffffff, addr: base + INT2NTSR1); |
36 | |
37 | /* unmask all known interrupts in INTCS2 */ |
38 | writel(val: 0x08330773, addr: base + INT2SMSKCR0); |
39 | writel(val: 0x00311110, addr: base + INT2SMSKCR1); |
40 | |
41 | iounmap(addr: base); |
42 | } |
43 | |
44 | static const char *const r8a7778_compat_dt[] __initconst = { |
45 | "renesas,r8a7778" , |
46 | NULL |
47 | }; |
48 | |
49 | DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)" ) |
50 | .init_early = shmobile_init_delay, |
51 | .init_irq = r8a7778_init_irq_dt, |
52 | .init_late = shmobile_init_late, |
53 | .dt_compat = r8a7778_compat_dt, |
54 | MACHINE_END |
55 | |