1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * m5441x.c -- support for Coldfire m5441x processors |
4 | * |
5 | * (C) Copyright Steven King <sfking@fdwdc.com> |
6 | */ |
7 | |
8 | #include <linux/clkdev.h> |
9 | #include <linux/kernel.h> |
10 | #include <linux/param.h> |
11 | #include <linux/init.h> |
12 | #include <linux/io.h> |
13 | #include <linux/clk.h> |
14 | #include <asm/machdep.h> |
15 | #include <asm/coldfire.h> |
16 | #include <asm/mcfsim.h> |
17 | #include <asm/mcfuart.h> |
18 | #include <asm/mcfdma.h> |
19 | #include <asm/mcfclk.h> |
20 | |
21 | DEFINE_CLK(0, "flexbus" , 2, MCF_CLK); |
22 | DEFINE_CLK(0, "flexcan.0" , 8, MCF_CLK); |
23 | DEFINE_CLK(0, "flexcan.1" , 9, MCF_CLK); |
24 | DEFINE_CLK(0, "imx1-i2c.1" , 14, MCF_CLK); |
25 | DEFINE_CLK(0, "mcfdspi.1" , 15, MCF_CLK); |
26 | DEFINE_CLK(0, "edma" , 17, MCF_CLK); |
27 | DEFINE_CLK(0, "intc.0" , 18, MCF_CLK); |
28 | DEFINE_CLK(0, "intc.1" , 19, MCF_CLK); |
29 | DEFINE_CLK(0, "intc.2" , 20, MCF_CLK); |
30 | DEFINE_CLK(0, "imx1-i2c.0" , 22, MCF_CLK); |
31 | DEFINE_CLK(0, "fsl-dspi.0" , 23, MCF_CLK); |
32 | DEFINE_CLK(0, "mcfuart.0" , 24, MCF_BUSCLK); |
33 | DEFINE_CLK(0, "mcfuart.1" , 25, MCF_BUSCLK); |
34 | DEFINE_CLK(0, "mcfuart.2" , 26, MCF_BUSCLK); |
35 | DEFINE_CLK(0, "mcfuart.3" , 27, MCF_BUSCLK); |
36 | DEFINE_CLK(0, "mcftmr.0" , 28, MCF_CLK); |
37 | DEFINE_CLK(0, "mcftmr.1" , 29, MCF_CLK); |
38 | DEFINE_CLK(0, "mcftmr.2" , 30, MCF_CLK); |
39 | DEFINE_CLK(0, "mcftmr.3" , 31, MCF_CLK); |
40 | DEFINE_CLK(0, "mcfpit.0" , 32, MCF_CLK); |
41 | DEFINE_CLK(0, "mcfpit.1" , 33, MCF_CLK); |
42 | DEFINE_CLK(0, "mcfpit.2" , 34, MCF_CLK); |
43 | DEFINE_CLK(0, "mcfpit.3" , 35, MCF_CLK); |
44 | DEFINE_CLK(0, "mcfeport.0" , 37, MCF_CLK); |
45 | DEFINE_CLK(0, "mcfadc.0" , 38, MCF_CLK); |
46 | DEFINE_CLK(0, "mcfdac.0" , 39, MCF_CLK); |
47 | DEFINE_CLK(0, "mcfrtc.0" , 42, MCF_CLK); |
48 | DEFINE_CLK(0, "mcfsim.0" , 43, MCF_CLK); |
49 | DEFINE_CLK(0, "mcfusb-otg.0" , 44, MCF_CLK); |
50 | DEFINE_CLK(0, "mcfusb-host.0" , 45, MCF_CLK); |
51 | DEFINE_CLK(0, "mcfddr-sram.0" , 46, MCF_CLK); |
52 | DEFINE_CLK(0, "mcfssi.0" , 47, MCF_CLK); |
53 | DEFINE_CLK(0, "pll.0" , 48, MCF_CLK); |
54 | DEFINE_CLK(0, "mcfrng.0" , 49, MCF_CLK); |
55 | DEFINE_CLK(0, "mcfssi.1" , 50, MCF_CLK); |
56 | DEFINE_CLK(0, "sdhci-esdhc-mcf.0" , 51, MCF_CLK); |
57 | DEFINE_CLK(0, "enet-fec.0" , 53, MCF_CLK); |
58 | DEFINE_CLK(0, "enet-fec.1" , 54, MCF_CLK); |
59 | DEFINE_CLK(0, "switch.0" , 55, MCF_CLK); |
60 | DEFINE_CLK(0, "switch.1" , 56, MCF_CLK); |
61 | DEFINE_CLK(0, "nand.0" , 63, MCF_CLK); |
62 | |
63 | DEFINE_CLK(1, "mcfow.0" , 2, MCF_CLK); |
64 | DEFINE_CLK(1, "imx1-i2c.2" , 4, MCF_CLK); |
65 | DEFINE_CLK(1, "imx1-i2c.3" , 5, MCF_CLK); |
66 | DEFINE_CLK(1, "imx1-i2c.4" , 6, MCF_CLK); |
67 | DEFINE_CLK(1, "imx1-i2c.5" , 7, MCF_CLK); |
68 | DEFINE_CLK(1, "mcfuart.4" , 24, MCF_BUSCLK); |
69 | DEFINE_CLK(1, "mcfuart.5" , 25, MCF_BUSCLK); |
70 | DEFINE_CLK(1, "mcfuart.6" , 26, MCF_BUSCLK); |
71 | DEFINE_CLK(1, "mcfuart.7" , 27, MCF_BUSCLK); |
72 | DEFINE_CLK(1, "mcfuart.8" , 28, MCF_BUSCLK); |
73 | DEFINE_CLK(1, "mcfuart.9" , 29, MCF_BUSCLK); |
74 | DEFINE_CLK(1, "mcfpwm.0" , 34, MCF_BUSCLK); |
75 | DEFINE_CLK(1, "sys.0" , 36, MCF_BUSCLK); |
76 | DEFINE_CLK(1, "gpio.0" , 37, MCF_BUSCLK); |
77 | |
78 | DEFINE_CLK(2, "ipg.0" , 0, MCF_CLK); |
79 | DEFINE_CLK(2, "ahb.0" , 1, MCF_CLK); |
80 | DEFINE_CLK(2, "per.0" , 2, MCF_CLK); |
81 | |
82 | static struct clk_lookup m5411x_clk_lookup[] = { |
83 | CLKDEV_INIT("flexbus" , NULL, &__clk_0_2), |
84 | CLKDEV_INIT("mcfcan.0" , NULL, &__clk_0_8), |
85 | CLKDEV_INIT("mcfcan.1" , NULL, &__clk_0_9), |
86 | CLKDEV_INIT("imx1-i2c.1" , NULL, &__clk_0_14), |
87 | CLKDEV_INIT("mcfdspi.1" , NULL, &__clk_0_15), |
88 | CLKDEV_INIT("edma" , NULL, &__clk_0_17), |
89 | CLKDEV_INIT("intc.0" , NULL, &__clk_0_18), |
90 | CLKDEV_INIT("intc.1" , NULL, &__clk_0_19), |
91 | CLKDEV_INIT("intc.2" , NULL, &__clk_0_20), |
92 | CLKDEV_INIT("imx1-i2c.0" , NULL, &__clk_0_22), |
93 | CLKDEV_INIT("fsl-dspi.0" , NULL, &__clk_0_23), |
94 | CLKDEV_INIT("mcfuart.0" , NULL, &__clk_0_24), |
95 | CLKDEV_INIT("mcfuart.1" , NULL, &__clk_0_25), |
96 | CLKDEV_INIT("mcfuart.2" , NULL, &__clk_0_26), |
97 | CLKDEV_INIT("mcfuart.3" , NULL, &__clk_0_27), |
98 | CLKDEV_INIT("mcftmr.0" , NULL, &__clk_0_28), |
99 | CLKDEV_INIT("mcftmr.1" , NULL, &__clk_0_29), |
100 | CLKDEV_INIT("mcftmr.2" , NULL, &__clk_0_30), |
101 | CLKDEV_INIT("mcftmr.3" , NULL, &__clk_0_31), |
102 | CLKDEV_INIT("mcfpit.0" , NULL, &__clk_0_32), |
103 | CLKDEV_INIT("mcfpit.1" , NULL, &__clk_0_33), |
104 | CLKDEV_INIT("mcfpit.2" , NULL, &__clk_0_34), |
105 | CLKDEV_INIT("mcfpit.3" , NULL, &__clk_0_35), |
106 | CLKDEV_INIT("mcfeport.0" , NULL, &__clk_0_37), |
107 | CLKDEV_INIT("mcfadc.0" , NULL, &__clk_0_38), |
108 | CLKDEV_INIT("mcfdac.0" , NULL, &__clk_0_39), |
109 | CLKDEV_INIT("mcfrtc.0" , NULL, &__clk_0_42), |
110 | CLKDEV_INIT("mcfsim.0" , NULL, &__clk_0_43), |
111 | CLKDEV_INIT("mcfusb-otg.0" , NULL, &__clk_0_44), |
112 | CLKDEV_INIT("mcfusb-host.0" , NULL, &__clk_0_45), |
113 | CLKDEV_INIT("mcfddr-sram.0" , NULL, &__clk_0_46), |
114 | CLKDEV_INIT("mcfssi.0" , NULL, &__clk_0_47), |
115 | CLKDEV_INIT(NULL, "pll.0" , &__clk_0_48), |
116 | CLKDEV_INIT("mcfrng.0" , NULL, &__clk_0_49), |
117 | CLKDEV_INIT("mcfssi.1" , NULL, &__clk_0_50), |
118 | CLKDEV_INIT("sdhci-esdhc-mcf.0" , NULL, &__clk_0_51), |
119 | CLKDEV_INIT("enet-fec.0" , NULL, &__clk_0_53), |
120 | CLKDEV_INIT("enet-fec.1" , NULL, &__clk_0_54), |
121 | CLKDEV_INIT("switch.0" , NULL, &__clk_0_55), |
122 | CLKDEV_INIT("switch.1" , NULL, &__clk_0_56), |
123 | CLKDEV_INIT("nand.0" , NULL, &__clk_0_63), |
124 | CLKDEV_INIT("mcfow.0" , NULL, &__clk_1_2), |
125 | CLKDEV_INIT("imx1-i2c.2" , NULL, &__clk_1_4), |
126 | CLKDEV_INIT("imx1-i2c.3" , NULL, &__clk_1_5), |
127 | CLKDEV_INIT("imx1-i2c.4" , NULL, &__clk_1_6), |
128 | CLKDEV_INIT("imx1-i2c.5" , NULL, &__clk_1_7), |
129 | CLKDEV_INIT("mcfuart.4" , NULL, &__clk_1_24), |
130 | CLKDEV_INIT("mcfuart.5" , NULL, &__clk_1_25), |
131 | CLKDEV_INIT("mcfuart.6" , NULL, &__clk_1_26), |
132 | CLKDEV_INIT("mcfuart.7" , NULL, &__clk_1_27), |
133 | CLKDEV_INIT("mcfuart.8" , NULL, &__clk_1_28), |
134 | CLKDEV_INIT("mcfuart.9" , NULL, &__clk_1_29), |
135 | CLKDEV_INIT("mcfpwm.0" , NULL, &__clk_1_34), |
136 | CLKDEV_INIT(NULL, "sys.0" , &__clk_1_36), |
137 | CLKDEV_INIT("gpio.0" , NULL, &__clk_1_37), |
138 | CLKDEV_INIT("ipg.0" , NULL, &__clk_2_0), |
139 | CLKDEV_INIT("ahb.0" , NULL, &__clk_2_1), |
140 | CLKDEV_INIT("per.0" , NULL, &__clk_2_2), |
141 | }; |
142 | |
143 | static struct clk * const enable_clks[] __initconst = { |
144 | /* make sure these clocks are enabled */ |
145 | &__clk_0_8, /* flexcan.0 */ |
146 | &__clk_0_9, /* flexcan.1 */ |
147 | &__clk_0_15, /* dspi.1 */ |
148 | &__clk_0_17, /* eDMA */ |
149 | &__clk_0_18, /* intc0 */ |
150 | &__clk_0_19, /* intc0 */ |
151 | &__clk_0_20, /* intc0 */ |
152 | &__clk_0_23, /* dspi.0 */ |
153 | &__clk_0_24, /* uart0 */ |
154 | &__clk_0_25, /* uart1 */ |
155 | &__clk_0_26, /* uart2 */ |
156 | &__clk_0_27, /* uart3 */ |
157 | |
158 | &__clk_0_33, /* pit.1 */ |
159 | &__clk_0_37, /* eport */ |
160 | &__clk_0_48, /* pll */ |
161 | &__clk_0_51, /* esdhc */ |
162 | |
163 | &__clk_1_36, /* CCM/reset module/Power management */ |
164 | &__clk_1_37, /* gpio */ |
165 | }; |
166 | static struct clk * const disable_clks[] __initconst = { |
167 | &__clk_0_14, /* i2c.1 */ |
168 | &__clk_0_22, /* i2c.0 */ |
169 | &__clk_0_23, /* dspi.0 */ |
170 | &__clk_0_28, /* tmr.1 */ |
171 | &__clk_0_29, /* tmr.2 */ |
172 | &__clk_0_30, /* tmr.2 */ |
173 | &__clk_0_31, /* tmr.3 */ |
174 | &__clk_0_32, /* pit.0 */ |
175 | &__clk_0_34, /* pit.2 */ |
176 | &__clk_0_35, /* pit.3 */ |
177 | &__clk_0_38, /* adc */ |
178 | &__clk_0_39, /* dac */ |
179 | &__clk_0_44, /* usb otg */ |
180 | &__clk_0_45, /* usb host */ |
181 | &__clk_0_47, /* ssi.0 */ |
182 | &__clk_0_49, /* rng */ |
183 | &__clk_0_50, /* ssi.1 */ |
184 | &__clk_0_53, /* enet-fec */ |
185 | &__clk_0_54, /* enet-fec */ |
186 | &__clk_0_55, /* switch.0 */ |
187 | &__clk_0_56, /* switch.1 */ |
188 | |
189 | &__clk_1_2, /* 1-wire */ |
190 | &__clk_1_4, /* i2c.2 */ |
191 | &__clk_1_5, /* i2c.3 */ |
192 | &__clk_1_6, /* i2c.4 */ |
193 | &__clk_1_7, /* i2c.5 */ |
194 | &__clk_1_24, /* uart 4 */ |
195 | &__clk_1_25, /* uart 5 */ |
196 | &__clk_1_26, /* uart 6 */ |
197 | &__clk_1_27, /* uart 7 */ |
198 | &__clk_1_28, /* uart 8 */ |
199 | &__clk_1_29, /* uart 9 */ |
200 | }; |
201 | |
202 | static void __clk_enable2(struct clk *clk) |
203 | { |
204 | __raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK); |
205 | } |
206 | |
207 | static void __clk_disable2(struct clk *clk) |
208 | { |
209 | __raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK); |
210 | } |
211 | |
212 | struct clk_ops clk_ops2 = { |
213 | .enable = __clk_enable2, |
214 | .disable = __clk_disable2, |
215 | }; |
216 | |
217 | static void __init m5441x_clk_init(void) |
218 | { |
219 | unsigned i; |
220 | |
221 | for (i = 0; i < ARRAY_SIZE(enable_clks); ++i) |
222 | __clk_init_enabled(enable_clks[i]); |
223 | /* make sure these clocks are disabled */ |
224 | for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) |
225 | __clk_init_disabled(disable_clks[i]); |
226 | |
227 | clkdev_add_table(m5411x_clk_lookup, ARRAY_SIZE(m5411x_clk_lookup)); |
228 | } |
229 | |
230 | static void __init m5441x_uarts_init(void) |
231 | { |
232 | __raw_writeb(0x0f, MCFGPIO_PAR_UART0); |
233 | __raw_writeb(0x00, MCFGPIO_PAR_UART1); |
234 | __raw_writeb(0x00, MCFGPIO_PAR_UART2); |
235 | } |
236 | |
237 | static void __init m5441x_fec_init(void) |
238 | { |
239 | __raw_writeb(0x03, MCFGPIO_PAR_FEC); |
240 | } |
241 | |
242 | void __init config_BSP(char *commandp, int size) |
243 | { |
244 | m5441x_clk_init(); |
245 | mach_sched_init = hw_timer_init; |
246 | m5441x_uarts_init(); |
247 | m5441x_fec_init(); |
248 | } |
249 | |