1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de> |
4 | * Thanks to : |
5 | * Dale Farnsworth <dale@farnsworth.org> |
6 | * Mark A. Greer <mgreer@mvista.com> |
7 | * Nicolas DET <nd@bplan-gmbh.de> |
8 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> |
9 | * And anyone else who helped me on this. |
10 | */ |
11 | |
12 | #include <linux/types.h> |
13 | #include <linux/init.h> |
14 | #include <linux/ioport.h> |
15 | #include <linux/device.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/mv643xx.h> |
18 | #include <linux/pci.h> |
19 | |
20 | #define PEGASOS2_MARVELL_REGBASE (0xf1000000) |
21 | #define PEGASOS2_MARVELL_REGSIZE (0x00004000) |
22 | #define PEGASOS2_SRAM_BASE (0xf2000000) |
23 | #define PEGASOS2_SRAM_SIZE (256*1024) |
24 | |
25 | #define PEGASOS2_SRAM_BASE_ETH_PORT0 (PEGASOS2_SRAM_BASE) |
26 | #define PEGASOS2_SRAM_BASE_ETH_PORT1 (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) ) |
27 | |
28 | |
29 | #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) |
30 | #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4) |
31 | |
32 | #undef BE_VERBOSE |
33 | |
34 | static struct resource mv643xx_eth_shared_resources[] = { |
35 | [0] = { |
36 | .name = "ethernet shared base" , |
37 | .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS, |
38 | .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + |
39 | MV643XX_ETH_SHARED_REGS_SIZE - 1, |
40 | .flags = IORESOURCE_MEM, |
41 | }, |
42 | }; |
43 | |
44 | static struct platform_device mv643xx_eth_shared_device = { |
45 | .name = MV643XX_ETH_SHARED_NAME, |
46 | .id = 0, |
47 | .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources), |
48 | .resource = mv643xx_eth_shared_resources, |
49 | }; |
50 | |
51 | /* |
52 | * The orion mdio driver only covers shared + 0x4 up to shared + 0x84 - 1 |
53 | */ |
54 | static struct resource mv643xx_eth_mvmdio_resources[] = { |
55 | [0] = { |
56 | .name = "ethernet mdio base" , |
57 | .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x4, |
58 | .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 0x83, |
59 | .flags = IORESOURCE_MEM, |
60 | }, |
61 | }; |
62 | |
63 | static struct platform_device mv643xx_eth_mvmdio_device = { |
64 | .name = "orion-mdio" , |
65 | .id = -1, |
66 | .num_resources = ARRAY_SIZE(mv643xx_eth_mvmdio_resources), |
67 | .resource = mv643xx_eth_mvmdio_resources, |
68 | }; |
69 | |
70 | static struct resource mv643xx_eth_port1_resources[] = { |
71 | [0] = { |
72 | .name = "eth port1 irq" , |
73 | .start = 9, |
74 | .end = 9, |
75 | .flags = IORESOURCE_IRQ, |
76 | }, |
77 | }; |
78 | |
79 | static struct mv643xx_eth_platform_data eth_port1_pd = { |
80 | .shared = &mv643xx_eth_shared_device, |
81 | .port_number = 1, |
82 | .phy_addr = MV643XX_ETH_PHY_ADDR(7), |
83 | |
84 | .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1, |
85 | .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, |
86 | .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, |
87 | |
88 | .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE, |
89 | .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, |
90 | .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, |
91 | }; |
92 | |
93 | static struct platform_device eth_port1_device = { |
94 | .name = MV643XX_ETH_NAME, |
95 | .id = 1, |
96 | .num_resources = ARRAY_SIZE(mv643xx_eth_port1_resources), |
97 | .resource = mv643xx_eth_port1_resources, |
98 | .dev = { |
99 | .platform_data = ð_port1_pd, |
100 | }, |
101 | }; |
102 | |
103 | static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { |
104 | &mv643xx_eth_shared_device, |
105 | &mv643xx_eth_mvmdio_device, |
106 | ð_port1_device, |
107 | }; |
108 | |
109 | /***********/ |
110 | /***********/ |
111 | #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } |
112 | #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset) |
113 | |
114 | static void __iomem *mv643xx_reg_base; |
115 | |
116 | static int __init Enable_SRAM(void) |
117 | { |
118 | u32 ALong; |
119 | |
120 | if (mv643xx_reg_base == NULL) |
121 | mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, |
122 | PEGASOS2_MARVELL_REGSIZE); |
123 | |
124 | if (mv643xx_reg_base == NULL) |
125 | return -ENOMEM; |
126 | |
127 | #ifdef BE_VERBOSE |
128 | printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n" , |
129 | (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base); |
130 | #endif |
131 | |
132 | MV_WRITE(MV64340_SRAM_CONFIG, 0); |
133 | |
134 | MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16); |
135 | |
136 | MV_READ(MV64340_BASE_ADDR_ENABLE, ALong); |
137 | ALong &= ~(1 << 19); |
138 | MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong); |
139 | |
140 | ALong = 0x02; |
141 | ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; |
142 | MV_WRITE(MV643XX_ETH_BAR_4, ALong); |
143 | |
144 | MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000); |
145 | |
146 | MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); |
147 | ALong &= ~(1 << 4); |
148 | MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); |
149 | |
150 | #ifdef BE_VERBOSE |
151 | printk("Pegasos II/Marvell MV64361: register unmapped\n" ); |
152 | printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n" , (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE); |
153 | #endif |
154 | |
155 | iounmap(addr: mv643xx_reg_base); |
156 | mv643xx_reg_base = NULL; |
157 | |
158 | return 1; |
159 | } |
160 | |
161 | |
162 | /***********/ |
163 | /***********/ |
164 | static int __init mv643xx_eth_add_pds(void) |
165 | { |
166 | int ret = 0; |
167 | static struct pci_device_id pci_marvell_mv64360[] = { |
168 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) }, |
169 | { } |
170 | }; |
171 | |
172 | #ifdef BE_VERBOSE |
173 | printk("Pegasos II/Marvell MV64361: init\n" ); |
174 | #endif |
175 | |
176 | if (pci_dev_present(ids: pci_marvell_mv64360)) { |
177 | ret = platform_add_devices(mv643xx_eth_pd_devs, |
178 | ARRAY_SIZE(mv643xx_eth_pd_devs)); |
179 | |
180 | if ( Enable_SRAM() < 0) |
181 | { |
182 | eth_port1_pd.tx_sram_addr = 0; |
183 | eth_port1_pd.tx_sram_size = 0; |
184 | eth_port1_pd.rx_sram_addr = 0; |
185 | eth_port1_pd.rx_sram_size = 0; |
186 | |
187 | #ifdef BE_VERBOSE |
188 | printk("Pegasos II/Marvell MV64361: Can't enable the " |
189 | "SRAM\n" ); |
190 | #endif |
191 | } |
192 | } |
193 | |
194 | #ifdef BE_VERBOSE |
195 | printk("Pegasos II/Marvell MV64361: init is over\n" ); |
196 | #endif |
197 | |
198 | return ret; |
199 | } |
200 | |
201 | device_initcall(mv643xx_eth_add_pds); |
202 | |