1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* pci_impl.h: Helper definitions for PCI controller support. |
3 | * |
4 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
5 | */ |
6 | |
7 | #ifndef PCI_IMPL_H |
8 | #define PCI_IMPL_H |
9 | |
10 | #include <linux/types.h> |
11 | #include <linux/spinlock.h> |
12 | #include <linux/pci.h> |
13 | #include <linux/msi.h> |
14 | #include <asm/io.h> |
15 | #include <asm/prom.h> |
16 | #include <asm/iommu.h> |
17 | |
18 | /* The abstraction used here is that there are PCI controllers, |
19 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules |
20 | * underneath. Each PCI bus module uses an IOMMU (shared by both |
21 | * PBMs of a controller, or per-PBM), and if a streaming buffer |
22 | * is present, each PCI bus module has its own. (ie. the IOMMU |
23 | * might be shared between PBMs, the STC is never shared) |
24 | * Furthermore, each PCI bus module controls its own autonomous |
25 | * PCI bus. |
26 | */ |
27 | |
28 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ |
29 | (*((STC)->strbuf_flushflag) = 0UL) |
30 | #define PCI_STC_FLUSHFLAG_SET(STC) \ |
31 | (*((STC)->strbuf_flushflag) != 0UL) |
32 | |
33 | #ifdef CONFIG_PCI_MSI |
34 | struct pci_pbm_info; |
35 | struct sparc64_msiq_ops { |
36 | int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid, |
37 | unsigned long *head); |
38 | int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid, |
39 | unsigned long *head, unsigned long *msi); |
40 | int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid, |
41 | unsigned long head); |
42 | int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid, |
43 | unsigned long msi, int is_msi64); |
44 | int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi); |
45 | int (*msiq_alloc)(struct pci_pbm_info *pbm); |
46 | void (*msiq_free)(struct pci_pbm_info *pbm); |
47 | int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid, |
48 | unsigned long devino); |
49 | }; |
50 | |
51 | void sparc64_pbm_msi_init(struct pci_pbm_info *pbm, |
52 | const struct sparc64_msiq_ops *ops); |
53 | |
54 | struct sparc64_msiq_cookie { |
55 | struct pci_pbm_info *pbm; |
56 | unsigned long msiqid; |
57 | }; |
58 | #endif |
59 | |
60 | struct pci_pbm_info { |
61 | struct pci_pbm_info *next; |
62 | struct pci_pbm_info *sibling; |
63 | int index; |
64 | |
65 | /* Physical address base of controller registers. */ |
66 | unsigned long controller_regs; |
67 | |
68 | /* Physical address base of PBM registers. */ |
69 | unsigned long pbm_regs; |
70 | |
71 | /* Physical address of DMA sync register, if any. */ |
72 | unsigned long sync_reg; |
73 | |
74 | /* Opaque 32-bit system bus Port ID. */ |
75 | u32 portid; |
76 | |
77 | /* Opaque 32-bit handle used for hypervisor calls. */ |
78 | u32 devhandle; |
79 | |
80 | /* Chipset version information. */ |
81 | int chip_type; |
82 | #define PBM_CHIP_TYPE_SABRE 1 |
83 | #define PBM_CHIP_TYPE_PSYCHO 2 |
84 | #define PBM_CHIP_TYPE_SCHIZO 3 |
85 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 |
86 | #define PBM_CHIP_TYPE_TOMATILLO 5 |
87 | int chip_version; |
88 | int chip_revision; |
89 | |
90 | /* Name used for top-level resources. */ |
91 | const char *name; |
92 | |
93 | /* OBP specific information. */ |
94 | struct platform_device *op; |
95 | u64 ino_bitmap; |
96 | |
97 | /* PBM I/O and Memory space resources. */ |
98 | struct resource io_space; |
99 | struct resource mem_space; |
100 | struct resource mem64_space; |
101 | struct resource busn; |
102 | /* offset */ |
103 | resource_size_t io_offset; |
104 | resource_size_t mem_offset; |
105 | resource_size_t mem64_offset; |
106 | |
107 | /* Base of PCI Config space, can be per-PBM or shared. */ |
108 | unsigned long config_space; |
109 | |
110 | /* This will be 12 on PCI-E controllers, 8 elsewhere. */ |
111 | unsigned long config_space_reg_bits; |
112 | |
113 | unsigned long pci_afsr; |
114 | unsigned long pci_afar; |
115 | unsigned long pci_csr; |
116 | |
117 | /* State of 66MHz capabilities on this PBM. */ |
118 | int is_66mhz_capable; |
119 | int all_devs_66mhz; |
120 | |
121 | #ifdef CONFIG_PCI_MSI |
122 | /* MSI info. */ |
123 | u32 msiq_num; |
124 | u32 msiq_ent_count; |
125 | u32 msiq_first; |
126 | u32 msiq_first_devino; |
127 | u32 msiq_rotor; |
128 | struct sparc64_msiq_cookie *msiq_irq_cookies; |
129 | u32 msi_num; |
130 | u32 msi_first; |
131 | u32 msi_data_mask; |
132 | u32 msix_data_width; |
133 | u64 msi32_start; |
134 | u64 msi64_start; |
135 | u32 msi32_len; |
136 | u32 msi64_len; |
137 | void *msi_queues; |
138 | unsigned long *msi_bitmap; |
139 | unsigned int *msi_irq_table; |
140 | int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev, |
141 | struct msi_desc *entry); |
142 | void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev); |
143 | const struct sparc64_msiq_ops *msi_ops; |
144 | #endif /* !(CONFIG_PCI_MSI) */ |
145 | |
146 | /* This PBM's streaming buffer. */ |
147 | struct strbuf stc; |
148 | |
149 | /* IOMMU state, potentially shared by both PBM segments. */ |
150 | struct iommu *iommu; |
151 | |
152 | /* Now things for the actual PCI bus probes. */ |
153 | unsigned int pci_first_busno; |
154 | unsigned int pci_last_busno; |
155 | struct pci_bus *pci_bus; |
156 | struct pci_ops *pci_ops; |
157 | |
158 | int numa_node; |
159 | }; |
160 | |
161 | extern struct pci_pbm_info *pci_pbm_root; |
162 | |
163 | extern int pci_num_pbms; |
164 | |
165 | /* PCI bus scanning and fixup support. */ |
166 | void pci_get_pbm_props(struct pci_pbm_info *pbm); |
167 | struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm, |
168 | struct device *parent); |
169 | void pci_determine_mem_io_space(struct pci_pbm_info *pbm); |
170 | |
171 | /* Error reporting support. */ |
172 | void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *); |
173 | void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *); |
174 | void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *); |
175 | |
176 | /* Configuration space access. */ |
177 | void pci_config_read8(u8 *addr, u8 *ret); |
178 | void pci_config_read16(u16 *addr, u16 *ret); |
179 | void pci_config_read32(u32 *addr, u32 *ret); |
180 | void pci_config_write8(u8 *addr, u8 val); |
181 | void pci_config_write16(u16 *addr, u16 val); |
182 | void pci_config_write32(u32 *addr, u32 val); |
183 | |
184 | extern struct pci_ops sun4u_pci_ops; |
185 | extern struct pci_ops sun4v_pci_ops; |
186 | |
187 | extern volatile int pci_poke_in_progress; |
188 | extern volatile int pci_poke_cpu; |
189 | extern volatile int pci_poke_faulted; |
190 | |
191 | #endif /* !(PCI_IMPL_H) */ |
192 | |