1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* pci_sabre.c: Sabre specific PCI controller support. |
3 | * |
4 | * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) |
5 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
6 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) |
7 | */ |
8 | |
9 | #include <linux/kernel.h> |
10 | #include <linux/types.h> |
11 | #include <linux/pci.h> |
12 | #include <linux/init.h> |
13 | #include <linux/export.h> |
14 | #include <linux/slab.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_platform.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/property.h> |
20 | |
21 | #include <asm/apb.h> |
22 | #include <asm/iommu.h> |
23 | #include <asm/irq.h> |
24 | #include <asm/prom.h> |
25 | #include <asm/upa.h> |
26 | |
27 | #include "pci_impl.h" |
28 | #include "iommu_common.h" |
29 | #include "psycho_common.h" |
30 | |
31 | #define DRIVER_NAME "sabre" |
32 | #define PFX DRIVER_NAME ": " |
33 | |
34 | /* SABRE PCI controller register offsets and definitions. */ |
35 | #define SABRE_UE_AFSR 0x0030UL |
36 | #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ |
37 | #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ |
38 | #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ |
39 | #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ |
40 | #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ |
41 | #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ |
42 | #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ |
43 | #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ |
44 | #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */ |
45 | #define SABRE_UECE_AFAR 0x0038UL |
46 | #define SABRE_CE_AFSR 0x0040UL |
47 | #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ |
48 | #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ |
49 | #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ |
50 | #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ |
51 | #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */ |
52 | #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ |
53 | #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */ |
54 | #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */ |
55 | #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */ |
56 | #define SABRE_IOMMU_CONTROL 0x0200UL |
57 | #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */ |
58 | #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */ |
59 | #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */ |
60 | #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */ |
61 | #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
62 | #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000 |
63 | #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000 |
64 | #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000 |
65 | #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000 |
66 | #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000 |
67 | #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000 |
68 | #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000 |
69 | #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000 |
70 | #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */ |
71 | #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
72 | #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
73 | #define SABRE_IOMMU_TSBBASE 0x0208UL |
74 | #define SABRE_IOMMU_FLUSH 0x0210UL |
75 | #define SABRE_IMAP_A_SLOT0 0x0c00UL |
76 | #define SABRE_IMAP_B_SLOT0 0x0c20UL |
77 | #define SABRE_IMAP_SCSI 0x1000UL |
78 | #define SABRE_IMAP_ETH 0x1008UL |
79 | #define SABRE_IMAP_BPP 0x1010UL |
80 | #define SABRE_IMAP_AU_REC 0x1018UL |
81 | #define SABRE_IMAP_AU_PLAY 0x1020UL |
82 | #define SABRE_IMAP_PFAIL 0x1028UL |
83 | #define SABRE_IMAP_KMS 0x1030UL |
84 | #define SABRE_IMAP_FLPY 0x1038UL |
85 | #define SABRE_IMAP_SHW 0x1040UL |
86 | #define SABRE_IMAP_KBD 0x1048UL |
87 | #define SABRE_IMAP_MS 0x1050UL |
88 | #define SABRE_IMAP_SER 0x1058UL |
89 | #define SABRE_IMAP_UE 0x1070UL |
90 | #define SABRE_IMAP_CE 0x1078UL |
91 | #define SABRE_IMAP_PCIERR 0x1080UL |
92 | #define SABRE_IMAP_GFX 0x1098UL |
93 | #define SABRE_IMAP_EUPA 0x10a0UL |
94 | #define SABRE_ICLR_A_SLOT0 0x1400UL |
95 | #define SABRE_ICLR_B_SLOT0 0x1480UL |
96 | #define SABRE_ICLR_SCSI 0x1800UL |
97 | #define SABRE_ICLR_ETH 0x1808UL |
98 | #define SABRE_ICLR_BPP 0x1810UL |
99 | #define SABRE_ICLR_AU_REC 0x1818UL |
100 | #define SABRE_ICLR_AU_PLAY 0x1820UL |
101 | #define SABRE_ICLR_PFAIL 0x1828UL |
102 | #define SABRE_ICLR_KMS 0x1830UL |
103 | #define SABRE_ICLR_FLPY 0x1838UL |
104 | #define SABRE_ICLR_SHW 0x1840UL |
105 | #define SABRE_ICLR_KBD 0x1848UL |
106 | #define SABRE_ICLR_MS 0x1850UL |
107 | #define SABRE_ICLR_SER 0x1858UL |
108 | #define SABRE_ICLR_UE 0x1870UL |
109 | #define SABRE_ICLR_CE 0x1878UL |
110 | #define SABRE_ICLR_PCIERR 0x1880UL |
111 | #define SABRE_WRSYNC 0x1c20UL |
112 | #define SABRE_PCICTRL 0x2000UL |
113 | #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */ |
114 | #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */ |
115 | #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */ |
116 | #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */ |
117 | #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */ |
118 | #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
119 | #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */ |
120 | #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */ |
121 | #define SABRE_PIOAFSR 0x2010UL |
122 | #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */ |
123 | #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */ |
124 | #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ |
125 | #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ |
126 | #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */ |
127 | #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */ |
128 | #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ |
129 | #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ |
130 | #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */ |
131 | #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */ |
132 | #define SABRE_PIOAFAR 0x2018UL |
133 | #define SABRE_PCIDIAG 0x2020UL |
134 | #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */ |
135 | #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */ |
136 | #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */ |
137 | #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */ |
138 | #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */ |
139 | #define SABRE_PCITASR 0x2028UL |
140 | #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */ |
141 | #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */ |
142 | #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */ |
143 | #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */ |
144 | #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */ |
145 | #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */ |
146 | #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */ |
147 | #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */ |
148 | #define SABRE_PIOBUF_DIAG 0x5000UL |
149 | #define SABRE_DMABUF_DIAGLO 0x5100UL |
150 | #define SABRE_DMABUF_DIAGHI 0x51c0UL |
151 | #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */ |
152 | #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */ |
153 | #define SABRE_IOMMU_VADIAG 0xa400UL |
154 | #define SABRE_IOMMU_TCDIAG 0xa408UL |
155 | #define SABRE_IOMMU_TAG 0xa580UL |
156 | #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */ |
157 | #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */ |
158 | #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */ |
159 | #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */ |
160 | #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */ |
161 | #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */ |
162 | #define SABRE_IOMMU_DATA 0xa600UL |
163 | #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */ |
164 | #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */ |
165 | #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */ |
166 | #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */ |
167 | #define SABRE_PCI_IRQSTATE 0xa800UL |
168 | #define SABRE_OBIO_IRQSTATE 0xa808UL |
169 | #define SABRE_FFBCFG 0xf000UL |
170 | #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */ |
171 | #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */ |
172 | #define SABRE_MCCTRL0 0xf010UL |
173 | #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */ |
174 | #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */ |
175 | #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */ |
176 | #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */ |
177 | #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */ |
178 | #define SABRE_MCCTRL1 0xf018UL |
179 | #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */ |
180 | #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */ |
181 | #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */ |
182 | #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */ |
183 | #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */ |
184 | #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */ |
185 | #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */ |
186 | #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */ |
187 | #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */ |
188 | #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */ |
189 | #define SABRE_RESETCTRL 0xf020UL |
190 | |
191 | #define SABRE_CONFIGSPACE 0x001000000UL |
192 | #define SABRE_IOSPACE 0x002000000UL |
193 | #define SABRE_IOSPACE_SIZE 0x000ffffffUL |
194 | #define SABRE_MEMSPACE 0x100000000UL |
195 | #define SABRE_MEMSPACE_SIZE 0x07fffffffUL |
196 | |
197 | static int hummingbird_p; |
198 | static struct pci_bus *sabre_root_bus; |
199 | |
200 | static irqreturn_t sabre_ue_intr(int irq, void *dev_id) |
201 | { |
202 | struct pci_pbm_info *pbm = dev_id; |
203 | unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR; |
204 | unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; |
205 | unsigned long afsr, afar, error_bits; |
206 | int reported; |
207 | |
208 | /* Latch uncorrectable error status. */ |
209 | afar = upa_readq(afar_reg); |
210 | afsr = upa_readq(afsr_reg); |
211 | |
212 | /* Clear the primary/secondary error status bits. */ |
213 | error_bits = afsr & |
214 | (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | |
215 | SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | |
216 | SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE); |
217 | if (!error_bits) |
218 | return IRQ_NONE; |
219 | upa_writeq(error_bits, afsr_reg); |
220 | |
221 | /* Log the error. */ |
222 | printk("%s: Uncorrectable Error, primary error type[%s%s]\n" , |
223 | pbm->name, |
224 | ((error_bits & SABRE_UEAFSR_PDRD) ? |
225 | "DMA Read" : |
226 | ((error_bits & SABRE_UEAFSR_PDWR) ? |
227 | "DMA Write" : "???" )), |
228 | ((error_bits & SABRE_UEAFSR_PDTE) ? |
229 | ":Translation Error" : "" )); |
230 | printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n" , |
231 | pbm->name, |
232 | (afsr & SABRE_UEAFSR_BMSK) >> 32UL, |
233 | (afsr & SABRE_UEAFSR_OFF) >> 29UL, |
234 | ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); |
235 | printk("%s: UE AFAR [%016lx]\n" , pbm->name, afar); |
236 | printk("%s: UE Secondary errors [" , pbm->name); |
237 | reported = 0; |
238 | if (afsr & SABRE_UEAFSR_SDRD) { |
239 | reported++; |
240 | printk("(DMA Read)" ); |
241 | } |
242 | if (afsr & SABRE_UEAFSR_SDWR) { |
243 | reported++; |
244 | printk("(DMA Write)" ); |
245 | } |
246 | if (afsr & SABRE_UEAFSR_SDTE) { |
247 | reported++; |
248 | printk("(Translation Error)" ); |
249 | } |
250 | if (!reported) |
251 | printk("(none)" ); |
252 | printk("]\n" ); |
253 | |
254 | /* Interrogate IOMMU for error status. */ |
255 | psycho_check_iommu_error(pbm, afsr, afar, type: UE_ERR); |
256 | |
257 | return IRQ_HANDLED; |
258 | } |
259 | |
260 | static irqreturn_t sabre_ce_intr(int irq, void *dev_id) |
261 | { |
262 | struct pci_pbm_info *pbm = dev_id; |
263 | unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR; |
264 | unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; |
265 | unsigned long afsr, afar, error_bits; |
266 | int reported; |
267 | |
268 | /* Latch error status. */ |
269 | afar = upa_readq(afar_reg); |
270 | afsr = upa_readq(afsr_reg); |
271 | |
272 | /* Clear primary/secondary error status bits. */ |
273 | error_bits = afsr & |
274 | (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | |
275 | SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR); |
276 | if (!error_bits) |
277 | return IRQ_NONE; |
278 | upa_writeq(error_bits, afsr_reg); |
279 | |
280 | /* Log the error. */ |
281 | printk("%s: Correctable Error, primary error type[%s]\n" , |
282 | pbm->name, |
283 | ((error_bits & SABRE_CEAFSR_PDRD) ? |
284 | "DMA Read" : |
285 | ((error_bits & SABRE_CEAFSR_PDWR) ? |
286 | "DMA Write" : "???" ))); |
287 | |
288 | /* XXX Use syndrome and afar to print out module string just like |
289 | * XXX UDB CE trap handler does... -DaveM |
290 | */ |
291 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
292 | "was_block(%d)\n" , |
293 | pbm->name, |
294 | (afsr & SABRE_CEAFSR_ESYND) >> 48UL, |
295 | (afsr & SABRE_CEAFSR_BMSK) >> 32UL, |
296 | (afsr & SABRE_CEAFSR_OFF) >> 29UL, |
297 | ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); |
298 | printk("%s: CE AFAR [%016lx]\n" , pbm->name, afar); |
299 | printk("%s: CE Secondary errors [" , pbm->name); |
300 | reported = 0; |
301 | if (afsr & SABRE_CEAFSR_SDRD) { |
302 | reported++; |
303 | printk("(DMA Read)" ); |
304 | } |
305 | if (afsr & SABRE_CEAFSR_SDWR) { |
306 | reported++; |
307 | printk("(DMA Write)" ); |
308 | } |
309 | if (!reported) |
310 | printk("(none)" ); |
311 | printk("]\n" ); |
312 | |
313 | return IRQ_HANDLED; |
314 | } |
315 | |
316 | static void sabre_register_error_handlers(struct pci_pbm_info *pbm) |
317 | { |
318 | struct device_node *dp = pbm->op->dev.of_node; |
319 | struct platform_device *op; |
320 | unsigned long base = pbm->controller_regs; |
321 | u64 tmp; |
322 | int err; |
323 | |
324 | if (pbm->chip_type == PBM_CHIP_TYPE_SABRE) |
325 | dp = dp->parent; |
326 | |
327 | op = of_find_device_by_node(np: dp); |
328 | if (!op) |
329 | return; |
330 | |
331 | /* Sabre/Hummingbird IRQ property layout is: |
332 | * 0: PCI ERR |
333 | * 1: UE ERR |
334 | * 2: CE ERR |
335 | * 3: POWER FAIL |
336 | */ |
337 | if (op->archdata.num_irqs < 4) |
338 | return; |
339 | |
340 | /* We clear the error bits in the appropriate AFSR before |
341 | * registering the handler so that we don't get spurious |
342 | * interrupts. |
343 | */ |
344 | upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | |
345 | SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | |
346 | SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE), |
347 | base + SABRE_UE_AFSR); |
348 | |
349 | err = request_irq(irq: op->archdata.irqs[1], handler: sabre_ue_intr, flags: 0, name: "SABRE_UE" , dev: pbm); |
350 | if (err) |
351 | printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n" , |
352 | pbm->name, err); |
353 | |
354 | upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | |
355 | SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR), |
356 | base + SABRE_CE_AFSR); |
357 | |
358 | |
359 | err = request_irq(irq: op->archdata.irqs[2], handler: sabre_ce_intr, flags: 0, name: "SABRE_CE" , dev: pbm); |
360 | if (err) |
361 | printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n" , |
362 | pbm->name, err); |
363 | err = request_irq(irq: op->archdata.irqs[0], handler: psycho_pcierr_intr, flags: 0, |
364 | name: "SABRE_PCIERR" , dev: pbm); |
365 | if (err) |
366 | printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n" , |
367 | pbm->name, err); |
368 | |
369 | tmp = upa_readq(base + SABRE_PCICTRL); |
370 | tmp |= SABRE_PCICTRL_ERREN; |
371 | upa_writeq(tmp, base + SABRE_PCICTRL); |
372 | } |
373 | |
374 | static void apb_init(struct pci_bus *sabre_bus) |
375 | { |
376 | struct pci_dev *pdev; |
377 | |
378 | list_for_each_entry(pdev, &sabre_bus->devices, bus_list) { |
379 | if (pdev->vendor == PCI_VENDOR_ID_SUN && |
380 | pdev->device == PCI_DEVICE_ID_SUN_SIMBA) { |
381 | u16 word16; |
382 | |
383 | pci_read_config_word(dev: pdev, PCI_COMMAND, val: &word16); |
384 | word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | |
385 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
386 | PCI_COMMAND_IO; |
387 | pci_write_config_word(dev: pdev, PCI_COMMAND, val: word16); |
388 | |
389 | /* Status register bits are "write 1 to clear". */ |
390 | pci_write_config_word(dev: pdev, PCI_STATUS, val: 0xffff); |
391 | pci_write_config_word(dev: pdev, PCI_SEC_STATUS, val: 0xffff); |
392 | |
393 | /* Use a primary/seconday latency timer value |
394 | * of 64. |
395 | */ |
396 | pci_write_config_byte(dev: pdev, PCI_LATENCY_TIMER, val: 64); |
397 | pci_write_config_byte(dev: pdev, PCI_SEC_LATENCY_TIMER, val: 64); |
398 | |
399 | /* Enable reporting/forwarding of master aborts, |
400 | * parity, and SERR. |
401 | */ |
402 | pci_write_config_byte(dev: pdev, PCI_BRIDGE_CONTROL, |
403 | val: (PCI_BRIDGE_CTL_PARITY | |
404 | PCI_BRIDGE_CTL_SERR | |
405 | PCI_BRIDGE_CTL_MASTER_ABORT)); |
406 | } |
407 | } |
408 | } |
409 | |
410 | static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent) |
411 | { |
412 | static int once; |
413 | |
414 | /* The APB bridge speaks to the Sabre host PCI bridge |
415 | * at 66Mhz, but the front side of APB runs at 33Mhz |
416 | * for both segments. |
417 | * |
418 | * Hummingbird systems do not use APB, so they run |
419 | * at 66MHZ. |
420 | */ |
421 | if (hummingbird_p) |
422 | pbm->is_66mhz_capable = 1; |
423 | else |
424 | pbm->is_66mhz_capable = 0; |
425 | |
426 | /* This driver has not been verified to handle |
427 | * multiple SABREs yet, so trap this. |
428 | * |
429 | * Also note that the SABRE host bridge is hardwired |
430 | * to live at bus 0. |
431 | */ |
432 | if (once != 0) { |
433 | printk(KERN_ERR PFX "Multiple controllers unsupported.\n" ); |
434 | return; |
435 | } |
436 | once++; |
437 | |
438 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
439 | if (!pbm->pci_bus) |
440 | return; |
441 | |
442 | sabre_root_bus = pbm->pci_bus; |
443 | |
444 | apb_init(sabre_bus: pbm->pci_bus); |
445 | |
446 | sabre_register_error_handlers(pbm); |
447 | } |
448 | |
449 | static void sabre_pbm_init(struct pci_pbm_info *pbm, |
450 | struct platform_device *op) |
451 | { |
452 | psycho_pbm_init_common(pbm, op, chip_name: "SABRE" , PBM_CHIP_TYPE_SABRE); |
453 | pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR; |
454 | pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR; |
455 | pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL; |
456 | sabre_scan_bus(pbm, parent: &op->dev); |
457 | } |
458 | |
459 | static const struct of_device_id sabre_match[]; |
460 | static int sabre_probe(struct platform_device *op) |
461 | { |
462 | const struct linux_prom64_registers *pr_regs; |
463 | struct device_node *dp = op->dev.of_node; |
464 | struct pci_pbm_info *pbm; |
465 | u32 upa_portid, dma_mask; |
466 | struct iommu *iommu; |
467 | int tsbsize, err; |
468 | const u32 *vdma; |
469 | u64 clear_irq; |
470 | |
471 | hummingbird_p = (uintptr_t)device_get_match_data(dev: &op->dev); |
472 | if (!hummingbird_p) { |
473 | struct device_node *cpu_dp; |
474 | |
475 | /* Of course, Sun has to encode things a thousand |
476 | * different ways, inconsistently. |
477 | */ |
478 | for_each_node_by_type(cpu_dp, "cpu" ) { |
479 | if (of_node_name_eq(np: cpu_dp, name: "SUNW,UltraSPARC-IIe" )) |
480 | hummingbird_p = 1; |
481 | } |
482 | } |
483 | |
484 | err = -ENOMEM; |
485 | pbm = kzalloc(size: sizeof(*pbm), GFP_KERNEL); |
486 | if (!pbm) { |
487 | printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n" ); |
488 | goto out_err; |
489 | } |
490 | |
491 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
492 | if (!iommu) { |
493 | printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n" ); |
494 | goto out_free_controller; |
495 | } |
496 | |
497 | pbm->iommu = iommu; |
498 | |
499 | upa_portid = of_getintprop_default(dp, "upa-portid" , 0xff); |
500 | |
501 | pbm->portid = upa_portid; |
502 | |
503 | /* |
504 | * Map in SABRE register set and report the presence of this SABRE. |
505 | */ |
506 | |
507 | pr_regs = of_get_property(node: dp, name: "reg" , NULL); |
508 | err = -ENODEV; |
509 | if (!pr_regs) { |
510 | printk(KERN_ERR PFX "No reg property\n" ); |
511 | goto out_free_iommu; |
512 | } |
513 | |
514 | /* |
515 | * First REG in property is base of entire SABRE register space. |
516 | */ |
517 | pbm->controller_regs = pr_regs[0].phys_addr; |
518 | |
519 | /* Clear interrupts */ |
520 | |
521 | /* PCI first */ |
522 | for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) |
523 | upa_writeq(0x0UL, pbm->controller_regs + clear_irq); |
524 | |
525 | /* Then OBIO */ |
526 | for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) |
527 | upa_writeq(0x0UL, pbm->controller_regs + clear_irq); |
528 | |
529 | /* Error interrupts are enabled later after the bus scan. */ |
530 | upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | |
531 | SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN), |
532 | pbm->controller_regs + SABRE_PCICTRL); |
533 | |
534 | /* Now map in PCI config space for entire SABRE. */ |
535 | pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE; |
536 | |
537 | vdma = of_get_property(node: dp, name: "virtual-dma" , NULL); |
538 | if (!vdma) { |
539 | printk(KERN_ERR PFX "No virtual-dma property\n" ); |
540 | goto out_free_iommu; |
541 | } |
542 | |
543 | dma_mask = vdma[0]; |
544 | switch(vdma[1]) { |
545 | case 0x20000000: |
546 | dma_mask |= 0x1fffffff; |
547 | tsbsize = 64; |
548 | break; |
549 | case 0x40000000: |
550 | dma_mask |= 0x3fffffff; |
551 | tsbsize = 128; |
552 | break; |
553 | |
554 | case 0x80000000: |
555 | dma_mask |= 0x7fffffff; |
556 | tsbsize = 128; |
557 | break; |
558 | default: |
559 | printk(KERN_ERR PFX "Strange virtual-dma size.\n" ); |
560 | goto out_free_iommu; |
561 | } |
562 | |
563 | err = psycho_iommu_init(pbm, tsbsize, dvma_offset: vdma[0], dma_mask, SABRE_WRSYNC); |
564 | if (err) |
565 | goto out_free_iommu; |
566 | |
567 | /* |
568 | * Look for APB underneath. |
569 | */ |
570 | sabre_pbm_init(pbm, op); |
571 | |
572 | pbm->next = pci_pbm_root; |
573 | pci_pbm_root = pbm; |
574 | |
575 | dev_set_drvdata(dev: &op->dev, data: pbm); |
576 | |
577 | return 0; |
578 | |
579 | out_free_iommu: |
580 | kfree(objp: pbm->iommu); |
581 | |
582 | out_free_controller: |
583 | kfree(objp: pbm); |
584 | |
585 | out_err: |
586 | return err; |
587 | } |
588 | |
589 | static const struct of_device_id sabre_match[] = { |
590 | { |
591 | .name = "pci" , |
592 | .compatible = "pci108e,a001" , |
593 | .data = (void *) 1, |
594 | }, |
595 | { |
596 | .name = "pci" , |
597 | .compatible = "pci108e,a000" , |
598 | }, |
599 | {}, |
600 | }; |
601 | |
602 | static struct platform_driver sabre_driver = { |
603 | .driver = { |
604 | .name = DRIVER_NAME, |
605 | .of_match_table = sabre_match, |
606 | }, |
607 | .probe = sabre_probe, |
608 | }; |
609 | |
610 | static int __init sabre_init(void) |
611 | { |
612 | return platform_driver_register(&sabre_driver); |
613 | } |
614 | |
615 | subsys_initcall(sabre_init); |
616 | |