1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_cmnd.h>
31#include <linux/libata.h>
32#include <linux/ahci-remap.h>
33#include <linux/io-64-nonatomic-lo-hi.h>
34#include "ahci.h"
35
36#define DRV_NAME "ahci"
37#define DRV_VERSION "3.0"
38
39enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46};
47
48enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_no_debounce_delay,
54 board_ahci_no_msi,
55 /*
56 * board_ahci_pcs_quirk is for legacy Intel platforms.
57 * Modern Intel platforms should use board_ahci instead.
58 * (Some modern Intel platforms might have been added with
59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
60 * without testing that the platform actually works without the quirk.)
61 */
62 board_ahci_pcs_quirk,
63 board_ahci_pcs_quirk_no_devslp,
64 board_ahci_pcs_quirk_no_sntf,
65 board_ahci_yes_fbs,
66 board_ahci_yes_fbs_atapi_dma,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_al,
70 board_ahci_avn,
71 board_ahci_mcp65,
72 board_ahci_mcp77,
73 board_ahci_mcp89,
74 board_ahci_mv,
75 board_ahci_sb600,
76 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_vt8251,
78
79 /* aliases */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
84};
85
86static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87static void ahci_remove_one(struct pci_dev *dev);
88static void ahci_shutdown_one(struct pci_dev *dev);
89static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
90static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
95static bool is_mcp89_apple(struct pci_dev *pdev);
96static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
97 unsigned long deadline);
98#ifdef CONFIG_PM
99static int ahci_pci_device_runtime_suspend(struct device *dev);
100static int ahci_pci_device_runtime_resume(struct device *dev);
101#ifdef CONFIG_PM_SLEEP
102static int ahci_pci_device_suspend(struct device *dev);
103static int ahci_pci_device_resume(struct device *dev);
104#endif
105#endif /* CONFIG_PM */
106
107static const struct scsi_host_template ahci_sht = {
108 AHCI_SHT("ahci"),
109};
110
111static struct ata_port_operations ahci_vt8251_ops = {
112 .inherits = &ahci_ops,
113 .hardreset = ahci_vt8251_hardreset,
114};
115
116static struct ata_port_operations ahci_p5wdh_ops = {
117 .inherits = &ahci_ops,
118 .hardreset = ahci_p5wdh_hardreset,
119};
120
121static struct ata_port_operations ahci_avn_ops = {
122 .inherits = &ahci_ops,
123 .hardreset = ahci_avn_hardreset,
124};
125
126static const struct ata_port_info ahci_port_info[] = {
127 /* by features */
128 [board_ahci] = {
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
133 },
134 [board_ahci_43bit_dma] = {
135 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
136 .flags = AHCI_FLAG_COMMON,
137 .pio_mask = ATA_PIO4,
138 .udma_mask = ATA_UDMA6,
139 .port_ops = &ahci_ops,
140 },
141 [board_ahci_ign_iferr] = {
142 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 [board_ahci_no_debounce_delay] = {
149 .flags = AHCI_FLAG_COMMON,
150 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
151 .pio_mask = ATA_PIO4,
152 .udma_mask = ATA_UDMA6,
153 .port_ops = &ahci_ops,
154 },
155 [board_ahci_no_msi] = {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_pcs_quirk] = {
163 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
169 [board_ahci_pcs_quirk_no_devslp] = {
170 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
171 AHCI_HFLAG_NO_DEVSLP),
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
176 },
177 [board_ahci_pcs_quirk_no_sntf] = {
178 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
179 AHCI_HFLAG_NO_SNTF),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_yes_fbs] = {
186 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_yes_fbs_atapi_dma] = {
193 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS |
194 AHCI_HFLAG_ATAPI_DMA_QUIRK),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 /* by chipsets */
201 [board_ahci_al] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_avn] = {
209 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
210 .flags = AHCI_FLAG_COMMON,
211 .pio_mask = ATA_PIO4,
212 .udma_mask = ATA_UDMA6,
213 .port_ops = &ahci_avn_ops,
214 },
215 [board_ahci_mcp65] = {
216 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
217 AHCI_HFLAG_YES_NCQ),
218 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_ops,
222 },
223 [board_ahci_mcp77] = {
224 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
225 .flags = AHCI_FLAG_COMMON,
226 .pio_mask = ATA_PIO4,
227 .udma_mask = ATA_UDMA6,
228 .port_ops = &ahci_ops,
229 },
230 [board_ahci_mcp89] = {
231 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
232 .flags = AHCI_FLAG_COMMON,
233 .pio_mask = ATA_PIO4,
234 .udma_mask = ATA_UDMA6,
235 .port_ops = &ahci_ops,
236 },
237 [board_ahci_mv] = {
238 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
239 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
240 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245 [board_ahci_sb600] = {
246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
247 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
248 AHCI_HFLAG_32BIT_ONLY),
249 .flags = AHCI_FLAG_COMMON,
250 .pio_mask = ATA_PIO4,
251 .udma_mask = ATA_UDMA6,
252 .port_ops = &ahci_pmp_retry_srst_ops,
253 },
254 [board_ahci_sb700] = { /* for SB700 and SB800 */
255 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_pmp_retry_srst_ops,
260 },
261 [board_ahci_vt8251] = {
262 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
263 .flags = AHCI_FLAG_COMMON,
264 .pio_mask = ATA_PIO4,
265 .udma_mask = ATA_UDMA6,
266 .port_ops = &ahci_vt8251_ops,
267 },
268};
269
270static const struct pci_device_id ahci_pci_tbl[] = {
271 /* Intel */
272 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
273 { PCI_VDEVICE(INTEL, 0x2652), .vendor: board_ahci_pcs_quirk }, /* ICH6 */
274 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */
275 { PCI_VDEVICE(INTEL, 0x27c1), .vendor: board_ahci_pcs_quirk }, /* ICH7 */
276 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */
277 { PCI_VDEVICE(INTEL, 0x27c3), .vendor: board_ahci_pcs_quirk }, /* ICH7R */
278 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
279 { PCI_VDEVICE(INTEL, 0x2681), .vendor: board_ahci_pcs_quirk }, /* ESB2 */
280 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */
281 { PCI_VDEVICE(INTEL, 0x2683), .vendor: board_ahci_pcs_quirk }, /* ESB2 */
282 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */
283 { PCI_VDEVICE(INTEL, 0x2821), .vendor: board_ahci_pcs_quirk }, /* ICH8 */
284 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/
285 { PCI_VDEVICE(INTEL, 0x2824), .vendor: board_ahci_pcs_quirk }, /* ICH8 */
286 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */
287 { PCI_VDEVICE(INTEL, 0x282a), .vendor: board_ahci_pcs_quirk }, /* ICH8M */
288 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */
289 { PCI_VDEVICE(INTEL, 0x2923), .vendor: board_ahci_pcs_quirk }, /* ICH9 */
290 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */
291 { PCI_VDEVICE(INTEL, 0x2925), .vendor: board_ahci_pcs_quirk }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */
293 { PCI_VDEVICE(INTEL, 0x2929), .vendor: board_ahci_pcs_quirk }, /* ICH9M */
294 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */
295 { PCI_VDEVICE(INTEL, 0x292b), .vendor: board_ahci_pcs_quirk }, /* ICH9M */
296 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */
297 { PCI_VDEVICE(INTEL, 0x292f), .vendor: board_ahci_pcs_quirk }, /* ICH9M */
298 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */
299 { PCI_VDEVICE(INTEL, 0x294e), .vendor: board_ahci_pcs_quirk }, /* ICH9M */
300 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */
301 { PCI_VDEVICE(INTEL, 0x502b), .vendor: board_ahci_pcs_quirk }, /* Tolapai */
302 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */
303 { PCI_VDEVICE(INTEL, 0x3a22), .vendor: board_ahci_pcs_quirk }, /* ICH10 */
304 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */
305 { PCI_VDEVICE(INTEL, 0x3b22), .vendor: board_ahci_pcs_quirk }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */
307 { PCI_VDEVICE(INTEL, 0x3b24), .vendor: board_ahci_pcs_quirk }, /* PCH RAID */
308 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */
309 { PCI_VDEVICE(INTEL, 0x3b29), .vendor: board_ahci_pcs_quirk }, /* PCH M AHCI */
310 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */
311 { PCI_VDEVICE(INTEL, 0x3b2c), .vendor: board_ahci_pcs_quirk }, /* PCH M RAID */
312 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b0), .vendor: board_ahci }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19b2), .vendor: board_ahci }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19b4), .vendor: board_ahci }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19b6), .vendor: board_ahci }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19bE), .vendor: board_ahci }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c0), .vendor: board_ahci }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19c2), .vendor: board_ahci }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
327 { PCI_VDEVICE(INTEL, 0x19c4), .vendor: board_ahci }, /* DNV AHCI */
328 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
329 { PCI_VDEVICE(INTEL, 0x19c6), .vendor: board_ahci }, /* DNV AHCI */
330 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
331 { PCI_VDEVICE(INTEL, 0x19cE), .vendor: board_ahci }, /* DNV AHCI */
332 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
333 { PCI_VDEVICE(INTEL, 0x1c02), .vendor: board_ahci_pcs_quirk }, /* CPT AHCI */
334 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */
335 { PCI_VDEVICE(INTEL, 0x1c04), .vendor: board_ahci_pcs_quirk }, /* CPT RAID */
336 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */
337 { PCI_VDEVICE(INTEL, 0x1c06), .vendor: board_ahci_pcs_quirk }, /* CPT RAID */
338 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */
339 { PCI_VDEVICE(INTEL, 0x1d02), .vendor: board_ahci_pcs_quirk }, /* PBG AHCI */
340 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */
341 { PCI_VDEVICE(INTEL, 0x1d06), .vendor: board_ahci_pcs_quirk }, /* PBG RAID */
342 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */
343 { PCI_VDEVICE(INTEL, 0x1e02), .vendor: board_ahci_pcs_quirk }, /* Panther Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */
345 { PCI_VDEVICE(INTEL, 0x1e04), .vendor: board_ahci_pcs_quirk }, /* Panther Point RAID */
346 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */
347 { PCI_VDEVICE(INTEL, 0x1e06), .vendor: board_ahci_pcs_quirk }, /* Panther Point RAID */
348 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */
349 { PCI_VDEVICE(INTEL, 0x1e0e), .vendor: board_ahci_pcs_quirk }, /* Panther Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */
351 { PCI_VDEVICE(INTEL, 0x8c03), .vendor: board_ahci_pcs_quirk }, /* Lynx M AHCI */
352 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */
353 { PCI_VDEVICE(INTEL, 0x8c05), .vendor: board_ahci_pcs_quirk }, /* Lynx M RAID */
354 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */
355 { PCI_VDEVICE(INTEL, 0x8c07), .vendor: board_ahci_pcs_quirk }, /* Lynx M RAID */
356 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */
357 { PCI_VDEVICE(INTEL, 0x8c0f), .vendor: board_ahci_pcs_quirk }, /* Lynx M RAID */
358 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9c03), .vendor: board_ahci_pcs_quirk }, /* Lynx LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9c05), .vendor: board_ahci_pcs_quirk }, /* Lynx LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */
363 { PCI_VDEVICE(INTEL, 0x9c07), .vendor: board_ahci_pcs_quirk }, /* Lynx LP RAID */
364 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */
365 { PCI_VDEVICE(INTEL, 0x9c0f), .vendor: board_ahci_pcs_quirk }, /* Lynx LP RAID */
366 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */
367 { PCI_VDEVICE(INTEL, 0x1f22), .vendor: board_ahci_pcs_quirk }, /* Avoton AHCI */
368 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f24), .vendor: board_ahci_pcs_quirk }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f26), .vendor: board_ahci_pcs_quirk }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f2e), .vendor: board_ahci_pcs_quirk }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f32), .vendor: board_ahci_avn }, /* Avoton AHCI */
376 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
377 { PCI_VDEVICE(INTEL, 0x1f34), .vendor: board_ahci_avn }, /* Avoton RAID */
378 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
379 { PCI_VDEVICE(INTEL, 0x1f36), .vendor: board_ahci_avn }, /* Avoton RAID */
380 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
381 { PCI_VDEVICE(INTEL, 0x1f3e), .vendor: board_ahci_avn }, /* Avoton RAID */
382 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
383 { PCI_VDEVICE(INTEL, 0x2823), .vendor: board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/
384 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */
385 { PCI_VDEVICE(INTEL, 0x2827), .vendor: board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */
386 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */
387 { PCI_VDEVICE(INTEL, 0x43d4), .vendor: board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
388 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
389 { PCI_VDEVICE(INTEL, 0x43d6), .vendor: board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
390 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
391 { PCI_VDEVICE(INTEL, 0x8d02), .vendor: board_ahci_pcs_quirk }, /* Wellsburg AHCI */
392 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */
393 { PCI_VDEVICE(INTEL, 0x8d06), .vendor: board_ahci_pcs_quirk }, /* Wellsburg RAID */
394 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
395 { PCI_VDEVICE(INTEL, 0x8d62), .vendor: board_ahci_pcs_quirk }, /* Wellsburg AHCI */
396 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */
397 { PCI_VDEVICE(INTEL, 0x8d66), .vendor: board_ahci_pcs_quirk }, /* Wellsburg RAID */
398 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
399 { PCI_VDEVICE(INTEL, 0x23a3), .vendor: board_ahci_pcs_quirk }, /* Coleto Creek AHCI */
400 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */
401 { PCI_VDEVICE(INTEL, 0x9c85), .vendor: board_ahci_pcs_quirk }, /* Wildcat LP RAID */
402 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
403 { PCI_VDEVICE(INTEL, 0x9c8f), .vendor: board_ahci_pcs_quirk }, /* Wildcat LP RAID */
404 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */
405 { PCI_VDEVICE(INTEL, 0x8c83), .vendor: board_ahci_pcs_quirk }, /* 9 Series M AHCI */
406 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */
407 { PCI_VDEVICE(INTEL, 0x8c85), .vendor: board_ahci_pcs_quirk }, /* 9 Series M RAID */
408 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */
409 { PCI_VDEVICE(INTEL, 0x8c87), .vendor: board_ahci_pcs_quirk }, /* 9 Series M RAID */
410 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */
411 { PCI_VDEVICE(INTEL, 0x8c8f), .vendor: board_ahci_pcs_quirk }, /* 9 Series M RAID */
412 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */
413 { PCI_VDEVICE(INTEL, 0x9d05), .vendor: board_ahci_pcs_quirk }, /* Sunrise LP RAID */
414 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
415 { PCI_VDEVICE(INTEL, 0xa102), .vendor: board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */
416 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */
417 { PCI_VDEVICE(INTEL, 0xa105), .vendor: board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
418 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
419 { PCI_VDEVICE(INTEL, 0xa107), .vendor: board_ahci_pcs_quirk }, /* Sunrise M RAID */
420 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
421 { PCI_VDEVICE(INTEL, 0xa182), .vendor: board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
422 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
423 { PCI_VDEVICE(INTEL, 0xa1d2), .vendor: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
424 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
425 { PCI_VDEVICE(INTEL, 0xa202), .vendor: board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
426 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
427 { PCI_VDEVICE(INTEL, 0xa252), .vendor: board_ahci_pcs_quirk }, /* Lewisburg RAID*/
428 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
429 { PCI_VDEVICE(INTEL, 0xa356), .vendor: board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */
430 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */
431 { PCI_VDEVICE(INTEL, 0xa386), .vendor: board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */
432 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */
433 { PCI_VDEVICE(INTEL, 0x0f23), .vendor: board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */
434 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */
435 { PCI_VDEVICE(INTEL, 0x5ae3), .vendor: board_ahci_pcs_quirk }, /* ApolloLake AHCI */
436 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */
437 { PCI_VDEVICE(INTEL, 0x02d3), .vendor: board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */
438 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */
439 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
440 { PCI_VDEVICE(INTEL, 0x4b63), .vendor: board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
441
442 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
443 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
444 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
445 /* JMicron 362B and 362C have an AHCI function with IDE class code */
446 { PCI_VDEVICE(JMICRON, 0x2362), .vendor: board_ahci_ign_iferr },
447 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
448 /* May need to update quirk_jmicron_async_suspend() for additions */
449
450 /* ATI */
451 { PCI_VDEVICE(ATI, 0x4380), .vendor: board_ahci_sb600 }, /* ATI SB600 */
452 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
453 { PCI_VDEVICE(ATI, 0x4391), .vendor: board_ahci_sb700 }, /* ATI SB700/800 */
454 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
455 { PCI_VDEVICE(ATI, 0x4393), .vendor: board_ahci_sb700 }, /* ATI SB700/800 */
456 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
457 { PCI_VDEVICE(ATI, 0x4395), .vendor: board_ahci_sb700 }, /* ATI SB700/800 */
458
459 /* Amazon's Annapurna Labs support */
460 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
461 .class = PCI_CLASS_STORAGE_SATA_AHCI,
462 .class_mask = 0xffffff,
463 board_ahci_al },
464 /* AMD */
465 { PCI_VDEVICE(AMD, 0x7800), .vendor: board_ahci }, /* AMD Hudson-2 */
466 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
467 { PCI_VDEVICE(AMD, 0x7900), .vendor: board_ahci }, /* AMD CZ */
468 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */
469 /* AMD is using RAID class only for ahci controllers */
470 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
471 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, .vendor: board_ahci },
472
473 /* Dell S140/S150 */
474 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
475 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk },
476
477 /* VIA */
478 { PCI_VDEVICE(VIA, 0x3349), .vendor: board_ahci_vt8251 }, /* VIA VT8251 */
479 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
480
481 /* NVIDIA */
482 { PCI_VDEVICE(NVIDIA, 0x044c), .vendor: board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x044e), .vendor: board_ahci_mcp65 }, /* MCP65 */
485 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
486 { PCI_VDEVICE(NVIDIA, 0x045c), .vendor: board_ahci_mcp65 }, /* MCP65 */
487 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
488 { PCI_VDEVICE(NVIDIA, 0x045e), .vendor: board_ahci_mcp65 }, /* MCP65 */
489 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
490 { PCI_VDEVICE(NVIDIA, 0x0550), .vendor: board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0552), .vendor: board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x0554), .vendor: board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0556), .vendor: board_ahci_mcp67 }, /* MCP67 */
497 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
498 { PCI_VDEVICE(NVIDIA, 0x0558), .vendor: board_ahci_mcp67 }, /* MCP67 */
499 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
500 { PCI_VDEVICE(NVIDIA, 0x055a), .vendor: board_ahci_mcp67 }, /* MCP67 */
501 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
502 { PCI_VDEVICE(NVIDIA, 0x0580), .vendor: board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0582), .vendor: board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x0584), .vendor: board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x0586), .vendor: board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x0588), .vendor: board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
512 { PCI_VDEVICE(NVIDIA, 0x058a), .vendor: board_ahci_mcp_linux }, /* Linux ID */
513 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
514 { PCI_VDEVICE(NVIDIA, 0x058c), .vendor: board_ahci_mcp_linux }, /* Linux ID */
515 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
516 { PCI_VDEVICE(NVIDIA, 0x058e), .vendor: board_ahci_mcp_linux }, /* Linux ID */
517 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
518 { PCI_VDEVICE(NVIDIA, 0x07f0), .vendor: board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f2), .vendor: board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f4), .vendor: board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f6), .vendor: board_ahci_mcp73 }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f8), .vendor: board_ahci_mcp73 }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07fa), .vendor: board_ahci_mcp73 }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad0), .vendor: board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad2), .vendor: board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad4), .vendor: board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad6), .vendor: board_ahci_mcp77 }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad8), .vendor: board_ahci_mcp77 }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ada), .vendor: board_ahci_mcp77 }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0ab4), .vendor: board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab6), .vendor: board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab8), .vendor: board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0aba), .vendor: board_ahci_mcp79 }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abc), .vendor: board_ahci_mcp79 }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abe), .vendor: board_ahci_mcp79 }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0d84), .vendor: board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d86), .vendor: board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d88), .vendor: board_ahci_mcp89 }, /* MCP89 */
559 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
560 { PCI_VDEVICE(NVIDIA, 0x0d8a), .vendor: board_ahci_mcp89 }, /* MCP89 */
561 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
562 { PCI_VDEVICE(NVIDIA, 0x0d8c), .vendor: board_ahci_mcp89 }, /* MCP89 */
563 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
564 { PCI_VDEVICE(NVIDIA, 0x0d8e), .vendor: board_ahci_mcp89 }, /* MCP89 */
565 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
566
567 /* SiS */
568 { PCI_VDEVICE(SI, 0x1184), .vendor: board_ahci }, /* SiS 966 */
569 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
570 { PCI_VDEVICE(SI, 0x0186), .vendor: board_ahci }, /* SiS 968 */
571
572 /* ST Microelectronics */
573 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
574
575 /* Marvell */
576 { PCI_VDEVICE(MARVELL, 0x6145), .vendor: board_ahci_mv }, /* 6145 */
577 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
579 .class = PCI_CLASS_STORAGE_SATA_AHCI,
580 .class_mask = 0xffffff,
581 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
584 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
585 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
586 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
588 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
590 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
592 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
594 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
596 .driver_data = board_ahci_yes_fbs },
597 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
598 .driver_data = board_ahci_yes_fbs },
599 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
600 .driver_data = board_ahci_yes_fbs },
601 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215),
602 .driver_data = board_ahci_yes_fbs_atapi_dma },
603 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
604 .driver_data = board_ahci_yes_fbs },
605 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
606 .driver_data = board_ahci_no_debounce_delay },
607 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
608 .driver_data = board_ahci_yes_fbs },
609 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
610 .driver_data = board_ahci_yes_fbs },
611
612 /* Promise */
613 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
614 { PCI_VDEVICE(PROMISE, 0x3781), .vendor: board_ahci }, /* FastTrak TX8660 ahci-mode */
615
616 /* ASMedia */
617 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
618 { PCI_VDEVICE(ASMEDIA, 0x0602), .vendor: board_ahci_43bit_dma }, /* ASM1060 */
619 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
620 { PCI_VDEVICE(ASMEDIA, 0x0612), .vendor: board_ahci_43bit_dma }, /* ASM1061/1062 */
621 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
622 { PCI_VDEVICE(ASMEDIA, 0x0622), .vendor: board_ahci_43bit_dma }, /* ASM1062R */
623 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
624 { PCI_VDEVICE(ASMEDIA, 0x1062), .vendor: board_ahci }, /* ASM1062A */
625 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
626 { PCI_VDEVICE(ASMEDIA, 0x1164), .vendor: board_ahci }, /* ASM1164 */
627 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
628 { PCI_VDEVICE(ASMEDIA, 0x1166), .vendor: board_ahci }, /* ASM1166 */
629
630 /*
631 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
632 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
633 */
634 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi },
635 { PCI_VDEVICE(SAMSUNG, 0xa800), .vendor: board_ahci_no_msi },
636
637 /* Enmotus */
638 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
639
640 /* Loongson */
641 { PCI_VDEVICE(LOONGSON, 0x7a08), .vendor: board_ahci },
642
643 /* Generic, PCI class code for AHCI */
644 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
645 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
646
647 { } /* terminate list */
648};
649
650static const struct dev_pm_ops ahci_pci_pm_ops = {
651 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
652 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
653 ahci_pci_device_runtime_resume, NULL)
654};
655
656static struct pci_driver ahci_pci_driver = {
657 .name = DRV_NAME,
658 .id_table = ahci_pci_tbl,
659 .probe = ahci_init_one,
660 .remove = ahci_remove_one,
661 .shutdown = ahci_shutdown_one,
662 .driver = {
663 .pm = &ahci_pci_pm_ops,
664 },
665};
666
667#if IS_ENABLED(CONFIG_PATA_MARVELL)
668static int marvell_enable;
669#else
670static int marvell_enable = 1;
671#endif
672module_param(marvell_enable, int, 0644);
673MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
674
675static int mobile_lpm_policy = -1;
676module_param(mobile_lpm_policy, int, 0644);
677MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
678
679static char *ahci_mask_port_map;
680module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
681MODULE_PARM_DESC(mask_port_map,
682 "32-bits port map masks to ignore controllers ports. "
683 "Valid values are: "
684 "\"<mask>\" to apply the same mask to all AHCI controller "
685 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
686 "specify different masks for the controllers specified, "
687 "where <pci_dev> is the PCI ID of an AHCI controller in the "
688 "form \"domain:bus:dev.func\"");
689
690static void ahci_apply_port_map_mask(struct device *dev,
691 struct ahci_host_priv *hpriv, char *mask_s)
692{
693 unsigned int mask;
694
695 if (kstrtouint(s: mask_s, base: 0, res: &mask)) {
696 dev_err(dev, "Invalid port map mask\n");
697 return;
698 }
699
700 hpriv->mask_port_map = mask;
701}
702
703static void ahci_get_port_map_mask(struct device *dev,
704 struct ahci_host_priv *hpriv)
705{
706 char *param, *end, *str, *mask_s;
707 char *name;
708
709 if (!strlen(ahci_mask_port_map))
710 return;
711
712 str = kstrdup(s: ahci_mask_port_map, GFP_KERNEL);
713 if (!str)
714 return;
715
716 /* Handle single mask case */
717 if (!strchr(str, '=')) {
718 ahci_apply_port_map_mask(dev, hpriv, mask_s: str);
719 goto free;
720 }
721
722 /*
723 * Mask list case: parse the parameter to apply the mask only if
724 * the device name matches.
725 */
726 param = str;
727 end = param + strlen(param);
728 while (param && param < end && *param) {
729 name = param;
730 param = strchr(name, '=');
731 if (!param)
732 break;
733
734 *param = '\0';
735 param++;
736 if (param >= end)
737 break;
738
739 if (strcmp(dev_name(dev), name) != 0) {
740 param = strchr(param, ',');
741 if (param)
742 param++;
743 continue;
744 }
745
746 mask_s = param;
747 param = strchr(mask_s, ',');
748 if (param) {
749 *param = '\0';
750 param++;
751 }
752
753 ahci_apply_port_map_mask(dev, hpriv, mask_s);
754 }
755
756free:
757 kfree(objp: str);
758}
759
760static void ahci_pci_save_initial_config(struct pci_dev *pdev,
761 struct ahci_host_priv *hpriv)
762{
763 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
764 dev_info(&pdev->dev, "JMB361 has only one port\n");
765 hpriv->saved_port_map = 1;
766 }
767
768 /*
769 * Temporary Marvell 6145 hack: PATA port presence
770 * is asserted through the standard AHCI port
771 * presence register, as bit 4 (counting from 0)
772 */
773 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
774 if (pdev->device == 0x6121)
775 hpriv->mask_port_map = 0x3;
776 else
777 hpriv->mask_port_map = 0xf;
778 dev_info(&pdev->dev,
779 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
780 }
781
782 /* Handle port map masks passed as module parameter. */
783 if (ahci_mask_port_map)
784 ahci_get_port_map_mask(dev: &pdev->dev, hpriv);
785
786 ahci_save_initial_config(dev: &pdev->dev, hpriv);
787}
788
789static int ahci_pci_reset_controller(struct ata_host *host)
790{
791 struct pci_dev *pdev = to_pci_dev(host->dev);
792 struct ahci_host_priv *hpriv = host->private_data;
793 int rc;
794
795 rc = ahci_reset_controller(host);
796 if (rc)
797 return rc;
798
799 /*
800 * If platform firmware failed to enable ports, try to enable
801 * them here.
802 */
803 ahci_intel_pcs_quirk(pdev, hpriv);
804
805 return 0;
806}
807
808static void ahci_pci_init_controller(struct ata_host *host)
809{
810 struct ahci_host_priv *hpriv = host->private_data;
811 struct pci_dev *pdev = to_pci_dev(host->dev);
812 void __iomem *port_mmio;
813 u32 tmp;
814 int mv;
815
816 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
817 if (pdev->device == 0x6121)
818 mv = 2;
819 else
820 mv = 4;
821 port_mmio = __ahci_port_base(hpriv, port_no: mv);
822
823 writel(val: 0, addr: port_mmio + PORT_IRQ_MASK);
824
825 /* clear port IRQ */
826 tmp = readl(addr: port_mmio + PORT_IRQ_STAT);
827 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
828 if (tmp)
829 writel(val: tmp, addr: port_mmio + PORT_IRQ_STAT);
830 }
831
832 ahci_init_controller(host);
833}
834
835static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
836 unsigned long deadline)
837{
838 struct ata_port *ap = link->ap;
839 struct ahci_host_priv *hpriv = ap->host->private_data;
840 bool online;
841 int rc;
842
843 hpriv->stop_engine(ap);
844
845 rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context),
846 deadline, online: &online, NULL);
847
848 hpriv->start_engine(ap);
849
850 /* vt8251 doesn't clear BSY on signature FIS reception,
851 * request follow-up softreset.
852 */
853 return online ? -EAGAIN : rc;
854}
855
856static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
857 unsigned long deadline)
858{
859 struct ata_port *ap = link->ap;
860 struct ahci_port_priv *pp = ap->private_data;
861 struct ahci_host_priv *hpriv = ap->host->private_data;
862 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
863 struct ata_taskfile tf;
864 bool online;
865 int rc;
866
867 hpriv->stop_engine(ap);
868
869 /* clear D2H reception area to properly wait for D2H FIS */
870 ata_tf_init(dev: link->device, tf: &tf);
871 tf.status = ATA_BUSY;
872 ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis);
873
874 rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context),
875 deadline, online: &online, NULL);
876
877 hpriv->start_engine(ap);
878
879 /* The pseudo configuration device on SIMG4726 attached to
880 * ASUS P5W-DH Deluxe doesn't send signature FIS after
881 * hardreset if no device is attached to the first downstream
882 * port && the pseudo device locks up on SRST w/ PMP==0. To
883 * work around this, wait for !BSY only briefly. If BSY isn't
884 * cleared, perform CLO and proceed to IDENTIFY (achieved by
885 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
886 *
887 * Wait for two seconds. Devices attached to downstream port
888 * which can't process the following IDENTIFY after this will
889 * have to be reset again. For most cases, this should
890 * suffice while making probing snappish enough.
891 */
892 if (online) {
893 rc = ata_wait_after_reset(link, deadline: jiffies + 2 * HZ,
894 check_ready: ahci_check_ready);
895 if (rc)
896 ahci_kick_engine(ap);
897 }
898 return rc;
899}
900
901/*
902 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
903 *
904 * It has been observed with some SSDs that the timing of events in the
905 * link synchronization phase can leave the port in a state that can not
906 * be recovered by a SATA-hard-reset alone. The failing signature is
907 * SStatus.DET stuck at 1 ("Device presence detected but Phy
908 * communication not established"). It was found that unloading and
909 * reloading the driver when this problem occurs allows the drive
910 * connection to be recovered (DET advanced to 0x3). The critical
911 * component of reloading the driver is that the port state machines are
912 * reset by bouncing "port enable" in the AHCI PCS configuration
913 * register. So, reproduce that effect by bouncing a port whenever we
914 * see DET==1 after a reset.
915 */
916static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
917 unsigned long deadline)
918{
919 const unsigned int *timing = sata_ehc_deb_timing(ehc: &link->eh_context);
920 struct ata_port *ap = link->ap;
921 struct ahci_port_priv *pp = ap->private_data;
922 struct ahci_host_priv *hpriv = ap->host->private_data;
923 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
924 unsigned long tmo = deadline - jiffies;
925 struct ata_taskfile tf;
926 bool online;
927 int rc, i;
928
929 hpriv->stop_engine(ap);
930
931 for (i = 0; i < 2; i++) {
932 u16 val;
933 u32 sstatus;
934 int port = ap->port_no;
935 struct ata_host *host = ap->host;
936 struct pci_dev *pdev = to_pci_dev(host->dev);
937
938 /* clear D2H reception area to properly wait for D2H FIS */
939 ata_tf_init(dev: link->device, tf: &tf);
940 tf.status = ATA_BUSY;
941 ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis);
942
943 rc = sata_link_hardreset(link, timing, deadline, online: &online,
944 check_ready: ahci_check_ready);
945
946 if (sata_scr_read(link, reg: SCR_STATUS, val: &sstatus) != 0 ||
947 (sstatus & 0xf) != 1)
948 break;
949
950 ata_link_info(link, "avn bounce port%d\n", port);
951
952 pci_read_config_word(dev: pdev, where: 0x92, val: &val);
953 val &= ~(1 << port);
954 pci_write_config_word(dev: pdev, where: 0x92, val);
955 ata_msleep(ap, msecs: 1000);
956 val |= 1 << port;
957 pci_write_config_word(dev: pdev, where: 0x92, val);
958 deadline += tmo;
959 }
960
961 hpriv->start_engine(ap);
962
963 if (online)
964 *class = ahci_dev_classify(ap);
965
966 return rc;
967}
968
969
970#ifdef CONFIG_PM
971static void ahci_pci_disable_interrupts(struct ata_host *host)
972{
973 struct ahci_host_priv *hpriv = host->private_data;
974 void __iomem *mmio = hpriv->mmio;
975 u32 ctl;
976
977 /* AHCI spec rev1.1 section 8.3.3:
978 * Software must disable interrupts prior to requesting a
979 * transition of the HBA to D3 state.
980 */
981 ctl = readl(addr: mmio + HOST_CTL);
982 ctl &= ~HOST_IRQ_EN;
983 writel(val: ctl, addr: mmio + HOST_CTL);
984 readl(addr: mmio + HOST_CTL); /* flush */
985}
986
987static int ahci_pci_device_runtime_suspend(struct device *dev)
988{
989 struct pci_dev *pdev = to_pci_dev(dev);
990 struct ata_host *host = pci_get_drvdata(pdev);
991
992 ahci_pci_disable_interrupts(host);
993 return 0;
994}
995
996static int ahci_pci_device_runtime_resume(struct device *dev)
997{
998 struct pci_dev *pdev = to_pci_dev(dev);
999 struct ata_host *host = pci_get_drvdata(pdev);
1000 int rc;
1001
1002 rc = ahci_pci_reset_controller(host);
1003 if (rc)
1004 return rc;
1005 ahci_pci_init_controller(host);
1006 return 0;
1007}
1008
1009#ifdef CONFIG_PM_SLEEP
1010static int ahci_pci_device_suspend(struct device *dev)
1011{
1012 struct pci_dev *pdev = to_pci_dev(dev);
1013 struct ata_host *host = pci_get_drvdata(pdev);
1014 struct ahci_host_priv *hpriv = host->private_data;
1015
1016 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1017 dev_err(&pdev->dev,
1018 "BIOS update required for suspend/resume\n");
1019 return -EIO;
1020 }
1021
1022 ahci_pci_disable_interrupts(host);
1023 ata_host_suspend(host, PMSG_SUSPEND);
1024 return 0;
1025}
1026
1027static int ahci_pci_device_resume(struct device *dev)
1028{
1029 struct pci_dev *pdev = to_pci_dev(dev);
1030 struct ata_host *host = pci_get_drvdata(pdev);
1031 int rc;
1032
1033 /* Apple BIOS helpfully mangles the registers on resume */
1034 if (is_mcp89_apple(pdev))
1035 ahci_mcp89_apple_enable(pdev);
1036
1037 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1038 rc = ahci_pci_reset_controller(host);
1039 if (rc)
1040 return rc;
1041
1042 ahci_pci_init_controller(host);
1043 }
1044
1045 ata_host_resume(host);
1046
1047 return 0;
1048}
1049#endif
1050
1051#endif /* CONFIG_PM */
1052
1053static int ahci_configure_dma_masks(struct pci_dev *pdev,
1054 struct ahci_host_priv *hpriv)
1055{
1056 int dma_bits;
1057 int rc;
1058
1059 if (hpriv->cap & HOST_CAP_64) {
1060 dma_bits = 64;
1061 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1062 dma_bits = 43;
1063 } else {
1064 dma_bits = 32;
1065 }
1066
1067 /*
1068 * If the device fixup already set the dma_mask to some non-standard
1069 * value, don't extend it here. This happens on STA2X11, for example.
1070 *
1071 * XXX: manipulating the DMA mask from platform code is completely
1072 * bogus, platform code should use dev->bus_dma_limit instead..
1073 */
1074 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1075 return 0;
1076
1077 rc = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(dma_bits));
1078 if (rc)
1079 dev_err(&pdev->dev, "DMA enable failed\n");
1080 return rc;
1081}
1082
1083static void ahci_pci_print_info(struct ata_host *host)
1084{
1085 struct pci_dev *pdev = to_pci_dev(host->dev);
1086 u16 cc;
1087 const char *scc_s;
1088
1089 pci_read_config_word(dev: pdev, where: 0x0a, val: &cc);
1090 if (cc == PCI_CLASS_STORAGE_IDE)
1091 scc_s = "IDE";
1092 else if (cc == PCI_CLASS_STORAGE_SATA)
1093 scc_s = "SATA";
1094 else if (cc == PCI_CLASS_STORAGE_RAID)
1095 scc_s = "RAID";
1096 else
1097 scc_s = "unknown";
1098
1099 ahci_print_info(host, scc_s);
1100}
1101
1102/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1103 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1104 * support PMP and the 4726 either directly exports the device
1105 * attached to the first downstream port or acts as a hardware storage
1106 * controller and emulate a single ATA device (can be RAID 0/1 or some
1107 * other configuration).
1108 *
1109 * When there's no device attached to the first downstream port of the
1110 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1111 * configure the 4726. However, ATA emulation of the device is very
1112 * lame. It doesn't send signature D2H Reg FIS after the initial
1113 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1114 *
1115 * The following function works around the problem by always using
1116 * hardreset on the port and not depending on receiving signature FIS
1117 * afterward. If signature FIS isn't received soon, ATA class is
1118 * assumed without follow-up softreset.
1119 */
1120static void ahci_p5wdh_workaround(struct ata_host *host)
1121{
1122 static const struct dmi_system_id sysids[] = {
1123 {
1124 .ident = "P5W DH Deluxe",
1125 .matches = {
1126 DMI_MATCH(DMI_SYS_VENDOR,
1127 "ASUSTEK COMPUTER INC"),
1128 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1129 },
1130 },
1131 { }
1132 };
1133 struct pci_dev *pdev = to_pci_dev(host->dev);
1134
1135 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1136 dmi_check_system(list: sysids)) {
1137 struct ata_port *ap = host->ports[1];
1138
1139 dev_info(&pdev->dev,
1140 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1141
1142 ap->ops = &ahci_p5wdh_ops;
1143 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1144 }
1145}
1146
1147/*
1148 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1149 * booting in BIOS compatibility mode. We restore the registers but not ID.
1150 */
1151static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1152{
1153 u32 val;
1154
1155 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1156
1157 pci_read_config_dword(dev: pdev, where: 0xf8, val: &val);
1158 val |= 1 << 0x1b;
1159 /* the following changes the device ID, but appears not to affect function */
1160 /* val = (val & ~0xf0000000) | 0x80000000; */
1161 pci_write_config_dword(dev: pdev, where: 0xf8, val);
1162
1163 pci_read_config_dword(dev: pdev, where: 0x54c, val: &val);
1164 val |= 1 << 0xc;
1165 pci_write_config_dword(dev: pdev, where: 0x54c, val);
1166
1167 pci_read_config_dword(dev: pdev, where: 0x4a4, val: &val);
1168 val &= 0xff;
1169 val |= 0x01060100;
1170 pci_write_config_dword(dev: pdev, where: 0x4a4, val);
1171
1172 pci_read_config_dword(dev: pdev, where: 0x54c, val: &val);
1173 val &= ~(1 << 0xc);
1174 pci_write_config_dword(dev: pdev, where: 0x54c, val);
1175
1176 pci_read_config_dword(dev: pdev, where: 0xf8, val: &val);
1177 val &= ~(1 << 0x1b);
1178 pci_write_config_dword(dev: pdev, where: 0xf8, val);
1179}
1180
1181static bool is_mcp89_apple(struct pci_dev *pdev)
1182{
1183 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1184 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1185 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1186 pdev->subsystem_device == 0xcb89;
1187}
1188
1189/* only some SB600 ahci controllers can do 64bit DMA */
1190static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1191{
1192 static const struct dmi_system_id sysids[] = {
1193 /*
1194 * The oldest version known to be broken is 0901 and
1195 * working is 1501 which was released on 2007-10-26.
1196 * Enable 64bit DMA on 1501 and anything newer.
1197 *
1198 * Please read bko#9412 for more info.
1199 */
1200 {
1201 .ident = "ASUS M2A-VM",
1202 .matches = {
1203 DMI_MATCH(DMI_BOARD_VENDOR,
1204 "ASUSTeK Computer INC."),
1205 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1206 },
1207 .driver_data = "20071026", /* yyyymmdd */
1208 },
1209 /*
1210 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1211 * support 64bit DMA.
1212 *
1213 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1214 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1215 * This spelling mistake was fixed in BIOS version 1.5, so
1216 * 1.5 and later have the Manufacturer as
1217 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1218 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1219 *
1220 * BIOS versions earlier than 1.9 had a Board Product Name
1221 * DMI field of "MS-7376". This was changed to be
1222 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1223 * match on DMI_BOARD_NAME of "MS-7376".
1224 */
1225 {
1226 .ident = "MSI K9A2 Platinum",
1227 .matches = {
1228 DMI_MATCH(DMI_BOARD_VENDOR,
1229 "MICRO-STAR INTER"),
1230 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1231 },
1232 },
1233 /*
1234 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1235 * 64bit DMA.
1236 *
1237 * This board also had the typo mentioned above in the
1238 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1239 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1240 */
1241 {
1242 .ident = "MSI K9AGM2",
1243 .matches = {
1244 DMI_MATCH(DMI_BOARD_VENDOR,
1245 "MICRO-STAR INTER"),
1246 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1247 },
1248 },
1249 /*
1250 * All BIOS versions for the Asus M3A support 64bit DMA.
1251 * (all release versions from 0301 to 1206 were tested)
1252 */
1253 {
1254 .ident = "ASUS M3A",
1255 .matches = {
1256 DMI_MATCH(DMI_BOARD_VENDOR,
1257 "ASUSTeK Computer INC."),
1258 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1259 },
1260 },
1261 { }
1262 };
1263 const struct dmi_system_id *match;
1264 int year, month, date;
1265 char buf[9];
1266
1267 match = dmi_first_match(list: sysids);
1268 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1269 !match)
1270 return false;
1271
1272 if (!match->driver_data)
1273 goto enable_64bit;
1274
1275 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1276 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1277
1278 if (strcmp(buf, match->driver_data) >= 0)
1279 goto enable_64bit;
1280 else {
1281 dev_warn(&pdev->dev,
1282 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1283 match->ident);
1284 return false;
1285 }
1286
1287enable_64bit:
1288 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1289 return true;
1290}
1291
1292static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1293{
1294 static const struct dmi_system_id broken_systems[] = {
1295 {
1296 .ident = "HP Compaq nx6310",
1297 .matches = {
1298 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1299 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1300 },
1301 /* PCI slot number of the controller */
1302 .driver_data = (void *)0x1FUL,
1303 },
1304 {
1305 .ident = "HP Compaq 6720s",
1306 .matches = {
1307 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1308 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1309 },
1310 /* PCI slot number of the controller */
1311 .driver_data = (void *)0x1FUL,
1312 },
1313
1314 { } /* terminate list */
1315 };
1316 const struct dmi_system_id *dmi = dmi_first_match(list: broken_systems);
1317
1318 if (dmi) {
1319 unsigned long slot = (unsigned long)dmi->driver_data;
1320 /* apply the quirk only to on-board controllers */
1321 return slot == PCI_SLOT(pdev->devfn);
1322 }
1323
1324 return false;
1325}
1326
1327static bool ahci_broken_suspend(struct pci_dev *pdev)
1328{
1329 static const struct dmi_system_id sysids[] = {
1330 /*
1331 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1332 * to the harddisk doesn't become online after
1333 * resuming from STR. Warn and fail suspend.
1334 *
1335 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1336 *
1337 * Use dates instead of versions to match as HP is
1338 * apparently recycling both product and version
1339 * strings.
1340 *
1341 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1342 */
1343 {
1344 .ident = "dv4",
1345 .matches = {
1346 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1347 DMI_MATCH(DMI_PRODUCT_NAME,
1348 "HP Pavilion dv4 Notebook PC"),
1349 },
1350 .driver_data = "20090105", /* F.30 */
1351 },
1352 {
1353 .ident = "dv5",
1354 .matches = {
1355 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1356 DMI_MATCH(DMI_PRODUCT_NAME,
1357 "HP Pavilion dv5 Notebook PC"),
1358 },
1359 .driver_data = "20090506", /* F.16 */
1360 },
1361 {
1362 .ident = "dv6",
1363 .matches = {
1364 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1365 DMI_MATCH(DMI_PRODUCT_NAME,
1366 "HP Pavilion dv6 Notebook PC"),
1367 },
1368 .driver_data = "20090423", /* F.21 */
1369 },
1370 {
1371 .ident = "HDX18",
1372 .matches = {
1373 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1374 DMI_MATCH(DMI_PRODUCT_NAME,
1375 "HP HDX18 Notebook PC"),
1376 },
1377 .driver_data = "20090430", /* F.23 */
1378 },
1379 /*
1380 * Acer eMachines G725 has the same problem. BIOS
1381 * V1.03 is known to be broken. V3.04 is known to
1382 * work. Between, there are V1.06, V2.06 and V3.03
1383 * that we don't have much idea about. For now,
1384 * assume that anything older than V3.04 is broken.
1385 *
1386 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1387 */
1388 {
1389 .ident = "G725",
1390 .matches = {
1391 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1392 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1393 },
1394 .driver_data = "20091216", /* V3.04 */
1395 },
1396 { } /* terminate list */
1397 };
1398 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1399 int year, month, date;
1400 char buf[9];
1401
1402 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1403 return false;
1404
1405 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1406 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1407
1408 return strcmp(buf, dmi->driver_data) < 0;
1409}
1410
1411static bool ahci_broken_lpm(struct pci_dev *pdev)
1412{
1413 static const struct dmi_system_id sysids[] = {
1414 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1415 {
1416 .matches = {
1417 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1418 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1419 },
1420 .driver_data = "20180406", /* 1.31 */
1421 },
1422 {
1423 .matches = {
1424 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1425 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1426 },
1427 .driver_data = "20180420", /* 1.28 */
1428 },
1429 {
1430 .matches = {
1431 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1432 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1433 },
1434 .driver_data = "20180315", /* 1.33 */
1435 },
1436 {
1437 .matches = {
1438 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1439 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1440 },
1441 /*
1442 * Note date based on release notes, 2.35 has been
1443 * reported to be good, but I've been unable to get
1444 * a hold of the reporter to get the DMI BIOS date.
1445 * TODO: fix this.
1446 */
1447 .driver_data = "20180310", /* 2.35 */
1448 },
1449 { } /* terminate list */
1450 };
1451 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1452 int year, month, date;
1453 char buf[9];
1454
1455 if (!dmi)
1456 return false;
1457
1458 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1459 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1460
1461 return strcmp(buf, dmi->driver_data) < 0;
1462}
1463
1464static bool ahci_broken_online(struct pci_dev *pdev)
1465{
1466#define ENCODE_BUSDEVFN(bus, slot, func) \
1467 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1468 static const struct dmi_system_id sysids[] = {
1469 /*
1470 * There are several gigabyte boards which use
1471 * SIMG5723s configured as hardware RAID. Certain
1472 * 5723 firmware revisions shipped there keep the link
1473 * online but fail to answer properly to SRST or
1474 * IDENTIFY when no device is attached downstream
1475 * causing libata to retry quite a few times leading
1476 * to excessive detection delay.
1477 *
1478 * As these firmwares respond to the second reset try
1479 * with invalid device signature, considering unknown
1480 * sig as offline works around the problem acceptably.
1481 */
1482 {
1483 .ident = "EP45-DQ6",
1484 .matches = {
1485 DMI_MATCH(DMI_BOARD_VENDOR,
1486 "Gigabyte Technology Co., Ltd."),
1487 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1488 },
1489 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1490 },
1491 {
1492 .ident = "EP45-DS5",
1493 .matches = {
1494 DMI_MATCH(DMI_BOARD_VENDOR,
1495 "Gigabyte Technology Co., Ltd."),
1496 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1497 },
1498 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1499 },
1500 { } /* terminate list */
1501 };
1502#undef ENCODE_BUSDEVFN
1503 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1504 unsigned int val;
1505
1506 if (!dmi)
1507 return false;
1508
1509 val = (unsigned long)dmi->driver_data;
1510
1511 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1512}
1513
1514#ifdef CONFIG_ATA_ACPI
1515static void ahci_gtf_filter_workaround(struct ata_host *host)
1516{
1517 static const struct dmi_system_id sysids[] = {
1518 /*
1519 * Aspire 3810T issues a bunch of SATA enable commands
1520 * via _GTF including an invalid one and one which is
1521 * rejected by the device. Among the successful ones
1522 * is FPDMA non-zero offset enable which when enabled
1523 * only on the drive side leads to NCQ command
1524 * failures. Filter it out.
1525 */
1526 {
1527 .ident = "Aspire 3810T",
1528 .matches = {
1529 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1530 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1531 },
1532 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1533 },
1534 { }
1535 };
1536 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1537 unsigned int filter;
1538 int i;
1539
1540 if (!dmi)
1541 return;
1542
1543 filter = (unsigned long)dmi->driver_data;
1544 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1545 filter, dmi->ident);
1546
1547 for (i = 0; i < host->n_ports; i++) {
1548 struct ata_port *ap = host->ports[i];
1549 struct ata_link *link;
1550 struct ata_device *dev;
1551
1552 ata_for_each_link(link, ap, EDGE)
1553 ata_for_each_dev(dev, link, ALL)
1554 dev->gtf_filter |= filter;
1555 }
1556}
1557#else
1558static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1559{}
1560#endif
1561
1562/*
1563 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1564 * as DUMMY, or detected but eventually get a "link down" and never get up
1565 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1566 * port_map may hold a value of 0x00.
1567 *
1568 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1569 * and can significantly reduce the occurrence of the problem.
1570 *
1571 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1572 */
1573static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1574 struct pci_dev *pdev)
1575{
1576 static const struct dmi_system_id sysids[] = {
1577 {
1578 .ident = "Acer Switch Alpha 12",
1579 .matches = {
1580 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1581 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1582 },
1583 },
1584 { }
1585 };
1586
1587 if (dmi_check_system(list: sysids)) {
1588 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1589 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1590 hpriv->port_map = 0x7;
1591 hpriv->cap = 0xC734FF02;
1592 }
1593 }
1594}
1595
1596#ifdef CONFIG_ARM64
1597/*
1598 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1599 * Workaround is to make sure all pending IRQs are served before leaving
1600 * handler.
1601 */
1602static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1603{
1604 struct ata_host *host = dev_instance;
1605 struct ahci_host_priv *hpriv;
1606 unsigned int rc = 0;
1607 void __iomem *mmio;
1608 u32 irq_stat, irq_masked;
1609 unsigned int handled = 1;
1610
1611 hpriv = host->private_data;
1612 mmio = hpriv->mmio;
1613 irq_stat = readl(mmio + HOST_IRQ_STAT);
1614 if (!irq_stat)
1615 return IRQ_NONE;
1616
1617 do {
1618 irq_masked = irq_stat & hpriv->port_map;
1619 spin_lock(&host->lock);
1620 rc = ahci_handle_port_intr(host, irq_masked);
1621 if (!rc)
1622 handled = 0;
1623 writel(irq_stat, mmio + HOST_IRQ_STAT);
1624 irq_stat = readl(mmio + HOST_IRQ_STAT);
1625 spin_unlock(&host->lock);
1626 } while (irq_stat);
1627
1628 return IRQ_RETVAL(handled);
1629}
1630#endif
1631
1632static void ahci_remap_check(struct pci_dev *pdev, int bar,
1633 struct ahci_host_priv *hpriv)
1634{
1635 int i;
1636 u32 cap;
1637
1638 /*
1639 * Check if this device might have remapped nvme devices.
1640 */
1641 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1642 pci_resource_len(pdev, bar) < SZ_512K ||
1643 bar != AHCI_PCI_BAR_STANDARD ||
1644 !(readl(addr: hpriv->mmio + AHCI_VSCAP) & 1))
1645 return;
1646
1647 cap = readq(addr: hpriv->mmio + AHCI_REMAP_CAP);
1648 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1649 if ((cap & (1 << i)) == 0)
1650 continue;
1651 if (readl(addr: hpriv->mmio + ahci_remap_dcc(i))
1652 != PCI_CLASS_STORAGE_EXPRESS)
1653 continue;
1654
1655 /* We've found a remapped device */
1656 hpriv->remapped_nvme++;
1657 }
1658
1659 if (!hpriv->remapped_nvme)
1660 return;
1661
1662 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1663 hpriv->remapped_nvme);
1664 dev_warn(&pdev->dev,
1665 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1666
1667 /*
1668 * Don't rely on the msi-x capability in the remap case,
1669 * share the legacy interrupt across ahci and remapped devices.
1670 */
1671 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1672}
1673
1674static int ahci_get_irq_vector(struct ata_host *host, int port)
1675{
1676 return pci_irq_vector(to_pci_dev(host->dev), nr: port);
1677}
1678
1679static void ahci_init_irq(struct pci_dev *pdev, unsigned int n_ports,
1680 struct ahci_host_priv *hpriv)
1681{
1682 int nvec;
1683
1684 if (hpriv->flags & AHCI_HFLAG_NO_MSI) {
1685 pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_INTX);
1686 return;
1687 }
1688
1689 /*
1690 * If number of MSIs is less than number of ports then Sharing Last
1691 * Message mode could be enforced. In this case assume that advantage
1692 * of multiple MSIs is negated and use single MSI mode instead.
1693 */
1694 if (n_ports > 1) {
1695 nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: n_ports, INT_MAX,
1696 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1697 if (nvec > 0) {
1698 if (!(readl(addr: hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1699 hpriv->get_irq_vector = ahci_get_irq_vector;
1700 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1701 return;
1702 }
1703
1704 /*
1705 * Fallback to single MSI mode if the controller
1706 * enforced MRSM mode.
1707 */
1708 printk(KERN_INFO
1709 "ahci: MRSM is on, fallback to single MSI\n");
1710 pci_free_irq_vectors(dev: pdev);
1711 }
1712 }
1713
1714 /*
1715 * If the host is not capable of supporting per-port vectors, fall
1716 * back to single MSI before finally attempting single MSI-X or
1717 * a legacy INTx.
1718 */
1719 nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSI);
1720 if (nvec == 1)
1721 return;
1722 pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSIX | PCI_IRQ_INTX);
1723}
1724
1725static void ahci_mark_external_port(struct ata_port *ap)
1726{
1727 struct ahci_host_priv *hpriv = ap->host->private_data;
1728 void __iomem *port_mmio = ahci_port_base(ap);
1729 u32 tmp;
1730
1731 /* mark external ports (hotplug-capable, eSATA) */
1732 tmp = readl(addr: port_mmio + PORT_CMD);
1733 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
1734 (tmp & PORT_CMD_HPCP))
1735 ap->pflags |= ATA_PFLAG_EXTERNAL;
1736}
1737
1738static void ahci_update_initial_lpm_policy(struct ata_port *ap)
1739{
1740 struct ahci_host_priv *hpriv = ap->host->private_data;
1741 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1742
1743 /*
1744 * AHCI contains a known incompatibility between LPM and hot-plug
1745 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
1746 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
1747 * LPM if the port advertises itself as an external port.
1748 */
1749 if (ap->pflags & ATA_PFLAG_EXTERNAL) {
1750 ata_port_dbg(ap, "external port, not enabling LPM\n");
1751 return;
1752 }
1753
1754 /* If no LPM states are supported by the HBA, do not bother with LPM */
1755 if ((ap->host->flags & ATA_HOST_NO_PART) &&
1756 (ap->host->flags & ATA_HOST_NO_SSC) &&
1757 (ap->host->flags & ATA_HOST_NO_DEVSLP)) {
1758 ata_port_dbg(ap, "no LPM states supported, not enabling LPM\n");
1759 return;
1760 }
1761
1762 /* user modified policy via module param */
1763 if (mobile_lpm_policy != -1) {
1764 policy = mobile_lpm_policy;
1765 goto update_policy;
1766 }
1767
1768 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1769 if (hpriv->cap & HOST_CAP_PART)
1770 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1771 else if (hpriv->cap & HOST_CAP_SSC)
1772 policy = ATA_LPM_MIN_POWER;
1773 }
1774
1775update_policy:
1776 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1777 ap->target_lpm_policy = policy;
1778}
1779
1780static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1781{
1782 u16 tmp16;
1783
1784 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
1785 return;
1786
1787 /*
1788 * port_map is determined from PORTS_IMPL PCI register which is
1789 * implemented as write or write-once register. If the register
1790 * isn't programmed, ahci automatically generates it from number
1791 * of ports, which is good enough for PCS programming. It is
1792 * otherwise expected that platform firmware enables the ports
1793 * before the OS boots.
1794 */
1795 pci_read_config_word(dev: pdev, where: PCS_6, val: &tmp16);
1796 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1797 tmp16 |= hpriv->port_map;
1798 pci_write_config_word(dev: pdev, where: PCS_6, val: tmp16);
1799 }
1800}
1801
1802static ssize_t remapped_nvme_show(struct device *dev,
1803 struct device_attribute *attr,
1804 char *buf)
1805{
1806 struct ata_host *host = dev_get_drvdata(dev);
1807 struct ahci_host_priv *hpriv = host->private_data;
1808
1809 return sysfs_emit(buf, fmt: "%u\n", hpriv->remapped_nvme);
1810}
1811
1812static DEVICE_ATTR_RO(remapped_nvme);
1813
1814static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1815{
1816 unsigned int board_id = ent->driver_data;
1817 struct ata_port_info pi = ahci_port_info[board_id];
1818 const struct ata_port_info *ppi[] = { &pi, NULL };
1819 struct device *dev = &pdev->dev;
1820 struct ahci_host_priv *hpriv;
1821 struct ata_host *host;
1822 int n_ports, i, rc;
1823 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1824
1825 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1826
1827 ata_print_version_once(dev: &pdev->dev, DRV_VERSION);
1828
1829 /* The AHCI driver can only drive the SATA ports, the PATA driver
1830 can drive them all so if both drivers are selected make sure
1831 AHCI stays out of the way */
1832 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1833 return -ENODEV;
1834
1835 /* Apple BIOS on MCP89 prevents us using AHCI */
1836 if (is_mcp89_apple(pdev))
1837 ahci_mcp89_apple_enable(pdev);
1838
1839 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1840 * At the moment, we can only use the AHCI mode. Let the users know
1841 * that for SAS drives they're out of luck.
1842 */
1843 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1844 dev_info(&pdev->dev,
1845 "PDC42819 can only drive SATA devices with this driver\n");
1846
1847 /* Some devices use non-standard BARs */
1848 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1849 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1850 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1851 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1852 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1853 if (pdev->device == 0xa01c)
1854 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1855 if (pdev->device == 0xa084)
1856 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1857 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1858 if (pdev->device == 0x7a08)
1859 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1860 }
1861
1862 /* acquire resources */
1863 rc = pcim_enable_device(pdev);
1864 if (rc)
1865 return rc;
1866
1867 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1868 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1869 u8 map;
1870
1871 /* ICH6s share the same PCI ID for both piix and ahci
1872 * modes. Enabling ahci mode while MAP indicates
1873 * combined mode is a bad idea. Yield to ata_piix.
1874 */
1875 pci_read_config_byte(dev: pdev, where: ICH_MAP, val: &map);
1876 if (map & 0x3) {
1877 dev_info(&pdev->dev,
1878 "controller is in combined mode, can't enable AHCI mode\n");
1879 return -ENODEV;
1880 }
1881 }
1882
1883 /* AHCI controllers often implement SFF compatible interface.
1884 * Grab all PCI BARs just in case.
1885 */
1886 rc = pcim_request_all_regions(pdev, DRV_NAME);
1887 if (rc == -EBUSY)
1888 pcim_pin_device(pdev);
1889 if (rc)
1890 return rc;
1891
1892 hpriv = devm_kzalloc(dev, size: sizeof(*hpriv), GFP_KERNEL);
1893 if (!hpriv)
1894 return -ENOMEM;
1895 hpriv->flags |= (unsigned long)pi.private_data;
1896
1897 /* MCP65 revision A1 and A2 can't do MSI */
1898 if (board_id == board_ahci_mcp65 &&
1899 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1900 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1901
1902 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1903 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1904 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1905
1906 /* only some SB600s can do 64bit DMA */
1907 if (ahci_sb600_enable_64bit(pdev))
1908 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1909
1910 hpriv->mmio = pcim_iomap(pdev, bar: ahci_pci_bar, maxlen: 0);
1911 if (!hpriv->mmio)
1912 return -ENOMEM;
1913
1914 /* detect remapped nvme devices */
1915 ahci_remap_check(pdev, bar: ahci_pci_bar, hpriv);
1916
1917 sysfs_add_file_to_group(kobj: &pdev->dev.kobj,
1918 attr: &dev_attr_remapped_nvme.attr,
1919 NULL);
1920
1921#ifdef CONFIG_ARM64
1922 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1923 pdev->device == 0xa235 &&
1924 pdev->revision < 0x30)
1925 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1926
1927 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1928 hpriv->irq_handler = ahci_thunderx_irq_handler;
1929#endif
1930
1931 /* save initial config */
1932 ahci_pci_save_initial_config(pdev, hpriv);
1933
1934 /* prepare host */
1935 if (hpriv->cap & HOST_CAP_NCQ) {
1936 pi.flags |= ATA_FLAG_NCQ;
1937 /*
1938 * Auto-activate optimization is supposed to be
1939 * supported on all AHCI controllers indicating NCQ
1940 * capability, but it seems to be broken on some
1941 * chipsets including NVIDIAs.
1942 */
1943 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1944 pi.flags |= ATA_FLAG_FPDMA_AA;
1945
1946 /*
1947 * All AHCI controllers should be forward-compatible
1948 * with the new auxiliary field. This code should be
1949 * conditionalized if any buggy AHCI controllers are
1950 * encountered.
1951 */
1952 pi.flags |= ATA_FLAG_FPDMA_AUX;
1953 }
1954
1955 if (hpriv->cap & HOST_CAP_PMP)
1956 pi.flags |= ATA_FLAG_PMP;
1957
1958 ahci_set_em_messages(hpriv, pi: &pi);
1959
1960 if (ahci_broken_system_poweroff(pdev)) {
1961 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1962 dev_info(&pdev->dev,
1963 "quirky BIOS, skipping spindown on poweroff\n");
1964 }
1965
1966 if (ahci_broken_lpm(pdev)) {
1967 pi.flags |= ATA_FLAG_NO_LPM;
1968 dev_warn(&pdev->dev,
1969 "BIOS update required for Link Power Management support\n");
1970 }
1971
1972 if (ahci_broken_suspend(pdev)) {
1973 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1974 dev_warn(&pdev->dev,
1975 "BIOS update required for suspend/resume\n");
1976 }
1977
1978 if (ahci_broken_online(pdev)) {
1979 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1980 dev_info(&pdev->dev,
1981 "online status unreliable, applying workaround\n");
1982 }
1983
1984
1985 /* Acer SA5-271 workaround modifies private_data */
1986 acer_sa5_271_workaround(hpriv, pdev);
1987
1988 /* CAP.NP sometimes indicate the index of the last enabled
1989 * port, at other times, that of the last possible port, so
1990 * determining the maximum port number requires looking at
1991 * both CAP.NP and port_map.
1992 */
1993 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1994
1995 host = ata_host_alloc_pinfo(dev: &pdev->dev, ppi, n_ports);
1996 if (!host) {
1997 rc = -ENOMEM;
1998 goto err_rm_sysfs_file;
1999 }
2000 host->private_data = hpriv;
2001
2002 ahci_init_irq(pdev, n_ports, hpriv);
2003
2004 hpriv->irq = pci_irq_vector(dev: pdev, nr: 0);
2005
2006 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
2007 host->flags |= ATA_HOST_PARALLEL_SCAN;
2008 else
2009 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
2010
2011 if (!(hpriv->cap & HOST_CAP_PART))
2012 host->flags |= ATA_HOST_NO_PART;
2013
2014 if (!(hpriv->cap & HOST_CAP_SSC))
2015 host->flags |= ATA_HOST_NO_SSC;
2016
2017 if (!(hpriv->cap2 & HOST_CAP2_SDS))
2018 host->flags |= ATA_HOST_NO_DEVSLP;
2019
2020 if (pi.flags & ATA_FLAG_EM)
2021 ahci_reset_em(host);
2022
2023 for (i = 0; i < host->n_ports; i++) {
2024 struct ata_port *ap = host->ports[i];
2025
2026 ata_port_pbar_desc(ap, bar: ahci_pci_bar, offset: -1, name: "abar");
2027 ata_port_pbar_desc(ap, bar: ahci_pci_bar,
2028 offset: 0x100 + ap->port_no * 0x80, name: "port");
2029
2030 /* set enclosure management message type */
2031 if (ap->flags & ATA_FLAG_EM)
2032 ap->em_message_type = hpriv->em_msg_type;
2033
2034 ahci_mark_external_port(ap);
2035
2036 ahci_update_initial_lpm_policy(ap);
2037
2038 /* disabled/not-implemented port */
2039 if (!(hpriv->port_map & (1 << i)))
2040 ap->ops = &ata_dummy_port_ops;
2041 }
2042
2043 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2044 ahci_p5wdh_workaround(host);
2045
2046 /* apply gtf filter quirk */
2047 ahci_gtf_filter_workaround(host);
2048
2049 /* initialize adapter */
2050 rc = ahci_configure_dma_masks(pdev, hpriv);
2051 if (rc)
2052 goto err_rm_sysfs_file;
2053
2054 rc = ahci_pci_reset_controller(host);
2055 if (rc)
2056 goto err_rm_sysfs_file;
2057
2058 ahci_pci_init_controller(host);
2059 ahci_pci_print_info(host);
2060
2061 pci_set_master(dev: pdev);
2062
2063 rc = ahci_host_activate(host, sht: &ahci_sht);
2064 if (rc)
2065 goto err_rm_sysfs_file;
2066
2067 pm_runtime_put_noidle(dev: &pdev->dev);
2068 return 0;
2069
2070err_rm_sysfs_file:
2071 sysfs_remove_file_from_group(kobj: &pdev->dev.kobj,
2072 attr: &dev_attr_remapped_nvme.attr, NULL);
2073 return rc;
2074}
2075
2076static void ahci_shutdown_one(struct pci_dev *pdev)
2077{
2078 ata_pci_shutdown_one(pdev);
2079}
2080
2081static void ahci_remove_one(struct pci_dev *pdev)
2082{
2083 sysfs_remove_file_from_group(kobj: &pdev->dev.kobj,
2084 attr: &dev_attr_remapped_nvme.attr,
2085 NULL);
2086 pm_runtime_get_noresume(dev: &pdev->dev);
2087 ata_pci_remove_one(pdev);
2088}
2089
2090module_pci_driver(ahci_pci_driver);
2091
2092MODULE_AUTHOR("Jeff Garzik");
2093MODULE_DESCRIPTION("AHCI SATA low-level driver");
2094MODULE_LICENSE("GPL");
2095MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2096MODULE_VERSION(DRV_VERSION);
2097

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source code of linux/drivers/ata/ahci.c