1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> |
4 | */ |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/platform_device.h> |
8 | |
9 | #include "clk-gate.h" |
10 | #include "clk-mtk.h" |
11 | |
12 | #include <dt-bindings/clock/mediatek,mt6735-imgsys.h> |
13 | |
14 | #define IMG_CG_CON 0x00 |
15 | #define IMG_CG_SET 0x04 |
16 | #define IMG_CG_CLR 0x08 |
17 | |
18 | static struct mtk_gate_regs imgsys_cg_regs = { |
19 | .set_ofs = IMG_CG_SET, |
20 | .clr_ofs = IMG_CG_CLR, |
21 | .sta_ofs = IMG_CG_CON, |
22 | }; |
23 | |
24 | static const struct mtk_gate imgsys_gates[] = { |
25 | GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2" , "mm_sel" , &imgsys_cg_regs, 0, &mtk_clk_gate_ops_setclr), |
26 | GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi" , "mm_sel" , &imgsys_cg_regs, 5, &mtk_clk_gate_ops_setclr), |
27 | GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam" , "mm_sel" , &imgsys_cg_regs, 6, &mtk_clk_gate_ops_setclr), |
28 | GATE_MTK(CLK_IMG_SEN_TG, "sen_tg" , "mm_sel" , &imgsys_cg_regs, 7, &mtk_clk_gate_ops_setclr), |
29 | GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam" , "mm_sel" , &imgsys_cg_regs, 8, &mtk_clk_gate_ops_setclr), |
30 | GATE_MTK(CLK_IMG_CAM_SV, "cam_sv" , "mm_sel" , &imgsys_cg_regs, 9, &mtk_clk_gate_ops_setclr), |
31 | GATE_MTK(CLK_IMG_SUFOD, "sufod" , "mm_sel" , &imgsys_cg_regs, 10, &mtk_clk_gate_ops_setclr), |
32 | GATE_MTK(CLK_IMG_FD, "fd" , "mm_sel" , &imgsys_cg_regs, 11, &mtk_clk_gate_ops_setclr), |
33 | }; |
34 | |
35 | static const struct mtk_clk_desc imgsys_clks = { |
36 | .clks = imgsys_gates, |
37 | .num_clks = ARRAY_SIZE(imgsys_gates), |
38 | }; |
39 | |
40 | static const struct of_device_id of_match_mt6735_imgsys[] = { |
41 | { .compatible = "mediatek,mt6735-imgsys" , .data = &imgsys_clks }, |
42 | { /* sentinel */ } |
43 | }; |
44 | |
45 | static struct platform_driver clk_mt6735_imgsys = { |
46 | .probe = mtk_clk_simple_probe, |
47 | .remove = mtk_clk_simple_remove, |
48 | .driver = { |
49 | .name = "clk-mt6735-imgsys" , |
50 | .of_match_table = of_match_mt6735_imgsys, |
51 | }, |
52 | }; |
53 | module_platform_driver(clk_mt6735_imgsys); |
54 | |
55 | MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>" ); |
56 | MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver" ); |
57 | MODULE_LICENSE("GPL" ); |
58 | |