1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2018 MediaTek Inc. |
4 | * Author: Owen Chen <owen.chen@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/platform_device.h> |
9 | |
10 | #include "clk-mtk.h" |
11 | #include "clk-gate.h" |
12 | |
13 | #include <dt-bindings/clock/mt6765-clk.h> |
14 | |
15 | static const struct mtk_gate_regs mipi0a_cg_regs = { |
16 | .set_ofs = 0x80, |
17 | .clr_ofs = 0x80, |
18 | .sta_ofs = 0x80, |
19 | }; |
20 | |
21 | #define GATE_MIPI0A(_id, _name, _parent, _shift) \ |
22 | GATE_MTK(_id, _name, _parent, &mipi0a_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
23 | |
24 | static const struct mtk_gate mipi0a_clks[] = { |
25 | GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A, |
26 | "mipi0a_csr_0a" , "f_fseninf_ck" , 1), |
27 | }; |
28 | |
29 | static const struct mtk_clk_desc mipi0a_desc = { |
30 | .clks = mipi0a_clks, |
31 | .num_clks = ARRAY_SIZE(mipi0a_clks), |
32 | }; |
33 | |
34 | static const struct of_device_id of_match_clk_mt6765_mipi0a[] = { |
35 | { |
36 | .compatible = "mediatek,mt6765-mipi0a" , |
37 | .data = &mipi0a_desc, |
38 | }, { |
39 | /* sentinel */ |
40 | } |
41 | }; |
42 | MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mipi0a); |
43 | |
44 | static struct platform_driver clk_mt6765_mipi0a_drv = { |
45 | .probe = mtk_clk_simple_probe, |
46 | .remove_new = mtk_clk_simple_remove, |
47 | .driver = { |
48 | .name = "clk-mt6765-mipi0a" , |
49 | .of_match_table = of_match_clk_mt6765_mipi0a, |
50 | }, |
51 | }; |
52 | module_platform_driver(clk_mt6765_mipi0a_drv); |
53 | MODULE_LICENSE("GPL" ); |
54 | |