| 1 | // SPDX-License-Identifier: GPL-2.0-only |
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| 2 | /* |
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| 3 | * Copyright (c) 2022 Collabora Ltd. |
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| 4 | * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #include <dt-bindings/clock/mediatek,mt6795-clk.h> |
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| 8 | #include <linux/module.h> |
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| 9 | #include <linux/platform_device.h> |
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| 10 | #include "clk-gate.h" |
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| 11 | #include "clk-mtk.h" |
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| 12 | |
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| 13 | static const struct mtk_gate_regs mfg_cg_regs = { |
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| 14 | .set_ofs = 0x4, |
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| 15 | .clr_ofs = 0x8, |
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| 16 | .sta_ofs = 0x0, |
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| 17 | }; |
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| 18 | |
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| 19 | #define GATE_MFG(_id, _name, _parent, _shift) \ |
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| 20 | GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
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| 21 | |
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| 22 | static const struct mtk_gate mfg_clks[] = { |
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| 23 | GATE_MFG(CLK_MFG_BAXI, "mfg_baxi" , "axi_mfg_in_sel" , 0), |
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| 24 | GATE_MFG(CLK_MFG_BMEM, "mfg_bmem" , "mem_mfg_in_sel" , 1), |
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| 25 | GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d" , "mfg_sel" , 2), |
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| 26 | GATE_MFG(CLK_MFG_B26M, "mfg_b26m" , "clk26m" , 3), |
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| 27 | }; |
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| 28 | |
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| 29 | static const struct mtk_clk_desc mfg_desc = { |
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| 30 | .clks = mfg_clks, |
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| 31 | .num_clks = ARRAY_SIZE(mfg_clks), |
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| 32 | }; |
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| 33 | |
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| 34 | static const struct of_device_id of_match_clk_mt6795_mfg[] = { |
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| 35 | { .compatible = "mediatek,mt6795-mfgcfg" , .data = &mfg_desc }, |
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| 36 | { /* sentinel */ } |
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| 37 | }; |
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| 38 | MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_mfg); |
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| 39 | |
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| 40 | static struct platform_driver clk_mt6795_mfg_drv = { |
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| 41 | .driver = { |
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| 42 | .name = "clk-mt6795-mfg" , |
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| 43 | .of_match_table = of_match_clk_mt6795_mfg, |
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| 44 | }, |
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| 45 | .probe = mtk_clk_simple_probe, |
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| 46 | .remove_new = mtk_clk_simple_remove, |
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| 47 | }; |
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| 48 | module_platform_driver(clk_mt6795_mfg_drv); |
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| 49 | |
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| 50 | MODULE_DESCRIPTION("MediaTek MT6795 mfg clocks driver" ); |
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| 51 | MODULE_LICENSE("GPL" ); |
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| 52 | |
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