1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2022 Collabora Ltd. |
4 | * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
5 | */ |
6 | |
7 | #include <dt-bindings/clock/mediatek,mt6795-clk.h> |
8 | #include <linux/module.h> |
9 | #include <linux/platform_device.h> |
10 | #include "clk-gate.h" |
11 | #include "clk-mtk.h" |
12 | #include "clk-mux.h" |
13 | |
14 | /* |
15 | * For some clocks, we don't care what their actual rates are. And these |
16 | * clocks may change their rate on different products or different scenarios. |
17 | * So we model these clocks' rate as 0, to denote it's not an actual rate. |
18 | */ |
19 | #define DUMMY_RATE 0 |
20 | |
21 | #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ |
22 | MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \ |
23 | (_reg + 0x4), (_reg + 0x8), _shift, _width, \ |
24 | _gate, 0, -1, _flags) |
25 | |
26 | #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ |
27 | TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \ |
28 | _gate, CLK_SET_RATE_PARENT | _flags) |
29 | |
30 | static DEFINE_SPINLOCK(mt6795_top_clk_lock); |
31 | |
32 | static const char * const aud_1_parents[] = { |
33 | "clk26m" , |
34 | "apll1_ck" , |
35 | "univpll2_d4" , |
36 | "univpll2_d8" |
37 | }; |
38 | |
39 | static const char * const aud_2_parents[] = { |
40 | "clk26m" , |
41 | "apll2_ck" , |
42 | "univpll2_d4" , |
43 | "univpll2_d8" |
44 | }; |
45 | |
46 | static const char * const aud_intbus_parents[] = { |
47 | "clk26m" , |
48 | "syspll1_d4" , |
49 | "syspll4_d2" , |
50 | "univpll3_d2" , |
51 | "univpll2_d8" , |
52 | "dmpll_d4" , |
53 | "dmpll_d8" |
54 | }; |
55 | |
56 | static const char * const audio_parents[] = { |
57 | "clk26m" , |
58 | "syspll3_d4" , |
59 | "syspll4_d4" , |
60 | "syspll1_d16" |
61 | }; |
62 | |
63 | static const char * const axi_mfg_in_parents[] = { |
64 | "clk26m" , |
65 | "axi_sel" , |
66 | "dmpll_d2" |
67 | }; |
68 | |
69 | static const char * const axi_parents[] = { |
70 | "clk26m" , |
71 | "syspll1_d2" , |
72 | "syspll_d5" , |
73 | "syspll1_d4" , |
74 | "univpll_d5" , |
75 | "univpll2_d2" , |
76 | "dmpll_d2" , |
77 | "dmpll_d4" |
78 | }; |
79 | |
80 | static const char * const camtg_parents[] = { |
81 | "clk26m" , |
82 | "univpll_d26" , |
83 | "univpll2_d2" , |
84 | "syspll3_d2" , |
85 | "syspll3_d4" , |
86 | "univpll1_d4" , |
87 | "dmpll_d8" |
88 | }; |
89 | |
90 | static const char * const cci400_parents[] = { |
91 | "clk26m" , |
92 | "vencpll_ck" , |
93 | "clk26m" , |
94 | "clk26m" , |
95 | "univpll_d2" , |
96 | "syspll_d2" , |
97 | "msdcpll_ck" , |
98 | "dmpll_ck" |
99 | }; |
100 | |
101 | static const char * const ddrphycfg_parents[] = { |
102 | "clk26m" , |
103 | "syspll1_d8" |
104 | }; |
105 | |
106 | static const char * const dpi0_parents[] = { |
107 | "clk26m" , |
108 | "tvdpll_d2" , |
109 | "tvdpll_d4" , |
110 | "clk26m" , |
111 | "clk26m" , |
112 | "tvdpll_d8" , |
113 | "tvdpll_d16" |
114 | }; |
115 | |
116 | static const char * const i2s0_m_ck_parents[] = { |
117 | "apll1_div1" , |
118 | "apll2_div1" |
119 | }; |
120 | |
121 | static const char * const i2s1_m_ck_parents[] = { |
122 | "apll1_div2" , |
123 | "apll2_div2" |
124 | }; |
125 | |
126 | static const char * const i2s2_m_ck_parents[] = { |
127 | "apll1_div3" , |
128 | "apll2_div3" |
129 | }; |
130 | |
131 | static const char * const i2s3_m_ck_parents[] = { |
132 | "apll1_div4" , |
133 | "apll2_div4" |
134 | }; |
135 | |
136 | static const char * const i2s3_b_ck_parents[] = { |
137 | "apll1_div5" , |
138 | "apll2_div5" |
139 | }; |
140 | |
141 | static const char * const irda_parents[] = { |
142 | "clk26m" , |
143 | "univpll2_d4" , |
144 | "syspll2_d4" , |
145 | "dmpll_d8" , |
146 | }; |
147 | |
148 | static const char * const mem_mfg_in_parents[] = { |
149 | "clk26m" , |
150 | "mmpll_ck" , |
151 | "dmpll_ck" |
152 | }; |
153 | |
154 | static const char * const mem_parents[] = { |
155 | "clk26m" , |
156 | "dmpll_ck" |
157 | }; |
158 | |
159 | static const char * const mfg_parents[] = { |
160 | "clk26m" , |
161 | "mmpll_ck" , |
162 | "dmpll_ck" , |
163 | "clk26m" , |
164 | "clk26m" , |
165 | "clk26m" , |
166 | "clk26m" , |
167 | "clk26m" , |
168 | "clk26m" , |
169 | "syspll_d3" , |
170 | "syspll1_d2" , |
171 | "syspll_d5" , |
172 | "univpll_d3" , |
173 | "univpll1_d2" , |
174 | "univpll_d5" , |
175 | "univpll2_d2" |
176 | }; |
177 | |
178 | static const char * const mm_parents[] = { |
179 | "clk26m" , |
180 | "vencpll_d2" , |
181 | "syspll_d3" , |
182 | "syspll1_d2" , |
183 | "syspll_d5" , |
184 | "syspll1_d4" , |
185 | "univpll1_d2" , |
186 | "univpll2_d2" , |
187 | "dmpll_d2" |
188 | }; |
189 | |
190 | static const char * const mjc_parents[] = { |
191 | "clk26m" , |
192 | "univpll_d3" , |
193 | "vcodecpll_ck" , |
194 | "tvdpll_445p5m" , |
195 | "vencpll_d2" , |
196 | "syspll_d3" , |
197 | "univpll1_d2" , |
198 | "syspll_d5" , |
199 | "syspll1_d2" , |
200 | "univpll_d5" , |
201 | "univpll2_d2" , |
202 | "dmpll_ck" |
203 | }; |
204 | |
205 | static const char * const msdc50_0_h_parents[] = { |
206 | "clk26m" , |
207 | "syspll1_d2" , |
208 | "syspll2_d2" , |
209 | "syspll4_d2" , |
210 | "univpll_d5" , |
211 | "univpll1_d4" |
212 | }; |
213 | |
214 | static const char * const msdc50_0_parents[] = { |
215 | "clk26m" , |
216 | "msdcpll_ck" , |
217 | "msdcpll_d2" , |
218 | "univpll1_d4" , |
219 | "syspll2_d2" , |
220 | "syspll_d7" , |
221 | "msdcpll_d4" , |
222 | "vencpll_d4" , |
223 | "tvdpll_ck" , |
224 | "univpll_d2" , |
225 | "univpll1_d2" , |
226 | "mmpll_ck" |
227 | }; |
228 | |
229 | static const char * const msdc30_1_parents[] = { |
230 | "clk26m" , |
231 | "univpll2_d2" , |
232 | "msdcpll_d4" , |
233 | "univpll1_d4" , |
234 | "syspll2_d2" , |
235 | "syspll_d7" , |
236 | "univpll_d7" , |
237 | "vencpll_d4" |
238 | }; |
239 | |
240 | static const char * const msdc30_2_parents[] = { |
241 | "clk26m" , |
242 | "univpll2_d2" , |
243 | "msdcpll_d4" , |
244 | "univpll1_d4" , |
245 | "syspll2_d2" , |
246 | "syspll_d7" , |
247 | "univpll_d7" , |
248 | "vencpll_d2" |
249 | }; |
250 | |
251 | static const char * const msdc30_3_parents[] = { |
252 | "clk26m" , |
253 | "univpll2_d2" , |
254 | "msdcpll_d4" , |
255 | "univpll1_d4" , |
256 | "syspll2_d2" , |
257 | "syspll_d7" , |
258 | "univpll_d7" , |
259 | "vencpll_d4" |
260 | }; |
261 | |
262 | static const char * const pmicspi_parents[] = { |
263 | "clk26m" , |
264 | "syspll1_d8" , |
265 | "syspll3_d4" , |
266 | "syspll1_d16" , |
267 | "univpll3_d4" , |
268 | "univpll_d26" , |
269 | "dmpll_d8" , |
270 | "dmpll_d16" |
271 | }; |
272 | |
273 | static const char * const pwm_parents[] = { |
274 | "clk26m" , |
275 | "univpll2_d4" , |
276 | "univpll3_d2" , |
277 | "univpll1_d4" |
278 | }; |
279 | |
280 | static const char * const scam_parents[] = { |
281 | "clk26m" , |
282 | "syspll3_d2" , |
283 | "univpll2_d4" , |
284 | "dmpll_d4" |
285 | }; |
286 | |
287 | static const char * const scp_parents[] = { |
288 | "clk26m" , |
289 | "syspll1_d2" , |
290 | "univpll_d5" , |
291 | "syspll_d5" , |
292 | "dmpll_d2" , |
293 | "dmpll_d4" |
294 | }; |
295 | |
296 | static const char * const spi_parents[] = { |
297 | "clk26m" , |
298 | "syspll3_d2" , |
299 | "syspll1_d4" , |
300 | "syspll4_d2" , |
301 | "univpll3_d2" , |
302 | "univpll2_d4" , |
303 | "univpll1_d8" |
304 | }; |
305 | |
306 | static const char * const uart_parents[] = { |
307 | "clk26m" , |
308 | "univpll2_d8" |
309 | }; |
310 | |
311 | static const char * const usb20_parents[] = { |
312 | "clk26m" , |
313 | "univpll1_d8" , |
314 | "univpll3_d4" |
315 | }; |
316 | |
317 | static const char * const usb30_parents[] = { |
318 | "clk26m" , |
319 | "univpll3_d2" , |
320 | "usb_syspll_125m" , |
321 | "univpll2_d4" |
322 | }; |
323 | |
324 | static const char * const vdec_parents[] = { |
325 | "clk26m" , |
326 | "vcodecpll_ck" , |
327 | "tvdpll_445p5m" , |
328 | "univpll_d3" , |
329 | "vencpll_d2" , |
330 | "syspll_d3" , |
331 | "univpll1_d2" , |
332 | "mmpll_d2" , |
333 | "dmpll_d2" , |
334 | "dmpll_d4" |
335 | }; |
336 | |
337 | static const char * const venc_parents[] = { |
338 | "clk26m" , |
339 | "vcodecpll_ck" , |
340 | "tvdpll_445p5m" , |
341 | "univpll_d3" , |
342 | "vencpll_d2" , |
343 | "syspll_d3" , |
344 | "univpll1_d2" , |
345 | "univpll2_d2" , |
346 | "dmpll_d2" , |
347 | "dmpll_d4" |
348 | }; |
349 | |
350 | static const struct mtk_fixed_clk fixed_clks[] = { |
351 | FIXED_CLK(CLK_TOP_ADSYS_26M, "adsys_26m" , "clk26m" , 26 * MHZ), |
352 | FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o" , "clk26m" , DUMMY_RATE), |
353 | FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m" , "clk26m" , 125 * MHZ), |
354 | FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig" , "clk26m" , DUMMY_RATE), |
355 | FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig" , "clk26m" , DUMMY_RATE), |
356 | }; |
357 | |
358 | static const struct mtk_fixed_factor top_divs[] = { |
359 | FACTOR(CLK_TOP_ARMCA53PLL_754M, "armca53pll_754m" , "clk26m" , 1, 2), |
360 | FACTOR(CLK_TOP_ARMCA53PLL_502M, "armca53pll_502m" , "clk26m" , 1, 3), |
361 | |
362 | FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m" , "mainpll" , 1, 2, 0), |
363 | FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m" , "mainpll" , 1, 3, 0), |
364 | FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m" , "mainpll" , 1, 5, 0), |
365 | FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m" , "mainpll" , 1, 7, 0), |
366 | |
367 | FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m" , "tvdpll" , 1, 4), |
368 | FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m" , "tvdpll" , 1, 3), |
369 | |
370 | FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m" , "univpll" , 1, 2, 0), |
371 | FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m" , "univpll" , 1, 3, 0), |
372 | FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m" , "univpll" , 1, 5, 0), |
373 | FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m" , "univpll" , 1, 7, 0), |
374 | FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m" , "univpll" , 1, 26, 0), |
375 | |
376 | FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext" , "clk32k" , 1, 1), |
377 | FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int" , "clk26m" , 1, 793), |
378 | FACTOR(CLK_TOP_FPC, "fpc_ck" , "clk26m" , 1, 1), |
379 | |
380 | FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2" , "clk26m" , 1, 2), |
381 | FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3" , "clk26m" , 1, 3), |
382 | |
383 | FACTOR(CLK_TOP_ARMCA53PLL_D2, "armca53pll_d2" , "clk26m" , 1, 1), |
384 | FACTOR(CLK_TOP_ARMCA53PLL_D3, "armca53pll_d3" , "clk26m" , 1, 1), |
385 | |
386 | FACTOR(CLK_TOP_APLL1, "apll1_ck" , "apll1" , 1, 1), |
387 | FACTOR(CLK_TOP_APLL2, "apll2_ck" , "apll2" , 1, 1), |
388 | |
389 | FACTOR(CLK_TOP_DMPLL, "dmpll_ck" , "clkph_mck_o" , 1, 1), |
390 | FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2" , "clkph_mck_o" , 1, 2), |
391 | FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4" , "clkph_mck_o" , 1, 4), |
392 | FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8" , "clkph_mck_o" , 1, 8), |
393 | FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16" , "clkph_mck_o" , 1, 16), |
394 | |
395 | FACTOR(CLK_TOP_MMPLL, "mmpll_ck" , "mmpll" , 1, 1), |
396 | FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2" , "mmpll" , 1, 2), |
397 | |
398 | FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck" , "msdcpll" , 1, 1), |
399 | FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2" , "msdcpll" , 1, 2), |
400 | FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4" , "msdcpll" , 1, 4), |
401 | FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck" , "msdcpll2" , 1, 1), |
402 | FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2" , "msdcpll2" , 1, 2), |
403 | FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4" , "msdcpll2" , 1, 4), |
404 | |
405 | FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2" , "main_h546m" , 1, 1, 0), |
406 | FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2" , "main_h546m" , 1, 2, 0), |
407 | FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4" , "main_h546m" , 1, 4, 0), |
408 | FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8" , "main_h546m" , 1, 8, 0), |
409 | FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16" , "main_h546m" , 1, 16, 0), |
410 | FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3" , "main_h364m" , 1, 1, 0), |
411 | FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2" , "main_h364m" , 1, 2, 0), |
412 | FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4" , "main_h364m" , 1, 4, 0), |
413 | FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5" , "main_h218p4m" , 1, 1, 0), |
414 | FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2" , "main_h218p4m" , 1, 2, 0), |
415 | FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4" , "main_h218p4m" , 1, 4, 0), |
416 | FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7" , "main_h156m" , 1, 1, 0), |
417 | FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2" , "main_h156m" , 1, 2, 0), |
418 | FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4" , "main_h156m" , 1, 4, 0), |
419 | |
420 | FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck" , "tvdpll_594m" , 1, 1), |
421 | FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2" , "tvdpll_594m" , 1, 2), |
422 | FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4" , "tvdpll_594m" , 1, 4), |
423 | FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8" , "tvdpll_594m" , 1, 8), |
424 | FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16" , "tvdpll_594m" , 1, 16), |
425 | |
426 | FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2" , "univ_624m" , 1, 1, 0), |
427 | FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2" , "univ_624m" , 1, 2, 0), |
428 | FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4" , "univ_624m" , 1, 4, 0), |
429 | FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8" , "univ_624m" , 1, 8, 0), |
430 | FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3" , "univ_416m" , 1, 1, 0), |
431 | FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2" , "univ_416m" , 1, 2, 0), |
432 | FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4" , "univ_416m" , 1, 4, 0), |
433 | FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8" , "univ_416m" , 1, 8, 0), |
434 | FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5" , "univ_249p6m" , 1, 1, 0), |
435 | FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2" , "univ_249p6m" , 1, 2, 0), |
436 | FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4" , "univ_249p6m" , 1, 4, 0), |
437 | FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8" , "univ_249p6m" , 1, 8, 0), |
438 | FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7" , "univ_178p3m" , 1, 1, 0), |
439 | FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26" , "univ_48m" , 1, 1, 0), |
440 | FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52" , "univ_48m" , 1, 2, 0), |
441 | |
442 | FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck" , "vcodecpll" , 1, 3), |
443 | FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5" , "vcodecpll" , 1, 4), |
444 | |
445 | FACTOR(CLK_TOP_VENCPLL, "vencpll_ck" , "vencpll" , 1, 1), |
446 | FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2" , "vencpll" , 1, 2), |
447 | FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4" , "vencpll" , 1, 4), |
448 | }; |
449 | |
450 | static const struct mtk_mux top_muxes[] = { |
451 | /* CLK_CFG_0 */ |
452 | TOP_MUX_GATE_NOSR(CLK_TOP_AXI_SEL, "axi_sel" , axi_parents, |
453 | 0x40, 0, 3, 7, CLK_IS_CRITICAL), |
454 | TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel" , mem_parents, |
455 | 0x40, 8, 1, 15, CLK_IS_CRITICAL), |
456 | TOP_MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel" , ddrphycfg_parents, |
457 | 0x40, 16, 1, 23, CLK_IS_CRITICAL), |
458 | TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel" , mm_parents, 0x40, 24, 3, 31, 0), |
459 | /* CLK_CFG_1 */ |
460 | TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel" , pwm_parents, 0x50, 0, 2, 7, 0), |
461 | TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel" , vdec_parents, 0x50, 8, 4, 15, 0), |
462 | TOP_MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel" , venc_parents, 0x50, 16, 4, 23, 0), |
463 | TOP_MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel" , mfg_parents, 0x50, 24, 4, 31, 0), |
464 | /* CLK_CFG_2 */ |
465 | TOP_MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel" , camtg_parents, 0x60, 0, 3, 7, 0), |
466 | TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel" , uart_parents, 0x60, 8, 1, 15, 0), |
467 | TOP_MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel" , spi_parents, 0x60, 16, 3, 23, 0), |
468 | TOP_MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel" , usb20_parents, 0x60, 24, 2, 31, 0), |
469 | /* CLK_CFG_3 */ |
470 | TOP_MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel" , usb30_parents, 0x70, 0, 2, 7, 0), |
471 | TOP_MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel" , msdc50_0_h_parents, |
472 | 0x70, 8, 3, 15, 0), |
473 | TOP_MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel" , msdc50_0_parents, 0x70, 16, 4, 23, 0), |
474 | TOP_MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel" , msdc30_1_parents, 0x70, 24, 3, 31, 0), |
475 | /* CLK_CFG_4 */ |
476 | TOP_MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel" , msdc30_2_parents, 0x80, 0, 3, 7, 0), |
477 | TOP_MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel" , msdc30_3_parents, 0x80, 8, 3, 15, 0), |
478 | TOP_MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel" , audio_parents, 0x80, 16, 2, 23, 0), |
479 | TOP_MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel" , aud_intbus_parents, |
480 | 0x80, 24, 3, 31, 0), |
481 | /* CLK_CFG_5 */ |
482 | TOP_MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel" , pmicspi_parents, 0x90, 0, 3, 5, 0), |
483 | TOP_MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel" , scp_parents, 0x90, 8, 3, 15, 0), |
484 | TOP_MUX_GATE(CLK_TOP_MJC_SEL, "mjc_sel" , mjc_parents, 0x90, 24, 4, 31, 0), |
485 | /* CLK_CFG_6 */ |
486 | /* |
487 | * The dpi0_sel clock should not propagate rate changes to its parent |
488 | * clock so the dpi driver can have full control over PLL and divider. |
489 | */ |
490 | TOP_MUX_GATE_NOSR(CLK_TOP_DPI0_SEL, "dpi0_sel" , dpi0_parents, 0xa0, 0, 3, 7, 0), |
491 | TOP_MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel" , irda_parents, 0xa0, 8, 2, 15, 0), |
492 | TOP_MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel" , cci400_parents, |
493 | 0xa0, 16, 3, 23, CLK_IS_CRITICAL), |
494 | TOP_MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel" , aud_1_parents, 0xa0, 24, 2, 31, 0), |
495 | /* CLK_CFG_7 */ |
496 | TOP_MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel" , aud_2_parents, 0xb0, 0, 2, 7, 0), |
497 | TOP_MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel" , mem_mfg_in_parents, |
498 | 0xb0, 8, 2, 15, 0), |
499 | TOP_MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel" , axi_mfg_in_parents, |
500 | 0xb0, 16, 2, 23, 0), |
501 | TOP_MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel" , scam_parents, 0xb0, 24, 2, 31, 0), |
502 | }; |
503 | |
504 | static struct mtk_composite top_aud_divs[] = { |
505 | MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel" , i2s0_m_ck_parents, 0x120, 4, 1), |
506 | MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel" , i2s1_m_ck_parents, 0x120, 5, 1), |
507 | MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel" , i2s2_m_ck_parents, 0x120, 6, 1), |
508 | MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel" , i2s3_m_ck_parents, 0x120, 7, 1), |
509 | MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel" , i2s3_b_ck_parents, 0x120, 8, 1), |
510 | |
511 | DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0" , "aud_1_sel" , 0x12c, 8, 0x120, 4, 24), |
512 | DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1" , "aud_1_sel" , 0x12c, 9, 0x124, 8, 0), |
513 | DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2" , "aud_1_sel" , 0x12c, 10, 0x124, 8, 8), |
514 | DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3" , "aud_1_sel" , 0x12c, 11, 0x124, 8, 16), |
515 | DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4" , "aud_1_sel" , 0x12c, 12, 0x124, 8, 24), |
516 | DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5" , "apll1_div4" , 0x12c, 13, 0x12c, 4, 0), |
517 | |
518 | DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0" , "aud_2_sel" , 0x12c, 16, 0x120, 4, 28), |
519 | DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1" , "aud_2_sel" , 0x12c, 17, 0x128, 8, 0), |
520 | DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2" , "aud_2_sel" , 0x12c, 18, 0x128, 8, 8), |
521 | DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3" , "aud_2_sel" , 0x12c, 19, 0x128, 8, 16), |
522 | DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4" , "aud_2_sel" , 0x12c, 20, 0x128, 8, 24), |
523 | DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5" , "apll2_div4" , 0x12c, 21, 0x12c, 4, 4), |
524 | }; |
525 | |
526 | static const struct mtk_clk_desc topck_desc = { |
527 | .fixed_clks = fixed_clks, |
528 | .num_fixed_clks = ARRAY_SIZE(fixed_clks), |
529 | .factor_clks = top_divs, |
530 | .num_factor_clks = ARRAY_SIZE(top_divs), |
531 | .mux_clks = top_muxes, |
532 | .num_mux_clks = ARRAY_SIZE(top_muxes), |
533 | .composite_clks = top_aud_divs, |
534 | .num_composite_clks = ARRAY_SIZE(top_aud_divs), |
535 | .clk_lock = &mt6795_top_clk_lock, |
536 | }; |
537 | |
538 | static const struct of_device_id of_match_clk_mt6795_topckgen[] = { |
539 | { .compatible = "mediatek,mt6795-topckgen" , .data = &topck_desc }, |
540 | { /* sentinel */ } |
541 | }; |
542 | MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_topckgen); |
543 | |
544 | static struct platform_driver clk_mt6795_topckgen_drv = { |
545 | .driver = { |
546 | .name = "clk-mt6795-topckgen" , |
547 | .of_match_table = of_match_clk_mt6795_topckgen, |
548 | }, |
549 | .probe = mtk_clk_simple_probe, |
550 | .remove_new = mtk_clk_simple_remove, |
551 | }; |
552 | module_platform_driver(clk_mt6795_topckgen_drv); |
553 | |
554 | MODULE_DESCRIPTION("MediaTek MT6795 topckgen clocks driver" ); |
555 | MODULE_LICENSE("GPL" ); |
556 | |