1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2021 MediaTek Inc. |
4 | * Author: Sam Shih <sam.shih@mediatek.com> |
5 | * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/mod_devicetable.h> |
10 | #include <linux/platform_device.h> |
11 | |
12 | #include "clk-mtk.h" |
13 | #include "clk-gate.h" |
14 | |
15 | #include <dt-bindings/clock/mt7986-clk.h> |
16 | |
17 | static const struct mtk_gate_regs sgmii0_cg_regs = { |
18 | .set_ofs = 0xe4, |
19 | .clr_ofs = 0xe4, |
20 | .sta_ofs = 0xe4, |
21 | }; |
22 | |
23 | #define GATE_SGMII0(_id, _name, _parent, _shift) \ |
24 | GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
25 | |
26 | static const struct mtk_gate sgmii0_clks[] = { |
27 | GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en" , "top_xtal" , 2), |
28 | GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en" , "top_xtal" , 3), |
29 | GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref" , "top_xtal" , 4), |
30 | GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb" , "top_xtal" , 5), |
31 | }; |
32 | |
33 | static const struct mtk_gate_regs sgmii1_cg_regs = { |
34 | .set_ofs = 0xe4, |
35 | .clr_ofs = 0xe4, |
36 | .sta_ofs = 0xe4, |
37 | }; |
38 | |
39 | #define GATE_SGMII1(_id, _name, _parent, _shift) \ |
40 | GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
41 | |
42 | static const struct mtk_gate sgmii1_clks[] = { |
43 | GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en" , "top_xtal" , 2), |
44 | GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en" , "top_xtal" , 3), |
45 | GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref" , "top_xtal" , 4), |
46 | GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb" , "top_xtal" , 5), |
47 | }; |
48 | |
49 | static const struct mtk_gate_regs eth_cg_regs = { |
50 | .set_ofs = 0x30, |
51 | .clr_ofs = 0x30, |
52 | .sta_ofs = 0x30, |
53 | }; |
54 | |
55 | #define GATE_ETH(_id, _name, _parent, _shift) \ |
56 | GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
57 | |
58 | static const struct mtk_gate eth_clks[] = { |
59 | GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en" , "netsys_2x_sel" , 6), |
60 | GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en" , "sgm_325m_sel" , 7), |
61 | GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en" , "sgm_325m_sel" , 8), |
62 | GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en" , "netsys_mcu_sel" , 14), |
63 | GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en" , "netsys_mcu_sel" , 15), |
64 | }; |
65 | |
66 | static const struct mtk_clk_desc eth_desc = { |
67 | .clks = eth_clks, |
68 | .num_clks = ARRAY_SIZE(eth_clks), |
69 | }; |
70 | |
71 | static const struct mtk_clk_desc sgmii0_desc = { |
72 | .clks = sgmii0_clks, |
73 | .num_clks = ARRAY_SIZE(sgmii0_clks), |
74 | }; |
75 | |
76 | static const struct mtk_clk_desc sgmii1_desc = { |
77 | .clks = sgmii1_clks, |
78 | .num_clks = ARRAY_SIZE(sgmii1_clks), |
79 | }; |
80 | |
81 | static const struct of_device_id of_match_clk_mt7986_eth[] = { |
82 | { .compatible = "mediatek,mt7986-ethsys" , .data = ð_desc }, |
83 | { .compatible = "mediatek,mt7986-sgmiisys_0" , .data = &sgmii0_desc }, |
84 | { .compatible = "mediatek,mt7986-sgmiisys_1" , .data = &sgmii1_desc }, |
85 | { /* sentinel */ } |
86 | }; |
87 | MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_eth); |
88 | |
89 | static struct platform_driver clk_mt7986_eth_drv = { |
90 | .driver = { |
91 | .name = "clk-mt7986-eth" , |
92 | .of_match_table = of_match_clk_mt7986_eth, |
93 | }, |
94 | .probe = mtk_clk_simple_probe, |
95 | .remove_new = mtk_clk_simple_remove, |
96 | }; |
97 | module_platform_driver(clk_mt7986_eth_drv); |
98 | |
99 | MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver" ); |
100 | MODULE_LICENSE("GPL" ); |
101 | |