1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include "clk-mtk.h"
14#include "clk-gate.h"
15#include "clk-mux.h"
16#include "clk-pll.h"
17#include <dt-bindings/clock/mediatek,mt7988-clk.h>
18
19#define MT7988_PLL_FMAX (2500UL * MHZ)
20#define MT7988_PCW_CHG_BIT 2
21
22#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
23 _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \
24 _pcw_chg_reg) \
25 { \
26 .id = _id, \
27 .name = _name, \
28 .reg = _reg, \
29 .pwr_reg = _pwr_reg, \
30 .en_mask = _en_mask, \
31 .flags = _flags, \
32 .rst_bar_mask = BIT(_rst_bar_mask), \
33 .fmax = MT7988_PLL_FMAX, \
34 .pcwbits = _pcwbits, \
35 .pd_reg = _pd_reg, \
36 .pd_shift = _pd_shift, \
37 .tuner_reg = _tuner_reg, \
38 .tuner_en_reg = _tuner_en_reg, \
39 .tuner_en_bit = _tuner_en_bit, \
40 .pcw_reg = _pcw_reg, \
41 .pcw_shift = _pcw_shift, \
42 .pcw_chg_reg = _pcw_chg_reg, \
43 .pcw_chg_bit = MT7988_PCW_CHG_BIT, \
44 .parent_name = "clkxtal", \
45 }
46
47static const struct mtk_pll_data plls[] = {
48 PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
49 0, 0, 0x0108, 0, 0x0104),
50 PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
51 0, 0, 0, 0x0118, 0, 0x0114),
52 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
53 0, 0, 0, 0x0128, 0, 0x0124),
54 PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
55 0x0700, 1, 0x0138, 0, 0x0134),
56 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
57 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
58 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
59 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
60 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
61 0, 0, 0x0168, 0, 0x0164),
62 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
63 0x0178, 0, 0x0174),
64 PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
65 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
66 PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
67 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
68 PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
69 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
70 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
71 0, 0x0318, 0, 0x0314),
72};
73
74static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
75 { .compatible = "mediatek,mt7988-apmixedsys" },
76 { /* sentinel */ }
77};
78
79static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
80{
81 struct clk_hw_onecell_data *clk_data;
82 struct device_node *node = pdev->dev.of_node;
83 int r;
84
85 clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
86 if (!clk_data)
87 return -ENOMEM;
88
89 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
90 if (r)
91 goto free_apmixed_data;
92
93 r = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, data: clk_data);
94 if (r)
95 goto unregister_plls;
96
97 return r;
98
99unregister_plls:
100 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
101free_apmixed_data:
102 mtk_free_clk_data(clk_data);
103 return r;
104}
105
106static struct platform_driver clk_mt7988_apmixed_drv = {
107 .probe = clk_mt7988_apmixed_probe,
108 .driver = {
109 .name = "clk-mt7988-apmixed",
110 .of_match_table = of_match_clk_mt7988_apmixed,
111 },
112};
113builtin_platform_driver(clk_mt7988_apmixed_drv);
114
115MODULE_DESCRIPTION("MediaTek MT7988 apmixedsys clocks driver");
116MODULE_LICENSE("GPL");
117

source code of linux/drivers/clk/mediatek/clk-mt7988-apmixed.c