1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2020 MediaTek Inc. |
4 | * Copyright (c) 2020 BayLibre, SAS |
5 | * Copyright (c) 2023 Collabora, Ltd. |
6 | */ |
7 | |
8 | #include <dt-bindings/clock/mt8167-clk.h> |
9 | #include <linux/clk.h> |
10 | #include <linux/of.h> |
11 | #include <linux/platform_device.h> |
12 | |
13 | #include "clk-pll.h" |
14 | #include "clk-mtk.h" |
15 | |
16 | static DEFINE_SPINLOCK(mt8167_apmixed_clk_lock); |
17 | |
18 | #define MT8167_PLL_FMAX (2500UL * MHZ) |
19 | |
20 | #define CON0_MT8167_RST_BAR BIT(27) |
21 | |
22 | #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
23 | _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ |
24 | _pcw_shift, _div_table) { \ |
25 | .id = _id, \ |
26 | .name = _name, \ |
27 | .reg = _reg, \ |
28 | .pwr_reg = _pwr_reg, \ |
29 | .en_mask = _en_mask, \ |
30 | .flags = _flags, \ |
31 | .rst_bar_mask = CON0_MT8167_RST_BAR, \ |
32 | .fmax = MT8167_PLL_FMAX, \ |
33 | .pcwbits = _pcwbits, \ |
34 | .pd_reg = _pd_reg, \ |
35 | .pd_shift = _pd_shift, \ |
36 | .tuner_reg = _tuner_reg, \ |
37 | .pcw_reg = _pcw_reg, \ |
38 | .pcw_shift = _pcw_shift, \ |
39 | .div_table = _div_table, \ |
40 | } |
41 | |
42 | #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
43 | _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ |
44 | _pcw_shift) \ |
45 | PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
46 | _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ |
47 | NULL) |
48 | |
49 | static const struct mtk_pll_div_table mmpll_div_table[] = { |
50 | { .div = 0, .freq = MT8167_PLL_FMAX }, |
51 | { .div = 1, .freq = 1000000000 }, |
52 | { .div = 2, .freq = 604500000 }, |
53 | { .div = 3, .freq = 253500000 }, |
54 | { .div = 4, .freq = 126750000 }, |
55 | { /* sentinel */ } |
56 | }; |
57 | |
58 | static const struct mtk_pll_data plls[] = { |
59 | PLL(CLK_APMIXED_ARMPLL, "armpll" , 0x0100, 0x0110, 0, 0, |
60 | 21, 0x0104, 24, 0, 0x0104, 0), |
61 | PLL(CLK_APMIXED_MAINPLL, "mainpll" , 0x0120, 0x0130, 0, |
62 | HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), |
63 | PLL(CLK_APMIXED_UNIVPLL, "univpll" , 0x0140, 0x0150, 0x30000000, |
64 | HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), |
65 | PLL_B(CLK_APMIXED_MMPLL, "mmpll" , 0x0160, 0x0170, 0, 0, |
66 | 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), |
67 | PLL(CLK_APMIXED_APLL1, "apll1" , 0x0180, 0x0190, 0, 0, |
68 | 31, 0x0180, 1, 0x0194, 0x0184, 0), |
69 | PLL(CLK_APMIXED_APLL2, "apll2" , 0x01A0, 0x01B0, 0, 0, |
70 | 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), |
71 | PLL(CLK_APMIXED_TVDPLL, "tvdpll" , 0x01C0, 0x01D0, 0, 0, |
72 | 21, 0x01C4, 24, 0, 0x01C4, 0), |
73 | PLL(CLK_APMIXED_LVDSPLL, "lvdspll" , 0x01E0, 0x01F0, 0, 0, |
74 | 21, 0x01E4, 24, 0, 0x01E4, 0), |
75 | }; |
76 | |
77 | #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ |
78 | .id = _id, \ |
79 | .name = _name, \ |
80 | .parent_name = _parent, \ |
81 | .div_reg = _reg, \ |
82 | .div_shift = _shift, \ |
83 | .div_width = _width, \ |
84 | .clk_divider_flags = _flag, \ |
85 | } |
86 | |
87 | static const struct mtk_clk_divider adj_divs[] = { |
88 | DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref" , "tvdpll" , |
89 | 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), |
90 | }; |
91 | |
92 | static int clk_mt8167_apmixed_probe(struct platform_device *pdev) |
93 | { |
94 | void __iomem *base; |
95 | struct clk_hw_onecell_data *clk_data; |
96 | struct device_node *node = pdev->dev.of_node; |
97 | struct device *dev = &pdev->dev; |
98 | int ret; |
99 | |
100 | base = devm_platform_ioremap_resource(pdev, index: 0); |
101 | if (IS_ERR(ptr: base)) |
102 | return PTR_ERR(ptr: base); |
103 | |
104 | clk_data = mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK); |
105 | if (!clk_data) |
106 | return -ENOMEM; |
107 | |
108 | ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); |
109 | if (ret) |
110 | return ret; |
111 | |
112 | ret = mtk_clk_register_dividers(dev, mcds: adj_divs, ARRAY_SIZE(adj_divs), base, |
113 | lock: &mt8167_apmixed_clk_lock, clk_data); |
114 | if (ret) |
115 | goto unregister_plls; |
116 | |
117 | ret = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, data: clk_data); |
118 | if (ret) |
119 | goto unregister_dividers; |
120 | |
121 | return 0; |
122 | |
123 | unregister_dividers: |
124 | mtk_clk_unregister_dividers(mcds: adj_divs, ARRAY_SIZE(adj_divs), clk_data); |
125 | unregister_plls: |
126 | mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); |
127 | |
128 | return ret; |
129 | } |
130 | |
131 | static const struct of_device_id of_match_clk_mt8167_apmixed[] = { |
132 | { .compatible = "mediatek,mt8167-apmixedsys" }, |
133 | { /* sentinel */ } |
134 | }; |
135 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed); |
136 | |
137 | static struct platform_driver clk_mt8167_apmixed_drv = { |
138 | .probe = clk_mt8167_apmixed_probe, |
139 | .driver = { |
140 | .name = "clk-mt8167-apmixed" , |
141 | .of_match_table = of_match_clk_mt8167_apmixed, |
142 | }, |
143 | }; |
144 | builtin_platform_driver(clk_mt8167_apmixed_drv) |
145 | MODULE_LICENSE("GPL" ); |
146 | |