1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 MediaTek Inc. |
4 | * Copyright (c) 2022 Collabora Ltd. |
5 | * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
6 | */ |
7 | |
8 | #include <dt-bindings/clock/mt8173-clk.h> |
9 | #include <linux/module.h> |
10 | #include <linux/platform_device.h> |
11 | #include "clk-cpumux.h" |
12 | #include "clk-gate.h" |
13 | #include "clk-mtk.h" |
14 | #include "reset.h" |
15 | |
16 | #define GATE_ICG(_id, _name, _parent, _shift) \ |
17 | GATE_MTK(_id, _name, _parent, &infra_cg_regs, \ |
18 | _shift, &mtk_clk_gate_ops_setclr) |
19 | |
20 | static struct clk_hw_onecell_data *infra_clk_data; |
21 | |
22 | static const struct mtk_gate_regs infra_cg_regs = { |
23 | .set_ofs = 0x0040, |
24 | .clr_ofs = 0x0044, |
25 | .sta_ofs = 0x0048, |
26 | }; |
27 | |
28 | static const char * const ca53_parents[] __initconst = { |
29 | "clk26m" , |
30 | "armca7pll" , |
31 | "mainpll" , |
32 | "univpll" |
33 | }; |
34 | |
35 | static const char * const ca72_parents[] __initconst = { |
36 | "clk26m" , |
37 | "armca15pll" , |
38 | "mainpll" , |
39 | "univpll" |
40 | }; |
41 | |
42 | static const struct mtk_composite cpu_muxes[] = { |
43 | MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel" , ca53_parents, 0x0000, 0, 2), |
44 | MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel" , ca72_parents, 0x0000, 2, 2), |
45 | }; |
46 | |
47 | static const struct mtk_fixed_factor infra_early_divs[] = { |
48 | FACTOR(CLK_INFRA_CLK_13M, "clk13m" , "clk26m" , 1, 2), |
49 | }; |
50 | |
51 | static const struct mtk_gate infra_gates[] = { |
52 | GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk" , "axi_sel" , 0), |
53 | GATE_ICG(CLK_INFRA_SMI, "infra_smi" , "mm_sel" , 1), |
54 | GATE_ICG(CLK_INFRA_AUDIO, "infra_audio" , "aud_intbus_sel" , 5), |
55 | GATE_ICG(CLK_INFRA_GCE, "infra_gce" , "axi_sel" , 6), |
56 | GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram" , "axi_sel" , 7), |
57 | GATE_ICG(CLK_INFRA_M4U, "infra_m4u" , "mem_sel" , 8), |
58 | GATE_ICG(CLK_INFRA_CPUM, "infra_cpum" , "cpum_ck" , 15), |
59 | GATE_ICG(CLK_INFRA_KP, "infra_kp" , "axi_sel" , 16), |
60 | GATE_ICG(CLK_INFRA_CEC, "infra_cec" , "clk26m" , 18), |
61 | GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi" , "pmicspi_sel" , 22), |
62 | GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap" , "axi_sel" , 23), |
63 | }; |
64 | |
65 | static u16 infrasys_rst_ofs[] = { 0x30, 0x34 }; |
66 | |
67 | static const struct mtk_clk_rst_desc clk_rst_desc = { |
68 | .version = MTK_RST_SIMPLE, |
69 | .rst_bank_ofs = infrasys_rst_ofs, |
70 | .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), |
71 | }; |
72 | |
73 | static const struct of_device_id of_match_clk_mt8173_infracfg[] = { |
74 | { .compatible = "mediatek,mt8173-infracfg" }, |
75 | { /* sentinel */ } |
76 | }; |
77 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg); |
78 | |
79 | static void clk_mt8173_infra_init_early(struct device_node *node) |
80 | { |
81 | int i; |
82 | |
83 | infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); |
84 | if (!infra_clk_data) |
85 | return; |
86 | |
87 | for (i = 0; i < CLK_INFRA_NR_CLK; i++) |
88 | infra_clk_data->hws[i] = ERR_PTR(error: -EPROBE_DEFER); |
89 | |
90 | mtk_clk_register_factors(clks: infra_early_divs, |
91 | ARRAY_SIZE(infra_early_divs), clk_data: infra_clk_data); |
92 | |
93 | of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, data: infra_clk_data); |
94 | } |
95 | CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg" , |
96 | clk_mt8173_infra_init_early); |
97 | |
98 | static int clk_mt8173_infracfg_probe(struct platform_device *pdev) |
99 | { |
100 | struct device_node *node = pdev->dev.of_node; |
101 | int r; |
102 | |
103 | r = mtk_clk_register_gates(dev: &pdev->dev, node, clks: infra_gates, |
104 | ARRAY_SIZE(infra_gates), clk_data: infra_clk_data); |
105 | if (r) |
106 | return r; |
107 | |
108 | r = mtk_clk_register_cpumuxes(dev: &pdev->dev, node, clks: cpu_muxes, |
109 | ARRAY_SIZE(cpu_muxes), clk_data: infra_clk_data); |
110 | if (r) |
111 | goto unregister_gates; |
112 | |
113 | r = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, data: infra_clk_data); |
114 | if (r) |
115 | goto unregister_cpumuxes; |
116 | |
117 | r = mtk_register_reset_controller_with_dev(dev: &pdev->dev, desc: &clk_rst_desc); |
118 | if (r) |
119 | goto unregister_clk_hw; |
120 | |
121 | return 0; |
122 | |
123 | unregister_clk_hw: |
124 | of_clk_del_provider(np: node); |
125 | unregister_cpumuxes: |
126 | mtk_clk_unregister_cpumuxes(clks: cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data: infra_clk_data); |
127 | unregister_gates: |
128 | mtk_clk_unregister_gates(clks: infra_gates, ARRAY_SIZE(infra_gates), clk_data: infra_clk_data); |
129 | return r; |
130 | } |
131 | |
132 | static void clk_mt8173_infracfg_remove(struct platform_device *pdev) |
133 | { |
134 | struct device_node *node = pdev->dev.of_node; |
135 | struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); |
136 | |
137 | of_clk_del_provider(np: node); |
138 | mtk_clk_unregister_cpumuxes(clks: cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); |
139 | mtk_clk_unregister_gates(clks: infra_gates, ARRAY_SIZE(infra_gates), clk_data); |
140 | mtk_free_clk_data(clk_data); |
141 | } |
142 | |
143 | static struct platform_driver clk_mt8173_infracfg_drv = { |
144 | .driver = { |
145 | .name = "clk-mt8173-infracfg" , |
146 | .of_match_table = of_match_clk_mt8173_infracfg, |
147 | }, |
148 | .probe = clk_mt8173_infracfg_probe, |
149 | .remove_new = clk_mt8173_infracfg_remove, |
150 | }; |
151 | module_platform_driver(clk_mt8173_infracfg_drv); |
152 | |
153 | MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver" ); |
154 | MODULE_LICENSE("GPL" ); |
155 | |