1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 MediaTek Inc. |
4 | * Copyright (c) 2022 Collabora Ltd. |
5 | * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
6 | */ |
7 | |
8 | #include <dt-bindings/clock/mt8173-clk.h> |
9 | #include <linux/module.h> |
10 | #include <linux/platform_device.h> |
11 | #include "clk-gate.h" |
12 | #include "clk-mtk.h" |
13 | |
14 | #define GATE_VDEC(_id, _name, _parent, _regs) \ |
15 | GATE_MTK(_id, _name, _parent, _regs, 0, \ |
16 | &mtk_clk_gate_ops_setclr_inv) |
17 | |
18 | static const struct mtk_gate_regs vdec0_cg_regs = { |
19 | .set_ofs = 0x0000, |
20 | .clr_ofs = 0x0004, |
21 | .sta_ofs = 0x0000, |
22 | }; |
23 | |
24 | static const struct mtk_gate_regs vdec1_cg_regs = { |
25 | .set_ofs = 0x0008, |
26 | .clr_ofs = 0x000c, |
27 | .sta_ofs = 0x0008, |
28 | }; |
29 | |
30 | static const struct mtk_gate vdec_clks[] = { |
31 | GATE_DUMMY(CLK_DUMMY, "vdec_dummy" ), |
32 | GATE_VDEC(CLK_VDEC_CKEN, "vdec_cken" , "vdec_sel" , &vdec0_cg_regs), |
33 | GATE_VDEC(CLK_VDEC_LARB_CKEN, "vdec_larb_cken" , "mm_sel" , &vdec1_cg_regs), |
34 | }; |
35 | |
36 | static const struct mtk_clk_desc vdec_desc = { |
37 | .clks = vdec_clks, |
38 | .num_clks = ARRAY_SIZE(vdec_clks), |
39 | }; |
40 | |
41 | static const struct of_device_id of_match_clk_mt8173_vdecsys[] = { |
42 | { .compatible = "mediatek,mt8173-vdecsys" , .data = &vdec_desc }, |
43 | { /* sentinel */ } |
44 | }; |
45 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vdecsys); |
46 | |
47 | static struct platform_driver clk_mt8173_vdecsys_drv = { |
48 | .probe = mtk_clk_simple_probe, |
49 | .remove_new = mtk_clk_simple_remove, |
50 | .driver = { |
51 | .name = "clk-mt8173-vdecsys" , |
52 | .of_match_table = of_match_clk_mt8173_vdecsys, |
53 | }, |
54 | }; |
55 | module_platform_driver(clk_mt8173_vdecsys_drv); |
56 | |
57 | MODULE_DESCRIPTION("MediaTek MT8173 vdecsys clocks driver" ); |
58 | MODULE_LICENSE("GPL" ); |
59 | |