1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // |
3 | // Copyright (c) 2018 MediaTek Inc. |
4 | // Author: Weiyi Lu <weiyi.lu@mediatek.com> |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/platform_device.h> |
8 | |
9 | #include "clk-mtk.h" |
10 | #include "clk-gate.h" |
11 | |
12 | #include <dt-bindings/clock/mt8183-clk.h> |
13 | |
14 | static const struct mtk_gate_regs ipu_adl_cg_regs = { |
15 | .set_ofs = 0x204, |
16 | .clr_ofs = 0x204, |
17 | .sta_ofs = 0x204, |
18 | }; |
19 | |
20 | #define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \ |
21 | GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \ |
22 | &mtk_clk_gate_ops_no_setclr_inv) |
23 | |
24 | static const struct mtk_gate ipu_adl_clks[] = { |
25 | GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen" , "dsp_sel" , 24), |
26 | }; |
27 | |
28 | static const struct mtk_clk_desc ipu_adl_desc = { |
29 | .clks = ipu_adl_clks, |
30 | .num_clks = ARRAY_SIZE(ipu_adl_clks), |
31 | }; |
32 | |
33 | static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = { |
34 | { |
35 | .compatible = "mediatek,mt8183-ipu_adl" , |
36 | .data = &ipu_adl_desc, |
37 | }, { |
38 | /* sentinel */ |
39 | } |
40 | }; |
41 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_adl); |
42 | |
43 | static struct platform_driver clk_mt8183_ipu_adl_drv = { |
44 | .probe = mtk_clk_simple_probe, |
45 | .remove_new = mtk_clk_simple_remove, |
46 | .driver = { |
47 | .name = "clk-mt8183-ipu_adl" , |
48 | .of_match_table = of_match_clk_mt8183_ipu_adl, |
49 | }, |
50 | }; |
51 | module_platform_driver(clk_mt8183_ipu_adl_drv); |
52 | MODULE_LICENSE("GPL" ); |
53 | |