1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2022 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/platform_device.h> |
8 | #include <dt-bindings/clock/mt8186-clk.h> |
9 | |
10 | #include "clk-mtk.h" |
11 | |
12 | static const char * const mcu_armpll_ll_parents[] = { |
13 | "clk26m" , |
14 | "armpll_ll" , |
15 | "mainpll" , |
16 | "univpll_d2" |
17 | }; |
18 | |
19 | static const char * const mcu_armpll_bl_parents[] = { |
20 | "clk26m" , |
21 | "armpll_bl" , |
22 | "mainpll" , |
23 | "univpll_d2" |
24 | }; |
25 | |
26 | static const char * const mcu_armpll_bus_parents[] = { |
27 | "clk26m" , |
28 | "ccipll" , |
29 | "mainpll" , |
30 | "univpll_d2" |
31 | }; |
32 | |
33 | /* |
34 | * We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver. |
35 | * Other fields like divider always keep the same value. (set once in bootloader) |
36 | */ |
37 | static struct mtk_composite mcu_muxes[] = { |
38 | /* CPU_PLLDIV_CFG0 */ |
39 | MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel" , mcu_armpll_ll_parents, 0x2A0, 9, 2), |
40 | /* CPU_PLLDIV_CFG1 */ |
41 | MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel" , mcu_armpll_bl_parents, 0x2A4, 9, 2), |
42 | /* BUS_PLLDIV_CFG */ |
43 | MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel" , mcu_armpll_bus_parents, 0x2E0, 9, 2), |
44 | }; |
45 | |
46 | static const struct mtk_clk_desc mcu_desc = { |
47 | .composite_clks = mcu_muxes, |
48 | .num_composite_clks = ARRAY_SIZE(mcu_muxes), |
49 | }; |
50 | |
51 | static const struct of_device_id of_match_clk_mt8186_mcu[] = { |
52 | { .compatible = "mediatek,mt8186-mcusys" , .data = &mcu_desc }, |
53 | { /* sentinel */} |
54 | }; |
55 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mcu); |
56 | |
57 | static struct platform_driver clk_mt8186_mcu_drv = { |
58 | .driver = { |
59 | .name = "clk-mt8186-mcu" , |
60 | .of_match_table = of_match_clk_mt8186_mcu, |
61 | }, |
62 | .probe = mtk_clk_simple_probe, |
63 | .remove_new = mtk_clk_simple_remove, |
64 | }; |
65 | module_platform_driver(clk_mt8186_mcu_drv); |
66 | |
67 | MODULE_DESCRIPTION("MediaTek MT8186 mcusys clocks driver" ); |
68 | MODULE_LICENSE("GPL" ); |
69 | |