1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2022 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/platform_device.h> |
8 | #include <dt-bindings/clock/mt8186-clk.h> |
9 | |
10 | #include "clk-gate.h" |
11 | #include "clk-mtk.h" |
12 | |
13 | static const struct mtk_gate_regs mfg_cg_regs = { |
14 | .set_ofs = 0x4, |
15 | .clr_ofs = 0x8, |
16 | .sta_ofs = 0x0, |
17 | }; |
18 | |
19 | #define GATE_MFG(_id, _name, _parent, _shift) \ |
20 | GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ |
21 | &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) |
22 | |
23 | static const struct mtk_gate mfg_clks[] = { |
24 | GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d" , "top_mfg" , 0), |
25 | }; |
26 | |
27 | static const struct mtk_clk_desc mfg_desc = { |
28 | .clks = mfg_clks, |
29 | .num_clks = ARRAY_SIZE(mfg_clks), |
30 | }; |
31 | |
32 | static const struct of_device_id of_match_clk_mt8186_mfg[] = { |
33 | { |
34 | .compatible = "mediatek,mt8186-mfgsys" , |
35 | .data = &mfg_desc, |
36 | }, { |
37 | /* sentinel */ |
38 | } |
39 | }; |
40 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mfg); |
41 | |
42 | static struct platform_driver clk_mt8186_mfg_drv = { |
43 | .probe = mtk_clk_simple_probe, |
44 | .remove_new = mtk_clk_simple_remove, |
45 | .driver = { |
46 | .name = "clk-mt8186-mfg" , |
47 | .of_match_table = of_match_clk_mt8186_mfg, |
48 | }, |
49 | }; |
50 | module_platform_driver(clk_mt8186_mfg_drv); |
51 | MODULE_LICENSE("GPL" ); |
52 | |