1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2022 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/platform_device.h> |
8 | #include <dt-bindings/clock/mt8186-clk.h> |
9 | |
10 | #include "clk-gate.h" |
11 | #include "clk-mtk.h" |
12 | |
13 | static const struct mtk_gate_regs mm0_cg_regs = { |
14 | .set_ofs = 0x104, |
15 | .clr_ofs = 0x108, |
16 | .sta_ofs = 0x100, |
17 | }; |
18 | |
19 | static const struct mtk_gate_regs mm1_cg_regs = { |
20 | .set_ofs = 0x1a4, |
21 | .clr_ofs = 0x1a8, |
22 | .sta_ofs = 0x1a0, |
23 | }; |
24 | |
25 | #define GATE_MM0(_id, _name, _parent, _shift) \ |
26 | GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
27 | |
28 | #define GATE_MM1(_id, _name, _parent, _shift) \ |
29 | GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
30 | |
31 | static const struct mtk_gate mm_clks[] = { |
32 | /* MM0 */ |
33 | GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0" , "top_disp" , 0), |
34 | GATE_MM0(CLK_MM_APB_MM_BUS, "mm_apb_mm_bus" , "top_disp" , 1), |
35 | GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0" , "top_disp" , 2), |
36 | GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0" , "top_disp" , 3), |
37 | GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l" , "top_disp" , 4), |
38 | GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0" , "top_disp" , 5), |
39 | GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0" , "top_disp" , 7), |
40 | GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0" , "top_disp" , 8), |
41 | GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0" , "top_disp" , 9), |
42 | GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0" , "top_disp" , 10), |
43 | GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra" , "top_disp" , 11), |
44 | GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0" , "top_disp" , 12), |
45 | GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0" , "top_disp" , 13), |
46 | GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0" , "top_disp" , 14), |
47 | GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0" , "top_disp" , 16), |
48 | GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common" , "top_disp" , 17), |
49 | GATE_MM0(CLK_MM_DSI0, "mm_dsi0" , "top_disp" , 19), |
50 | GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0" , "top_disp" , 20), |
51 | GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1" , "top_disp" , 21), |
52 | GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals" , "top_disp" , 22), |
53 | GATE_MM0(CLK_MM_SMI_IOMMU, "mm_smi_iommu" , "top_disp" , 24), |
54 | GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1" , "top_disp" , 25), |
55 | GATE_MM0(CLK_MM_DISP_DPI, "mm_disp_dpi" , "top_disp" , 26), |
56 | /* MM1 */ |
57 | GATE_MM1(CLK_MM_DSI0_DSI_CK_DOMAIN, "mm_dsi0_dsi_domain" , "top_disp" , 0), |
58 | GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck" , "top_disp" , 10), |
59 | }; |
60 | |
61 | static const struct mtk_clk_desc mm_desc = { |
62 | .clks = mm_clks, |
63 | .num_clks = ARRAY_SIZE(mm_clks), |
64 | }; |
65 | |
66 | static const struct platform_device_id clk_mt8186_mm_id_table[] = { |
67 | { .name = "clk-mt8186-mm" , .driver_data = (kernel_ulong_t)&mm_desc }, |
68 | { /* sentinel */ } |
69 | }; |
70 | MODULE_DEVICE_TABLE(platform, clk_mt8186_mm_id_table); |
71 | |
72 | static struct platform_driver clk_mt8186_mm_drv = { |
73 | .probe = mtk_clk_pdev_probe, |
74 | .remove_new = mtk_clk_pdev_remove, |
75 | .driver = { |
76 | .name = "clk-mt8186-mm" , |
77 | }, |
78 | .id_table = clk_mt8186_mm_id_table, |
79 | }; |
80 | module_platform_driver(clk_mt8186_mm_drv); |
81 | MODULE_LICENSE("GPL" ); |
82 | |