1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Garmin Chang <garmin.chang@mediatek.com>
5 */
6
7#include <dt-bindings/clock/mediatek,mt8188-clk.h>
8#include <linux/mod_devicetable.h>
9#include <linux/platform_device.h>
10
11#include "clk-gate.h"
12#include "clk-mtk.h"
13#include "clk-mux.h"
14
15static DEFINE_SPINLOCK(mt8188_clk_lock);
16
17static const struct mtk_fixed_clk top_fixed_clks[] = {
18 FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
19 FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL, 49152000),
20 FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
21 FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 533000000),
22 FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
23 FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
24};
25
26static const struct mtk_fixed_factor top_divs[] = {
27 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
28 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
29 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
30 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
31 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
32 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
33 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
34 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
35 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
36 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
37 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
38 FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
39 FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
40 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
41 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
42 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
43 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
44 FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
45 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
46 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
47 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
48 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
49 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
50 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
51 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
52 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
53 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
54 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
55 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
56 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
57 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
58 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
59 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
60 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
61 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
62 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
63 FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll_192m", 1, 10),
64 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
65 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
66 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
67 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
68 FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
69 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
70 FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
71 FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
72 FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
73 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
74 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
75 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
76 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
77 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
78 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
79 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
80 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
81 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
82 FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
83 FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
84 FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
85 FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
86 FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
87 FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
88 FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
89 FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
90 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
91 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
92 FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
93 FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll", 1, 4),
94 FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
95 FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
96 FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
97 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
98 FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
99 FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1, 2),
100 FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1, 4),
101 FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1, 8),
102 FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1, 7),
103 FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1, 10),
104 FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1, 16),
105};
106
107static const char * const axi_parents[] = {
108 "clk26m",
109 "mainpll_d4_d4",
110 "mainpll_d7_d2",
111 "mainpll_d4_d2",
112 "mainpll_d5_d2",
113 "mainpll_d6_d2",
114 "ulposc1_d4"
115};
116
117static const char * const spm_parents[] = {
118 "clk26m",
119 "ulposc1_d10",
120 "mainpll_d7_d4",
121 "clk32k"
122};
123
124static const char * const scp_parents[] = {
125 "clk26m",
126 "univpll_d4",
127 "mainpll_d6",
128 "univpll_d6",
129 "univpll_d4_d2",
130 "mainpll_d4_d2",
131 "univpll_d3",
132 "mainpll_d3"
133};
134
135static const char * const bus_aximem_parents[] = {
136 "clk26m",
137 "mainpll_d7_d2",
138 "mainpll_d4_d2",
139 "mainpll_d5_d2",
140 "mainpll_d6"
141};
142
143static const char * const vpp_parents[] = {
144 "clk26m",
145 "univpll_d6_d2",
146 "mainpll_d5_d2",
147 "mmpll_d6_d2",
148 "univpll_d5_d2",
149 "univpll_d4_d2",
150 "mmpll_d4_d2",
151 "mmpll_d7",
152 "univpll_d6",
153 "mainpll_d4",
154 "mmpll_d5",
155 "tvdpll1",
156 "tvdpll2",
157 "univpll_d4",
158 "mmpll_d4"
159};
160
161static const char * const ethdr_parents[] = {
162 "clk26m",
163 "univpll_d6_d2",
164 "mainpll_d5_d2",
165 "mmpll_d6_d2",
166 "univpll_d5_d2",
167 "univpll_d4_d2",
168 "mmpll_d4_d2",
169 "mmpll_d7",
170 "univpll_d6",
171 "mainpll_d4",
172 "mmpll_d5_d4",
173 "tvdpll1",
174 "tvdpll2",
175 "univpll_d4",
176 "mmpll_d4"
177};
178
179static const char * const ipe_parents[] = {
180 "clk26m",
181 "imgpll",
182 "mainpll_d4",
183 "mmpll_d6",
184 "univpll_d6",
185 "mainpll_d6",
186 "mmpll_d4_d2",
187 "univpll_d4_d2",
188 "mainpll_d4_d2",
189 "mmpll_d6_d2",
190 "univpll_d5_d2",
191 "mainpll_d7"
192};
193
194static const char * const cam_parents[] = {
195 "clk26m",
196 "tvdpll1",
197 "mainpll_d4",
198 "mmpll_d4",
199 "univpll_d4",
200 "univpll_d5",
201 "univpll_d6",
202 "mmpll_d7",
203 "univpll_d4_d2",
204 "mainpll_d4_d2",
205 "imgpll"
206};
207
208static const char * const ccu_parents[] = {
209 "clk26m",
210 "univpll_d6",
211 "mainpll_d4_d2",
212 "mainpll_d4",
213 "univpll_d5",
214 "mainpll_d6",
215 "mmpll_d6",
216 "mmpll_d7",
217 "univpll_d4_d2",
218 "univpll_d7"
219};
220
221static const char * const ccu_ahb_parents[] = {
222 "clk26m",
223 "univpll_d6",
224 "mainpll_d4_d2",
225 "mainpll_d4",
226 "univpll_d5",
227 "mainpll_d6",
228 "mmpll_d6",
229 "mmpll_d7",
230 "univpll_d4_d2",
231 "univpll_d7"
232};
233
234static const char * const img_parents[] = {
235 "clk26m",
236 "imgpll",
237 "univpll_d4",
238 "mainpll_d4",
239 "univpll_d5",
240 "mmpll_d6",
241 "mmpll_d7",
242 "univpll_d6",
243 "mainpll_d6",
244 "mmpll_d4_d2",
245 "univpll_d4_d2",
246 "mainpll_d4_d2",
247 "univpll_d5_d2"
248};
249
250static const char * const camtm_parents[] = {
251 "clk26m",
252 "univpll_d4_d4",
253 "univpll_d6_d2",
254 "univpll_d6_d4"
255};
256
257static const char * const dsp_parents[] = {
258 "clk26m",
259 "univpll_d6_d2",
260 "univpll_d4_d2",
261 "univpll_d5",
262 "univpll_d4",
263 "mmpll_d4",
264 "mainpll_d3",
265 "univpll_d3"
266};
267
268static const char * const dsp1_parents[] = {
269 "clk26m",
270 "univpll_d6_d2",
271 "mainpll_d4_d2",
272 "univpll_d5",
273 "mmpll_d5",
274 "univpll_d4",
275 "mainpll_d3",
276 "univpll_d3"
277};
278
279static const char * const dsp2_parents[] = {
280 "clk26m",
281 "univpll_d6_d2",
282 "mainpll_d4_d2",
283 "univpll_d5",
284 "mmpll_d5",
285 "univpll_d4",
286 "mainpll_d3",
287 "univpll_d3"
288};
289
290static const char * const dsp3_parents[] = {
291 "clk26m",
292 "univpll_d6_d2",
293 "mainpll_d4_d2",
294 "univpll_d5",
295 "mmpll_d5",
296 "univpll_d4",
297 "mainpll_d3",
298 "univpll_d3"
299};
300
301static const char * const dsp4_parents[] = {
302 "clk26m",
303 "univpll_d6_d2",
304 "univpll_d4_d2",
305 "mainpll_d4",
306 "univpll_d4",
307 "mmpll_d4",
308 "mainpll_d3",
309 "univpll_d3"
310};
311
312static const char * const dsp5_parents[] = {
313 "clk26m",
314 "univpll_d6_d2",
315 "univpll_d4_d2",
316 "mainpll_d4",
317 "univpll_d4",
318 "mmpll_d4",
319 "mainpll_d3",
320 "univpll_d3"
321};
322
323static const char * const dsp6_parents[] = {
324 "clk26m",
325 "univpll_d6_d2",
326 "univpll_d4_d2",
327 "mainpll_d4",
328 "univpll_d4",
329 "mmpll_d4",
330 "mainpll_d3",
331 "univpll_d3"
332};
333
334static const char * const dsp7_parents[] = {
335 "clk26m",
336 "univpll_d6_d2",
337 "univpll_d4_d2",
338 "univpll_d5",
339 "univpll_d4",
340 "mmpll_d4",
341 "mainpll_d3",
342 "univpll_d3"
343};
344
345static const char * const mfg_core_tmp_parents[] = {
346 "clk26m",
347 "mainpll_d5_d2",
348 "univpll_d6",
349 "univpll_d7"
350};
351
352static const char * const camtg_parents[] = {
353 "clk26m",
354 "univpll_192m_d8",
355 "univpll_d6_d8",
356 "univpll_192m_d4",
357 "univpll_192m_d10",
358 "clk13m",
359 "univpll_192m_d16",
360 "univpll_192m_d32"
361};
362
363static const char * const camtg2_parents[] = {
364 "clk26m",
365 "univpll_192m_d8",
366 "univpll_d6_d8",
367 "univpll_192m_d4",
368 "univpll_192m_d10",
369 "clk13m",
370 "univpll_192m_d16",
371 "univpll_192m_d32"
372};
373
374static const char * const camtg3_parents[] = {
375 "clk26m",
376 "univpll_192m_d8",
377 "univpll_d6_d8",
378 "univpll_192m_d4",
379 "univpll_192m_d10",
380 "clk13m",
381 "univpll_192m_d16",
382 "univpll_192m_d32"
383};
384
385static const char * const uart_parents[] = {
386 "clk26m",
387 "univpll_d6_d8"
388};
389
390static const char * const spi_parents[] = {
391 "clk26m",
392 "mainpll_d5_d4",
393 "mainpll_d6_d4",
394 "univpll_d6_d4",
395 "univpll_d6_d2",
396 "mainpll_d6_d2",
397 "mainpll_d4_d4",
398 "univpll_d5_d4"
399};
400
401static const char * const msdc5hclk_parents[] = {
402 "clk26m",
403 "mainpll_d4_d2",
404 "mainpll_d6_d2"
405};
406
407static const char * const msdc50_0_parents[] = {
408 "clk26m",
409 "msdcpll",
410 "msdcpll_d2",
411 "univpll_d4_d4",
412 "mainpll_d6_d2",
413 "univpll_d4_d2"
414};
415
416static const char * const msdc30_1_parents[] = {
417 "clk26m",
418 "univpll_d6_d2",
419 "mainpll_d6_d2",
420 "mainpll_d7_d2",
421 "msdcpll_d2"
422};
423
424static const char * const msdc30_2_parents[] = {
425 "clk26m",
426 "univpll_d6_d2",
427 "mainpll_d6_d2",
428 "mainpll_d7_d2",
429 "msdcpll_d2"
430};
431
432static const char * const intdir_parents[] = {
433 "clk26m",
434 "univpll_d6",
435 "mainpll_d4",
436 "univpll_d4"
437};
438
439static const char * const aud_intbus_parents[] = {
440 "clk26m",
441 "mainpll_d4_d4",
442 "mainpll_d7_d4"
443};
444
445static const char * const audio_h_parents[] = {
446 "clk26m",
447 "univpll_d7",
448 "apll1",
449 "apll2"
450};
451
452static const char * const pwrap_ulposc_parents[] = {
453 "clk26m",
454 "ulposc1_d10",
455 "ulposc1_d7",
456 "ulposc1_d8",
457 "ulposc1_d16",
458 "mainpll_d4_d8",
459 "univpll_d5_d8",
460 "tvdpll1_d16"
461};
462
463static const char * const atb_parents[] = {
464 "clk26m",
465 "mainpll_d4_d2",
466 "mainpll_d5_d2"
467};
468
469static const char * const sspm_parents[] = {
470 "clk26m",
471 "mainpll_d7_d2",
472 "mainpll_d6_d2",
473 "mainpll_d5_d2",
474 "mainpll_d9",
475 "mainpll_d4_d2"
476};
477
478/*
479 * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using
480 * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate
481 * in dual output case, which would lead to corruption of functionality loss.
482 */
483static const char * const dp_parents[] = {
484 "clk26m",
485 "tvdpll2_d2",
486 "tvdpll2_d4",
487 "tvdpll2_d8",
488 "tvdpll2_d16"
489};
490static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };
491
492static const char * const edp_parents[] = {
493 "clk26m",
494 "tvdpll1_d2",
495 "tvdpll1_d4",
496 "tvdpll1_d8",
497 "tvdpll1_d16"
498};
499static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };
500
501static const char * const dpi_parents[] = {
502 "clk26m",
503 "tvdpll1_d2",
504 "tvdpll2_d2",
505 "tvdpll1_d4",
506 "tvdpll2_d4",
507 "tvdpll1_d8",
508 "tvdpll2_d8",
509 "tvdpll1_d16",
510 "tvdpll2_d16"
511};
512
513static const char * const disp_pwm0_parents[] = {
514 "clk26m",
515 "univpll_d6_d4",
516 "ulposc1_d2",
517 "ulposc1_d4",
518 "ulposc1_d16",
519 "ethpll_d4"
520};
521
522static const char * const disp_pwm1_parents[] = {
523 "clk26m",
524 "univpll_d6_d4",
525 "ulposc1_d2",
526 "ulposc1_d4",
527 "ulposc1_d16"
528};
529
530static const char * const usb_parents[] = {
531 "clk26m",
532 "univpll_d5_d4",
533 "univpll_d6_d4",
534 "univpll_d5_d2"
535};
536
537static const char * const ssusb_xhci_parents[] = {
538 "clk26m",
539 "univpll_d5_d4",
540 "univpll_d6_d4",
541 "univpll_d5_d2"
542};
543
544static const char * const usb_2p_parents[] = {
545 "clk26m",
546 "univpll_d5_d4",
547 "univpll_d6_d4",
548 "univpll_d5_d2"
549};
550
551static const char * const ssusb_xhci_2p_parents[] = {
552 "clk26m",
553 "univpll_d5_d4",
554 "univpll_d6_d4",
555 "univpll_d5_d2"
556};
557
558static const char * const usb_3p_parents[] = {
559 "clk26m",
560 "univpll_d5_d4",
561 "univpll_d6_d4",
562 "univpll_d5_d2"
563};
564
565static const char * const ssusb_xhci_3p_parents[] = {
566 "clk26m",
567 "univpll_d5_d4",
568 "univpll_d6_d4",
569 "univpll_d5_d2"
570};
571
572static const char * const i2c_parents[] = {
573 "clk26m",
574 "mainpll_d4_d8",
575 "univpll_d5_d4"
576};
577
578static const char * const seninf_parents[] = {
579 "clk26m",
580 "univpll_d4_d4",
581 "univpll_d6_d2",
582 "mainpll_d4_d2",
583 "univpll_d7",
584 "univpll_d6",
585 "mmpll_d6",
586 "univpll_d5"
587};
588
589static const char * const seninf1_parents[] = {
590 "clk26m",
591 "univpll_d4_d4",
592 "univpll_d6_d2",
593 "mainpll_d4_d2",
594 "univpll_d7",
595 "univpll_d6",
596 "mmpll_d6",
597 "univpll_d5"
598};
599
600static const char * const gcpu_parents[] = {
601 "clk26m",
602 "mainpll_d6",
603 "univpll_d4_d2",
604 "mmpll_d5_d2",
605 "univpll_d5_d2"
606};
607
608static const char * const venc_parents[] = {
609 "clk26m",
610 "mmpll_d4_d2",
611 "mainpll_d6",
612 "univpll_d4_d2",
613 "mainpll_d4_d2",
614 "univpll_d6",
615 "mmpll_d6",
616 "mainpll_d5_d2",
617 "mainpll_d6_d2",
618 "mmpll_d9",
619 "univpll_d4_d4",
620 "mainpll_d4",
621 "univpll_d4",
622 "univpll_d5",
623 "univpll_d5_d2",
624 "mainpll_d5"
625};
626
627static const char * const vdec_parents[] = {
628 "clk26m",
629 "mainpll_d5_d2",
630 "mmpll_d6_d2",
631 "univpll_d5_d2",
632 "univpll_d4_d2",
633 "mmpll_d4_d2",
634 "univpll_d6",
635 "mainpll_d5",
636 "univpll_d5",
637 "mmpll_d6",
638 "mainpll_d4",
639 "tvdpll2",
640 "univpll_d4",
641 "imgpll",
642 "univpll_d6_d2",
643 "mmpll_d9"
644};
645
646static const char * const pwm_parents[] = {
647 "clk32k",
648 "clk26m",
649 "univpll_d4_d8",
650 "univpll_d6_d4"
651};
652
653static const char * const mcupm_parents[] = {
654 "clk26m",
655 "mainpll_d6_d2",
656 "mainpll_d7_d4"
657};
658
659static const char * const spmi_p_mst_parents[] = {
660 "clk26m",
661 "clk13m",
662 "ulposc1_d8",
663 "ulposc1_d10",
664 "ulposc1_d16",
665 "ulposc1_d7",
666 "clk32k",
667 "mainpll_d7_d8",
668 "mainpll_d6_d8",
669 "mainpll_d5_d8"
670};
671
672static const char * const spmi_m_mst_parents[] = {
673 "clk26m",
674 "clk13m",
675 "ulposc1_d8",
676 "ulposc1_d10",
677 "ulposc1_d16",
678 "ulposc1_d7",
679 "clk32k",
680 "mainpll_d7_d8",
681 "mainpll_d6_d8",
682 "mainpll_d5_d8"
683};
684
685static const char * const dvfsrc_parents[] = {
686 "clk26m",
687 "ulposc1_d10",
688 "univpll_d6_d8",
689 "msdcpll_d16"
690};
691
692static const char * const tl_parents[] = {
693 "clk26m",
694 "univpll_d5_d4",
695 "mainpll_d4_d4"
696};
697
698static const char * const aes_msdcfde_parents[] = {
699 "clk26m",
700 "mainpll_d4_d2",
701 "mainpll_d6",
702 "mainpll_d4_d4",
703 "univpll_d4_d2",
704 "univpll_d6"
705};
706
707static const char * const dsi_occ_parents[] = {
708 "clk26m",
709 "univpll_d6_d2",
710 "univpll_d5_d2",
711 "univpll_d4_d2"
712};
713
714static const char * const wpe_vpp_parents[] = {
715 "clk26m",
716 "mainpll_d5_d2",
717 "mmpll_d6_d2",
718 "univpll_d5_d2",
719 "mainpll_d4_d2",
720 "univpll_d4_d2",
721 "mmpll_d4_d2",
722 "mainpll_d6",
723 "mmpll_d7",
724 "univpll_d6",
725 "mainpll_d5",
726 "univpll_d5",
727 "mainpll_d4",
728 "tvdpll1",
729 "univpll_d4"
730};
731
732static const char * const hdcp_parents[] = {
733 "clk26m",
734 "univpll_d4_d8",
735 "mainpll_d5_d8",
736 "univpll_d6_d4"
737};
738
739static const char * const hdcp_24m_parents[] = {
740 "clk26m",
741 "univpll_192m_d4",
742 "univpll_192m_d8",
743 "univpll_d6_d8"
744};
745
746static const char * const hdmi_apb_parents[] = {
747 "clk26m",
748 "univpll_d6_d4",
749 "msdcpll_d2"
750};
751
752static const char * const snps_eth_250m_parents[] = {
753 "clk26m",
754 "ethpll_d2"
755};
756
757static const char * const snps_eth_62p4m_ptp_parents[] = {
758 "apll2_d3",
759 "apll1_d3",
760 "clk26m",
761 "ethpll_d8"
762};
763
764static const char * const snps_eth_50m_rmii_parents[] = {
765 "clk26m",
766 "ethpll_d10"
767};
768
769static const char * const adsp_parents[] = {
770 "clk26m",
771 "clk13m",
772 "mainpll_d6",
773 "mainpll_d5_d2",
774 "univpll_d4_d4",
775 "univpll_d4",
776 "ulposc1_d2",
777 "ulposc1_ck1",
778 "adsppll",
779 "adsppll_d2",
780 "adsppll_d4",
781 "adsppll_d8"
782};
783
784static const char * const audio_local_bus_parents[] = {
785 "clk26m",
786 "clk13m",
787 "mainpll_d4_d4",
788 "mainpll_d7_d2",
789 "mainpll_d5_d2",
790 "mainpll_d4_d2",
791 "mainpll_d7",
792 "mainpll_d4",
793 "univpll_d6",
794 "ulposc1_ck1",
795 "ulposc1_d4",
796 "ulposc1_d2"
797};
798
799static const char * const asm_h_parents[] = {
800 "clk26m",
801 "univpll_d6_d4",
802 "univpll_d6_d2",
803 "mainpll_d5_d2"
804};
805
806static const char * const asm_l_parents[] = {
807 "clk26m",
808 "univpll_d6_d4",
809 "univpll_d6_d2",
810 "mainpll_d5_d2"
811};
812
813static const char * const apll1_parents[] = {
814 "clk26m",
815 "apll1_d4"
816};
817
818static const char * const apll2_parents[] = {
819 "clk26m",
820 "apll2_d4"
821};
822
823static const char * const apll3_parents[] = {
824 "clk26m",
825 "apll3_d4"
826};
827
828static const char * const apll4_parents[] = {
829 "clk26m",
830 "apll4_d4"
831};
832
833static const char * const apll5_parents[] = {
834 "clk26m",
835 "apll5_d4"
836};
837
838static const char * const i2so1_parents[] = {
839 "clk26m",
840 "apll1",
841 "apll2",
842 "apll3",
843 "apll4",
844 "apll5"
845};
846
847static const char * const i2so2_parents[] = {
848 "clk26m",
849 "apll1",
850 "apll2",
851 "apll3",
852 "apll4",
853 "apll5"
854};
855
856static const char * const i2si1_parents[] = {
857 "clk26m",
858 "apll1",
859 "apll2",
860 "apll3",
861 "apll4",
862 "apll5"
863};
864
865static const char * const i2si2_parents[] = {
866 "clk26m",
867 "apll1",
868 "apll2",
869 "apll3",
870 "apll4",
871 "apll5"
872};
873
874static const char * const dptx_parents[] = {
875 "clk26m",
876 "apll1",
877 "apll2",
878 "apll3",
879 "apll4",
880 "apll5"
881};
882
883static const char * const aud_iec_parents[] = {
884 "clk26m",
885 "apll1",
886 "apll2",
887 "apll3",
888 "apll4",
889 "apll5"
890};
891
892static const char * const a1sys_hp_parents[] = {
893 "clk26m",
894 "apll1_d4"
895};
896
897static const char * const a2sys_parents[] = {
898 "clk26m",
899 "apll2_d4"
900};
901
902static const char * const a3sys_parents[] = {
903 "clk26m",
904 "apll3_d4",
905 "apll4_d4",
906 "apll5_d4"
907};
908
909static const char * const a4sys_parents[] = {
910 "clk26m",
911 "apll3_d4",
912 "apll4_d4",
913 "apll5_d4"
914};
915
916static const char * const ecc_parents[] = {
917 "clk26m",
918 "mainpll_d4_d4",
919 "mainpll_d5_d2",
920 "mainpll_d4_d2",
921 "mainpll_d6",
922 "univpll_d6"
923};
924
925static const char * const spinor_parents[] = {
926 "clk26m",
927 "clk13m",
928 "mainpll_d7_d8",
929 "univpll_d6_d8"
930};
931
932static const char * const ulposc_parents[] = {
933 "ulposc_ck1",
934 "ethpll_d2",
935 "mainpll_d4_d2",
936 "ethpll_d10"
937};
938
939static const char * const srck_parents[] = {
940 "ulposc1_d10",
941 "clk26m"
942};
943
944static const char * const mfg_fast_ref_parents[] = {
945 "top_mfg_core_tmp",
946 "mfgpll"
947};
948
949static const struct mtk_mux top_mtk_muxes[] = {
950 /*
951 * CLK_CFG_0
952 * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux.
953 * spm_sel and scp_sel are main clocks in always-on co-processor.
954 */
955 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
956 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0,
957 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
958 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
959 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1,
960 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
961 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
962 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2,
963 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
964 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents,
965 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3,
966 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
967 /* CLK_CFG_1 */
968 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
969 vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
970 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
971 ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
972 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
973 ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
974 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
975 cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
976 /* CLK_CFG_2 */
977 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
978 ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
979 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
980 ccu_ahb_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
981 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
982 img_parents, 0x038, 0x03C, 0x040, 16, 4, 23, 0x04, 10),
983 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
984 camtm_parents, 0x038, 0x03C, 0x040, 24, 4, 31, 0x04, 11),
985 /* CLK_CFG_3 */
986 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
987 dsp_parents, 0x044, 0x048, 0x04C, 0, 4, 7, 0x04, 12),
988 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
989 dsp1_parents, 0x044, 0x048, 0x04C, 8, 4, 15, 0x04, 13),
990 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
991 dsp2_parents, 0x044, 0x048, 0x04C, 16, 4, 23, 0x04, 14),
992 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
993 dsp3_parents, 0x044, 0x048, 0x04C, 24, 4, 31, 0x04, 15),
994 /* CLK_CFG_4 */
995 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
996 dsp4_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16),
997 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
998 dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17),
999 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
1000 dsp6_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18),
1001 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
1002 dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19),
1003 /* CLK_CFG_5 */
1004 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
1005 mfg_core_tmp_parents, 0x05C, 0x060, 0x064, 0, 4, 7, 0x04, 20),
1006 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
1007 camtg_parents, 0x05C, 0x060, 0x064, 8, 4, 15, 0x04, 21),
1008 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
1009 camtg2_parents, 0x05C, 0x060, 0x064, 16, 4, 23, 0x04, 22),
1010 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
1011 camtg3_parents, 0x05C, 0x060, 0x064, 24, 4, 31, 0x04, 23),
1012 /* CLK_CFG_6 */
1013 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
1014 uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
1015 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
1016 spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
1017 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
1018 msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26, 0),
1019 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
1020 msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27, 0),
1021 /* CLK_CFG_7 */
1022 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
1023 msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28, 0),
1024 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
1025 msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29, 0),
1026 MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
1027 intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
1028 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
1029 aud_intbus_parents, 0x074, 0x078, 0x07C, 24, 4, 31, 0x04, 31),
1030 /* CLK_CFG_8 */
1031 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
1032 audio_h_parents, 0x080, 0x084, 0x088, 0, 4, 7, 0x08, 0),
1033 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
1034 pwrap_ulposc_parents, 0x080, 0x084, 0x088, 8, 4, 15, 0x08, 1),
1035 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
1036 atb_parents, 0x080, 0x084, 0x088, 16, 4, 23, 0x08, 2),
1037 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
1038 sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),
1039 /* CLK_CFG_9 */
1040 MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",
1041 dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094,
1042 0, 4, 7, 0x08, 4),
1043 MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",
1044 edp_parents, edp_parents_idx, 0x08C, 0x090, 0x094,
1045 8, 4, 15, 0x08, 5),
1046 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
1047 dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),
1048 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
1049 disp_pwm0_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
1050 /* CLK_CFG_10 */
1051 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
1052 disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
1053 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
1054 usb_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
1055 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
1056 ssusb_xhci_parents, 0x098, 0x09C, 0x0A0, 16, 4, 23, 0x08, 10),
1057 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
1058 usb_2p_parents, 0x098, 0x09C, 0x0A0, 24, 4, 31, 0x08, 11),
1059 /* CLK_CFG_11 */
1060 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
1061 ssusb_xhci_2p_parents, 0x0A4, 0x0A8, 0x0AC, 0, 4, 7, 0x08, 12),
1062 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
1063 usb_3p_parents, 0x0A4, 0x0A8, 0x0AC, 8, 4, 15, 0x08, 13),
1064 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
1065 ssusb_xhci_3p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 4, 23, 0x08, 14),
1066 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
1067 i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24, 4, 31, 0x08, 15),
1068 /* CLK_CFG_12 */
1069 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
1070 seninf_parents, 0x0B0, 0x0B4, 0x0B8, 0, 4, 7, 0x08, 16),
1071 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
1072 seninf1_parents, 0x0B0, 0x0B4, 0x0B8, 8, 4, 15, 0x08, 17),
1073 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1074 gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16, 4, 23, 0x08, 18),
1075 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1076 venc_parents, 0x0B0, 0x0B4, 0x0B8, 24, 4, 31, 0x08, 19),
1077 /*
1078 * CLK_CFG_13
1079 * top_mcupm is main clock in co-processor, should not be handled by Linux.
1080 */
1081 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1082 vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0, 4, 7, 0x08, 20),
1083 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1084 pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
1085 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents,
1086 0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22,
1087 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1088 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1089 spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23),
1090 /*
1091 * CLK_CFG_14
1092 * dvfsrc_sel is for internal DVFS usage, should not be handled by Linux.
1093 */
1094 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1095 spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24),
1096 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
1097 0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25,
1098 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1099 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1100 tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26),
1101 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1102 aes_msdcfde_parents, 0x0C8, 0x0CC, 0x0D0, 24, 4, 31, 0x08, 27),
1103 /* CLK_CFG_15 */
1104 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1105 dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC, 0, 4, 7, 0x08, 28),
1106 MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1107 wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC, 8, 4, 15, 0x08, 29),
1108 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1109 hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16, 4, 23, 0x08, 30),
1110 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1111 hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC, 24, 4, 31, 0x08, 31),
1112 /* CLK_CFG_16 */
1113 MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1114 hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1115 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1116 snps_eth_250m_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1117 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1118 snps_eth_62p4m_ptp_parents, 0x0E0, 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2),
1119 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1120 snps_eth_50m_rmii_parents, 0x0E0, 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3),
1121 /* CLK_CFG_17 */
1122 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1123 adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1124 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1125 audio_local_bus_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1126 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1127 asm_h_parents, 0x0EC, 0x0F0, 0x0F4, 16, 4, 23, 0x0C, 6),
1128 MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1129 asm_l_parents, 0x0EC, 0x0F0, 0x0F4, 24, 4, 31, 0x0C, 7),
1130 /* CLK_CFG_18 */
1131 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1132 apll1_parents, 0x0F8, 0x0FC, 0x100, 0, 4, 7, 0x0C, 8),
1133 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1134 apll2_parents, 0x0F8, 0x0FC, 0x100, 8, 4, 15, 0x0C, 9),
1135 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1136 apll3_parents, 0x0F8, 0x0FC, 0x100, 16, 4, 23, 0x0C, 10),
1137 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1138 apll4_parents, 0x0F8, 0x0FC, 0x100, 24, 4, 31, 0x0C, 11),
1139 /* CLK_CFG_19 */
1140 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1141 apll5_parents, 0x0104, 0x0108, 0x010C, 0, 4, 7, 0x0C, 12),
1142 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
1143 i2so1_parents, 0x0104, 0x0108, 0x010C, 8, 4, 15, 0x0C, 13),
1144 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
1145 i2so2_parents, 0x0104, 0x0108, 0x010C, 16, 4, 23, 0x0C, 14),
1146 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
1147 i2si1_parents, 0x0104, 0x0108, 0x010C, 24, 4, 31, 0x0C, 15),
1148 /* CLK_CFG_20 */
1149 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
1150 i2si2_parents, 0x0110, 0x0114, 0x0118, 0, 4, 7, 0x0C, 16),
1151 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
1152 dptx_parents, 0x0110, 0x0114, 0x0118, 8, 4, 15, 0x0C, 17),
1153 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
1154 aud_iec_parents, 0x0110, 0x0114, 0x0118, 16, 4, 23, 0x0C, 18),
1155 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1156 a1sys_hp_parents, 0x0110, 0x0114, 0x0118, 24, 4, 31, 0x0C, 19),
1157 /* CLK_CFG_21 */
1158 MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
1159 a2sys_parents, 0x011C, 0x0120, 0x0124, 0, 4, 7, 0x0C, 20),
1160 MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
1161 a3sys_parents, 0x011C, 0x0120, 0x0124, 8, 4, 15, 0x0C, 21),
1162 MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
1163 a4sys_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1164 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1165 ecc_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1166 /*
1167 * CLK_CFG_22
1168 * top_ulposc/top_srck are clock source of always on co-processor,
1169 * should not be closed by Linux.
1170 */
1171 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1172 spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1173 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents,
1174 0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25,
1175 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1176 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
1177 0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26,
1178 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1179};
1180
1181static const struct mtk_composite top_adj_divs[] = {
1182 DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
1183 DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
1184 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
1185 DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "top_i2so2", 0x0320, 3, 0x0328, 8, 24),
1186 DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
1187 DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8),
1188};
1189static const struct mtk_gate_regs top0_cg_regs = {
1190 .set_ofs = 0x238,
1191 .clr_ofs = 0x238,
1192 .sta_ofs = 0x238,
1193};
1194
1195static const struct mtk_gate_regs top1_cg_regs = {
1196 .set_ofs = 0x250,
1197 .clr_ofs = 0x250,
1198 .sta_ofs = 0x250,
1199};
1200
1201#define GATE_TOP0(_id, _name, _parent, _shift) \
1202 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1203
1204#define GATE_TOP1(_id, _name, _parent, _shift) \
1205 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1206
1207static const struct mtk_gate top_clks[] = {
1208 /* TOP0 */
1209 GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, "cfgreg_clock_vpp0", "top_vpp", 0),
1210 GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, "cfgreg_clock_vpp1", "top_vpp", 1),
1211 GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, "cfgreg_clock_vdo0", "top_vpp", 2),
1212 GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, "cfgreg_clock_vdo1", "top_vpp", 3),
1213 GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, "cfgreg_clock_isp_axi_gals", "top_vpp", 4),
1214 GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0", "clk26m", 5),
1215 GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1", "clk26m", 6),
1216 GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0", "clk26m", 7),
1217 GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1", "clk26m", 8),
1218 GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, "cfgreg_aud_f26m_aud", "clk26m", 9),
1219 GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses", "univpll_d2", 15),
1220 GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, "cfgreg_f_pcie_phy_ref", "clk26m", 18),
1221 /* TOP1 */
1222 GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0),
1223 GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1224 GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1225 GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1226 GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1227 GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1228 GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1229 GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1230};
1231
1232static const struct of_device_id of_match_clk_mt8188_topck[] = {
1233 { .compatible = "mediatek,mt8188-topckgen" },
1234 { /* sentinel */ }
1235};
1236MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_topck);
1237
1238/* Register mux notifier for MFG mux */
1239static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1240{
1241 struct mtk_mux_nb *mfg_mux_nb;
1242
1243 mfg_mux_nb = devm_kzalloc(dev, size: sizeof(*mfg_mux_nb), GFP_KERNEL);
1244 if (!mfg_mux_nb)
1245 return -ENOMEM;
1246
1247 mfg_mux_nb->ops = &clk_mux_ops;
1248 mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
1249
1250 return devm_mtk_clk_mux_notifier_register(dev, clk, mux_nb: mfg_mux_nb);
1251}
1252
1253static int clk_mt8188_topck_probe(struct platform_device *pdev)
1254{
1255 struct clk_hw_onecell_data *top_clk_data;
1256 struct device_node *node = pdev->dev.of_node;
1257 struct clk_hw *hw;
1258 int r;
1259 void __iomem *base;
1260
1261 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1262 if (!top_clk_data)
1263 return -ENOMEM;
1264
1265 base = devm_platform_ioremap_resource(pdev, index: 0);
1266 if (IS_ERR(ptr: base)) {
1267 r = PTR_ERR(ptr: base);
1268 goto free_top_data;
1269 }
1270
1271 r = mtk_clk_register_fixed_clks(clks: top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1272 clk_data: top_clk_data);
1273 if (r)
1274 goto free_top_data;
1275
1276 r = mtk_clk_register_factors(clks: top_divs, ARRAY_SIZE(top_divs), clk_data: top_clk_data);
1277 if (r)
1278 goto unregister_fixed_clks;
1279
1280 r = mtk_clk_register_muxes(dev: &pdev->dev, muxes: top_mtk_muxes,
1281 ARRAY_SIZE(top_mtk_muxes), node,
1282 lock: &mt8188_clk_lock, clk_data: top_clk_data);
1283 if (r)
1284 goto unregister_factors;
1285
1286 hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_ref_parents,
1287 ARRAY_SIZE(mfg_fast_ref_parents), CLK_SET_RATE_PARENT,
1288 (base + 0x250), 8, 1, 0, &mt8188_clk_lock);
1289 if (IS_ERR(ptr: hw)) {
1290 r = PTR_ERR(ptr: hw);
1291 goto unregister_muxes;
1292 }
1293 top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
1294
1295 r = clk_mt8188_reg_mfg_mux_notifier(dev: &pdev->dev,
1296 clk: top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
1297 if (r)
1298 goto unregister_muxes;
1299
1300 r = mtk_clk_register_composites(dev: &pdev->dev, mcs: top_adj_divs,
1301 ARRAY_SIZE(top_adj_divs), base,
1302 lock: &mt8188_clk_lock, clk_data: top_clk_data);
1303 if (r)
1304 goto unregister_muxes;
1305
1306 r = mtk_clk_register_gates(dev: &pdev->dev, node, clks: top_clks,
1307 ARRAY_SIZE(top_clks), clk_data: top_clk_data);
1308 if (r)
1309 goto unregister_composite_divs;
1310
1311 r = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, data: top_clk_data);
1312 if (r)
1313 goto unregister_gates;
1314
1315 platform_set_drvdata(pdev, data: top_clk_data);
1316
1317 return r;
1318
1319unregister_gates:
1320 mtk_clk_unregister_gates(clks: top_clks, ARRAY_SIZE(top_clks), clk_data: top_clk_data);
1321unregister_composite_divs:
1322 mtk_clk_unregister_composites(mcs: top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data: top_clk_data);
1323unregister_muxes:
1324 mtk_clk_unregister_muxes(muxes: top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data: top_clk_data);
1325unregister_factors:
1326 mtk_clk_unregister_factors(clks: top_divs, ARRAY_SIZE(top_divs), clk_data: top_clk_data);
1327unregister_fixed_clks:
1328 mtk_clk_unregister_fixed_clks(clks: top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data: top_clk_data);
1329free_top_data:
1330 mtk_free_clk_data(clk_data: top_clk_data);
1331 return r;
1332}
1333
1334static void clk_mt8188_topck_remove(struct platform_device *pdev)
1335{
1336 struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
1337 struct device_node *node = pdev->dev.of_node;
1338
1339 of_clk_del_provider(np: node);
1340 mtk_clk_unregister_gates(clks: top_clks, ARRAY_SIZE(top_clks), clk_data: top_clk_data);
1341 mtk_clk_unregister_composites(mcs: top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data: top_clk_data);
1342 mtk_clk_unregister_muxes(muxes: top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data: top_clk_data);
1343 mtk_clk_unregister_factors(clks: top_divs, ARRAY_SIZE(top_divs), clk_data: top_clk_data);
1344 mtk_clk_unregister_fixed_clks(clks: top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data: top_clk_data);
1345 mtk_free_clk_data(clk_data: top_clk_data);
1346}
1347
1348static struct platform_driver clk_mt8188_topck_drv = {
1349 .probe = clk_mt8188_topck_probe,
1350 .remove_new = clk_mt8188_topck_remove,
1351 .driver = {
1352 .name = "clk-mt8188-topck",
1353 .of_match_table = of_match_clk_mt8188_topck,
1354 },
1355};
1356module_platform_driver(clk_mt8188_topck_drv);
1357MODULE_LICENSE("GPL");
1358

source code of linux/drivers/clk/mediatek/clk-mt8188-topckgen.c